A Study of Implementation of Digital Signal Processing for Adaptive Array Antenna

Transcription

1 MASTER THESIS A Study of Implemetatio of Digital Sigal Processig for Adaptive Array Atea Supervisor: Associate Prof. Hiroyuki ARAI Submitted o Feb., Divisio of Electrical Ad Computer Egieerig, Yokohama Natioal Uiversity, Japa DD9 Miseok Kim

2 PREFACE A adaptive array atea techology is paid attetio to a lot of applicatios i the ext geeratio wireless mobile commuicatios. This techology ca form a beam patter at a iteded directio by applyig digital sigal processig algorithms to the digitized sigals from each atea elemet. It has had some barriers i commercial uses due to implemetatio complexities ad impractically high costs, but advaces i digital device techologies have led to solve the implemetatio difficulties due to the oliearity of a aalog device with a digital sigal processig. This paper describes the developmet of a evaluatio prototype system for adaptive array atea test bed to realize reasoable cost ad high performace. Ad the it presets the examiatio of their applicatios. This paper cosists of 3 mai parts: first, a desig of digital prototype system; secod, a beamformig atea as a applicatio; third, a DOA (Directio Of Arrival estimatio system as the other applicatio. I Chapter the hardware cofiguratio ad the desig of the digital prototype board that we developed cosiderig the architecture of software defied radio (SDR are described. I Chapter 3 ad Chapter 4 the examiatios of the applicatio implemetatio usig this prototype system are discussed. Chapter 3 presets the beamformig techique by MRC (Maximum Ratio Combiig. It recombies the output power at maximal ratio by co-phasig received sigals at each elemet like a phased array atea. I this chapter, the circuit implemetatio details ad the experimetal results are preseted. The digital calibratio methods of errors i adaptive array atea system caused by o-ideal atea patter, mutual couplig betwee each elemet ad etc are proposed ad the circuit implemetatios of them are also preseted. O the other had, Chapter 4 deals with the implemetatio issue of DOA estimatio problem. As a matter of fact, it is sigificat to recogize previously the trasmissio coditios ad the eviromet of radio wave so as to model a multi-sigal propagatio efficietly ad form beampatter properly. Moreover to form beams at some directios, most of beamformig algorithms eed the kowledge of DOAs of icidet waves i advace. Geerally the DOA algorithm is very complex ad has heavy computatioal load. From this poit of view, the high performace DOA estimatio system is very useful i the array atea techology. I Chapter 4 the hardware implemetatio of MUSIC (MUltiple SIgal Classificatio method, a super-resolutio DOA estimatio method, is discussed. Especially the EVD (Eige Value Decompositio process that takes the largest computatioal load i the whole system is maily focused ad the circuit cofiguratio, the estimate of circuit scale ad the expected performace are examied. Fially, Chapter 5 summarizes ad cocludes this paper. ii

3 TABLE OF CONTENTS CHAPTER INTRODUCTION.... BACKGROUND.... SURVEY OF ADAPTIVE ANTENNA..... Overview..... Basic Cofiguratio ad Priciple Performace Improvemets OBJECTIVE AND STRUCTURE OF PAPER IMPLEMENTATION ISSUES ON ADAPTIVE ARRAY SIGNAL PROCESSING AND FPGA (FIELD PROGRAMMABLE GATE ARRAY Basic Descriptios of a FPGA Digital Sigal Processig o FPGAs... 9 CHAPTER DESIGN OF DIGITAL PROTOTYPE OF ADAPTIVE ANTENNA RECEIVER.... INTRODUCTION.... ARCHITECTURES OF ADAPTIVE ANTENNA SYSTEM..... Basebad Samplig Architecture..... IF (Itermediate Frequecy Samplig Architecture Future Treds ad Software Defied Radio (SDR DEVELOPMENT OF PROTOTYPE SYSTEM System Cofiguratio Digital Dow Coversio (DDC / Quasi Coheret Detectio NCO ad Mixer Lowpass Filter....4 EXAMINATION OF ANALOG TO DIGITAL SAMPLING SCHEMES Oversamplig Scheme Udersamplig Scheme SUMMARY...5 CHAPTER 3 EXAMINATION OF APPLICATIONS IMPLEMENTATION: MRC BEAMFORMING ANTENNA INTRODUCTION ELEMENT MRC BEAMFORMING ANTENNA HARDWARE IMPLEMENTATION Weight Calculatio / MRC (Maximum Ratio Combiig Processor Circuit Desig / Logic Sythesis (Scale of Circuit... 3 iii

4 3.4 EXPERIMENTAL RESULTS DOA Estimatio ad DOA Trackig Discussio EXAMINATION OF DIGITAL CALIBRATION OF ARRAY ANTENNA Adjustmet by NCO Cotrol Adjustmet by Maximal Ratio Combiig (MRC Discussio SUMMARY...44 CHAPTER 4 EXAMINATION OF APPLICATIONS IMPLEMENTATION: DOA ESTIMATION BY MUSIC METHOD INTRODUCTION PERFORMANCE REQUIREMENT DOA ESTIMATION USING MUSIC METHOD HARDWARE IMPLEMENTATION OF DOA ESTIMATOR USING MUSIC METHOD DESIGN OF EVD PROCESSOR USING JACOBI METHOD BASED ON CORDIC ALGORITHM Cyclic Jacobi Method CORDIC (COordiate Rotatio DIgital Computer Algorithm for Computig Vector Rotatio Examiatio of CORDIC-Jacobi EVD Processor with Fixed Poit Operatio Hardware Desig of EVD Processor Circuit Scale / Expected Performace Discussio SUMMARY...64 CHAPTER 5 SUMMARY AND CONCLUSION ACKNOWLEDGMENTS BIBLIOGRAPHY PUBLICATION LIST iv

5 Chapter Itroductio. Backgroud Wireless Commuicatio techologies have a great progress i recet years ad the markets, especially the cellular telephoe, have bee growig eormously. Moreover the ext geeratio commuicatio services will use higher frequecy bad area ad require more chael capacity ad wider badwidth for a high-speed data commuicatio. As a large icrease i chael capacity ad high trasmissio rates for wireless commuicatios, the techologies for the power savig ad efficiet frequecy usability are required. As a matter of fact i may commuicatio eviromets there are several serious problems such as a multi-path fadig caused by a reflectio by ay physical structures as Fig. -(a. Whe passig through multi-path, the sigals are delayed ad out of phase from the sigals through direct-path, as show i Fig. -(b that causes the sigal stregth to be weakeed at a receiver ad hece receivig quality is also reduced. Geerally it is kow as Raleigh Fadig. Wider bad ad higher trasmissio rate make it more critical problem i the improvemet of the commuicatio quality i the ext geeratio commuicatio. To solve this problem may solutios have bee studied. However it is very importat to cofigure receiver ad trasmitter flexibly i respose to the sigal eviromet recogizig spatial profiles as well as temporal oes. For example spatial diversity techiques usig composite iformatio from the array to miimize fadig ad other udesirable effects of multi-path propagatio have bee studied i may applicatios. Several techiques such as phased array atea ad diversity atea usig active array cofiguratios ca adapt the atea patter accordig to the chage of mobile commuicatio eviromet. However these aalog-based techiques have ay uavoidable problems that are related to difficult cotrol, absece of idividual beam shape cotrol, complex scheme ad correspodig heavy equipmet ad so forth [].

6 Desired BS MS Reflected (a (b Fig. -: (a Effect of Multi-path from a Mobile User ad (b Two Out-of-Phase Multi-path Sigals. Survey of Adaptive Atea.. Overview To meet the requiremets of the ext geeratio wireless commuicatios, a system capable of automatically chagig the directioality of its radiatio patters (beams i respose to its sigal eviromet must be idispesable. This ca oticeably icrease the performace characteristics such as capacity ad quality of a wireless system. I that regards the other alterative is a adaptive atea techology. A Adaptive Atea system uses spatially separated ateas called array atea ad processes received sigals with a digital sigal processor after aalog to digital coversio ad the ame is derived from a Adaptive Filter or Adaptive Filter Sigal Processig. This type of atea that is combied with a digital sigal processor is also called by the ame of Smart Atea or Software Atea or Digital Beamformig Atea (DBF Atea that all mea a itelliget atea differet from a covetioal omi-directioal atea oly receivig ad trasmittig sigals without ay cosideratios []-[4]. O the other had the term of Software Defied Radio (SDR expected as promisig cocept of the ext geeratio radio system seems to be used wider sese. A SDR meas a set of all target processors required for radio commuicatios as well as atea techology [5]. A Adaptive Atea is a part of a Software Defie Radio techology, but the terms are ofte used as if they have a similar meaig with each other. A Adaptive Atea ca be the best explaatio of the meaig of Adaptive Atea techology that it is a approach from a atea i a Software Defie Radio techology ad hece has a close relatioship betwee them i hardware system architecture. This paper makes a rule to use the term Adaptive

7 Atea from the poit of view that it applies digital sigal processig techology to the atea adaptively. A adaptive atea ca form a beam patter at a iteded directio by applyig digital sigal processig algorithm with the digitized data from each atea elemet. By software algorithm this system at the trasmitter is capable of steerig the maximum radiatio patter toward a desired mobile ad the system at the receiver ca spatially separate ad reject multi-path fadig eergy hece higher bit rate services ca be provided [6]. Despite of these advatages, there are some obstacles i commercial uses due to implemetatio complexities ad impractically high costs... Basic Cofiguratio ad Priciple Geerally a adaptive atea system cosists of a lot of fuctios icludig a array atea ad a RF (Radio Frequecy ad IF (Itermediate Frequecy circuitry ad beamformig etwork ad a adaptive cotroller. Fig. - illustrates the basic cofiguratio. A array atea is plural umber of ateas desiged to receive or trasmit sigals usig the combied beampatter. There are various physical arragemets of a array such as liear, circular, rectagular, ad etc. The structure of a array atea is determied i cosideratio of the characteristics ad the applicatios. Most fuctios of the RF/IF circuitry are frequecy dowcoversio, filterig ad amplifyig. The beamformig etwork performs a phase ad amplitude cotrol of iput sigals fed from array atea, which plays a role i combiig beampatter of the array atea operatig as a spatial filter. A adaptive cotroller determies the optimum weight for beamformig. There are various algorithms for obtaiig optimum weight. I a adaptive atea system, the complex structure, heavy hardware, difficulty to recostruct ad maiteace, etc. with aalog techologies come to eed the alterative solutio. Therefore the cofiguratio usig digital techologies has lately cosiderable attetio. # M # # W M Weight W Adaptive Cotroller Output Fig. -: Diagram of Basic Adaptive Atea System 3

8 (N Icidet wave s(n wavefrot ( M d xm d ( M d siθ θ x ( N x ( N Fig. -3: Uiform Liear Array of M-Elemet The basic structure to explai the priciple of adaptive atea sigal processig is illustrated by Fig. -3. The array atea is assumed to be a uiform equidistace liear array of idetical ad omi-directioal M elemets ad a electromagetic wave arrivig at array atea is a approximately plae ad arrowbad sigal. Let the agle betwee wave ormal ad icidet agle θ, the far-field expressio of the electrical sigal at k-th elemet at ay discrete time N is give by π xk ( N = sk ( N exp( j dk siθ k =,,, M (. λ where s k (N, λ ad θ is the evelop, wavelegth ad Directio-Of-Arrival (DOA agle of a icidet wave respectively ad d is the distace spaced betwee each atea. I this equatio if s k (N is a arrow bad sigal the temporal delay caused by differet path betwee elemets correspods to the phase differece. The output of array atea is produced by the ier product (multiply-accumulate operatio of iput sigals ad weight coefficiets determied by adaptive algorithms as (.. = M * π y( N wk sk ( N exp( j dk siθ k= λ (. They ca be also re-writte by vector expressio as (.3-(.4. X = x ( N x ( N x ( ] (.3 [ M N T H y = W X (.4 Basically adaptive atea techique forms the atea radiatio patter toward iteded directio by digital sigal processig. There are two kids of work. Oe is beam-steerig toward desired directio ad the other is ull-steerig toward udesired iterfereces, which may be more importat fuctio ad the origial cocept of a adaptive atea. Furthermore historically the 4

9 first adaptive atea is Howells itermediate frequecy (IF side-lobe caceller for ullig out the effect of oe jammer. O the other had, to determie the optimum weight, most of the beamformig algorithms such as MMSE (Miimizig Mea Square Error, MSN (Maximizig Sigal to Noise ratio, LCMV (Liearly Costraied Miimum Variace Filter, etc. whose solutios are based o solvig Wieer-Hopf equatio require the iformatio of DOAs of desired sigals ad iterferers i advace. Of course, there are also blid methods i which the iformatio of DOAs is ot ecessary such as CMA (Costat Modulus Algorithm. As a matter of fact it is sigificat to recogize previously the trasmissio coditios ad the eviromet of radio wave. That is to say, the spatial profile such as DOAs of icidet sigals as well as the temporal profile such as their frequecy characteristics is eeded. Therefore various techiques of DOA estimatio are studied also as a part of adaptive atea techologies [7]...3 Performace Improvemets Array sigal processig is capable of formig trasmit/receive beams towards the desired mobile. At the same time it is possible to place spatial ulls i the directio of udesired iterfereces called ull-steerig. This capability ca be used to improve the performace of a mobile commuicatio system as follows. The adaptive atea has a higher gai tha a covetioal omi-directioal atea. The higher gai ca be used to either icrease the effective coverage, or to icrease the receiver sesitivity. Coversely it ca be exploited to reduce trasmit power ad electromagetic radiatio i the commuicatio etwork. Multi-path propagatio i mobile radio eviromets leads to iter-symbol-iterferece (ISI. Usig trasmit ad receive beams that are directed towards the desired mobile reduces the adverse effects of multi-path ad ISI. Adaptive atea trasmitters emit less iterferece by oly sedig RF power i the desired directios. Furthermore, adaptive atea receivers ca reject iterferece by lookig oly i the directio of the desired source. Cosequetly adaptive ateas are capable of decreasig co-chael-iterferece (CCI [8]. 5

10 .3 Objective ad Structure of Paper This paper focuses o the implemetatio issues of a adaptive atea ad examies its applicatios for practical uses. Historically a adaptive atea has bee maily used for military applicatios, but recetly practical uses for various applicatios i wireless commuicatios are expected. However there are may obstacles to realize a adaptive atea system such as implemetatio complexity ad impractically high cost. The mai cocept of a adaptive atea is the automatic or adaptive cotrol of atea s beampatter by digital sigal processig with a software algorithm. A importat requiremet to realize i curret or ext geeratio commuicatios is high-speed realtime processig. But util ow the performace of digital devices such as geeral DSP (Digital Sigal Processor or MPU (Micro Processig Uit for array sigal processig is so poor as to uable to process a large-scale computatio ad they also cosume iefficietly large power to be usuitable for mobile commuicatios. O the other had usig high performace specific LSI called ASIC (Applicatio Specific Itegrated Circuit brig a low flexibility. A digital device capable of high-speed realtime processig, cosumig low power ad programmable is required for practical use of a adaptive atea i wireless commuicatios. I recet year usig a FPGA (Field Programmable Gate Array for the implemetatio of a adaptive atea meets the requiremets of high performace processig, programmability ad low power cosumptio. It is described i the ext sectio i detail. This paper examies the practical implemetatios of a adaptive atea techique usig FPGAs as a digital sigal processor. The desig ad developmet of a digital prototype system for the evaluatio of a adaptive atea techology are described i Chapter ad the applicatio implemetatios are examied i Chapter 3 ad Chapter 4. Beamformig ad DOA estimatio techique are two typical applicatios of a adaptive atea techology. I Chapter 3 the implemetatio of simple Maximal Ratio Combiatio (MRC beamformig atea ad this chapter also discusses a digital calibratio techiques of a array atea system. I Chapter 4 DOA estimatio techique usig MUSIC (MUltiple SIgal Classificatio algorithm are described ad Chapter 5 cocludes this paper. 6

11 .4 Implemetatio Issues o Adaptive Array Sigal Processig Ad FPGA (Field Programmable Gate Array There are may requiremets eeded for implemetatio of a adaptive atea techology i the ext geeratio wireless commuicatio system. From the poit of view that adaptive atea is a ew cocept of atea combiig with digital sigal processig uit, the most critical thig ca be the performace of a digital sigal processor. I other words the high performace for realtime processig of a large-scale computatio has bee the highest barrier to implemet. Cosiderig applicatios for mobile commuicatio the solutio of power cosumptio problem is also required. I additio recofigurablity or programmability ca improve the commuicatio quality extremely recogizig the commuicatio eviromet ad recostructig the optimum cofiguratio adaptively, which is a cocept of software defied radio. Particularly to meet the requiremet of the real-time processig performace i adaptive atea techiques takes a complex ad high cost array atea etwork ad a high performace DSP (Digital Sigal Processor. Hece i the past they were examied oly academically ad developed for oly special uses such as military radar applicatios. As the techologies of VLSI have made a great progress owadays, the processig speed is gettig faster ad the itegratio scale is gettig larger. SRAM-based FPGA (Field Programmable Gate Array techology has led to aother alterative solutio for digital sigal processig. I this paper, the system implemeted by usig a FPGA is itroduced. FPGAs i this system play a part as a digital sigal processor for digital beamformig or DOA (Directio Of Arrival estimatio fuctios, which require a large umber of MAC (Multiply-ACcumulate operatios ad eed large-scale parallel processig. FPGAs ca meet these requiremets..4. Basic Descriptios of a FPGA A programmable logic device (PLD is loosely defied as a device with cofigurable logic ad flip-flop liked together with programmable itercoect as show i Fig. -4. A FPGA is a kid of programmable logic devices ad a array of gates with programmable itercoect ad logic fuctios. It ca be recofigured ifiite times after maufacture but geerally distict from PLD by higher logic capacity. A FPGA cosists of logic blocks ad a itercoectio resource to coect the logic blocks. The logic block usually cotais lookup tables (LUTs ad flip-flops (FFs to store data as Fig. -5. Iput ports are coected to LUT iput ports or FF iput ports ad outputs from LUTs are either coected to output ports of the logic block or coected to FF iput 7

12 ports. By usig multiplexig, various combiatios of iputs ca be chose ad sequetial logics with memory elemet of FF as well as combiatioal logics with LUTs are also available []. To itegrate complex logic circuits distributed to lots of LSI s o board by sigle or more devices, programmable logic devices have bee maily used. A progress of device itegratio techology ca provide to implemet more complex circuits such as large-scale digital sigal processig o sigle FPGA. Furthermore it has may advatages over the other digital sigal processig solutios as DSP or MPU ad ASIC. The ext sectio describes the advatages i detail. Fig. -4: Structure of a FPGA Carry I Cascade I DATA DATA DATA3 DATA4 Look-up Table (LUT Cascade Chai & Carry Chai PRN D Q CLK CLRN LE Out Load Pre- Computed Logic Carry Out Cascade Out Fig. -5: FPGA Logic Block 8

13 .4. Digital Sigal Processig o FPGAs As metioed before, there are a few kids of digital sigal processig solutios for array sigal processig techiques. Oe is usig a geeral purposed processor (DSP or MPU, ad the other oe is usig a ASIC (Applicatio Specific Itegrated Circuit. While geeral purposed processor solutios are very flexible because their architectures are optimized to process a fixed set of istructios but may ot be ideally suited to the specific applicatio, ASIC solutios offer the ability to desig a custom architecture that is optimized for a particular applicatio. For example, a geeral purposed covetioal DSP has oly sigle multiply-accumulate (MAC stage, so the computatios must be executed sequetially, amely i serial, but whereas a ASIC implemetatio ca have multiple parallel Multiply-ACcumulate (MAC stages. Whe comparig the performace of the ASIC versus the geeral purposed DSP, it becomes apparet that the DSP or MPU offers slow speed but maximum flexibility (programmability while the ASIC provides high speed with miimal flexibility. O the other had, a FPGA combies the versatility of a programmable solutio with the performace of dedicated hardware as show i Fig. -6. A FPGA ca obtai the true goal of parallel processig executig algorithms with the iheret parallelism due to distributed arithmetic structure while avoidig the istructio fetch ad load/store bottleecks of traditioal Vo Neuma architectures []-[3]. Flexible, But Lacks Real-Time Performace Flexibility of DSP, with Performace of ASIC Flexibility DSP Processor DSP O FPGA High Performace, but Iflexible ASSPs ASICs Performace Fig. -6: FPGAs offer both Flexibility ad Performace 9

14 Implemetig DSP fuctio i FPGA devices provides the followig advatages as Table - []. FPGAs are thought as a key device i implemetatio of a adaptive atea or a software defied radio thaks to their high performace, flexibility ad recofigurablity ad etc. TABLE - A COMPARISON OF FPGA AND DSP PROCESSOR FPGA DSP Programmable Laguage VHDL, Verilog C, Assembly Ease of S/W programmig Performace Recofigurablity/ Programmability Fairly easy but eeds uderstadig the hardware architecture Very fast if optimized SRAM-type FPGAs ca be recofigured ifiite times Easy Speed depeds o operatig clock speed Re-programmable by chagig program Outperformig Area Digital Filters, FFT, etc Sequetial processig Power Cosumptio Implemetatio Method of MAC Speed of MAC Parallelism Ca be miimized if circuit is optimized Parallel ad distributive arithmetic Ca be fast if a parallel algorithm Ca be parallelized for high performace Caot optimize Repeat operatio of oe or a few MACs Depeds o operatio clock speed Usually sequetial ad caot be parallelized

15 Chapter Desig of Digital Prototype of Adaptive Atea Receiver. Itroductio A adaptive atea system is a compoud techology of may compoets. As icreasig the umber of atea elemets, accordigly the system scale gets huger. A adaptive atea system performs the aalog fuctios of frequecy coversio, filterig, gai cotrol ad the digital fuctios of adaptive sigal processig, modulatio/demodulatio ad etc after or before A/D or D/A coversio. It is very sigificat to cosider the architecture that provides low costs but meets the performace requiremets whe desigig a adaptive atea system. I this chapter, the architectures of a adaptive atea system are discussed. Ad the desig ad developmet of digital prototype evaluatio system o which adaptive atea techiques are implemeted are described. This chapter deals with the implemetatio of oly digital part of IF ad basebad stages except aalog RF stages. The digital part cosists of aalog to digital coverters (ADCs, FPGAs as a digital sigal processor ad a CPU for the cotrol of the whole system. This chapter presets the circuit cofiguratio ad IF sigal processig such as digital dowcoversio o FPGAs. I additio the relatioship to software defied radio architectures through the study of samplig schemes ad sigal processig o FPGAs is discussed.

16 . Architectures of Adaptive Atea System There are may ways of classifyig the architectures of a adaptive atea system. Oe of them is the way that how may dowcoversio stages it has. This way ca classify a direct coversio with oly sigle dowcoversio stage at RF ito basebad ad a super-heterodye with a few dowcoversio stages at RF ito basebad via IF. Aother is the way that where the ADCs (Aalog to Digital Coverters are placed. Geerally, the positio of ADCs is the most domiat factor of system architecture. This chapter discusses two types of architectures accordig to the placemet of a ADC. Oe is a basebad samplig architecture ad the other is a IF (Itermediate Frequecy samplig architecture. I additio future treds ad the architecture of software defied radio are discussed... Basebad Samplig Architecture As show i Fig. -, it has a few dowcoversio stages ad basebad I/Q sigals are derived from mixig the last IF sigal with a referece local oscillator. Because the ADC is placed at basebad, the system does ot require a high speed ad high performace ADC. Usually this system architecture has bee used as direct dowcoversio, double dowcoversio ad triple dowcoversio accordig to the umber of dowcoversio stages. Direct coversio has may problems to realize such as a difficulty of buildig filters to meet the phase ad amplitude matchig requiremets but is attractive from a system dowsizig poit of view with less RF compoets. Additioal mixers ca be added to the direct coversio architecture to improve performace ad stability ad usually the triple dowcoversio architecture has bee used. This architecture ca allow the secod IF frequecy to be sufficietly low so that a badpass filter such as a surface acoustic wave (SAW filter, ca be used to defie the sigal badwidth. This filter has very low phase ad amplitude distortio ad hece ca provide the high performace. The architectures metioed above have the aalog dowcoversio stage as the detectio of I/Q basebad sigals. That causes a few problems as followig [4] Poor matchig betwee the characteristics of the I/Q sigals Impairmet of I/Q orthogoality DC offset Spurious oise due to the oliearity of the aalog compoets

17 LNA Mixer LO BPF IF Amp. LPF LPF Video Amp. Video Amp. Aalog A/D A/D Digital I Q Adaptive Processig I Q Demodulatio LO o 9 o Fig. -: Receiver Architecture with Basebad Samplig.. IF (Itermediate Frequecy Samplig Architecture The alterative coversio architecture is show i Fig. -. This architecture digitizes sigals at IF directly ad the complex video sigal is geerated digitally. I this architecture, the aalog mixer ad lowpass filters are replaced with digital techiques. Oly oe high speed ADC provides with decreasig the system circuitry. I additio, the liearity of digital filters solves the matchig problems betwee I/Q sigals [4]. A digital dowcoverter (DDC is required to perform the coheret detectio fuctio. It cosists of a NCO (Numerical Cotrolled Oscillator, a pair of multipliers (mixers i aalog sese, lowpass filters ad decimatios. The decimatio reduces data rates which meas extractig the arrow basebad sigal from the widebad IF iput sigal. This ca allow the digital sigal processor to operate at moderate speed. This approach requires the high speed ad wide badwidth ADC ad high performace digital multipliers ad filters. LNA Mixer LO BPF Aalog IF Amp. A/D Digital cos( ω c NCO j si( ω c LPF LPF LPF Decimatio Digital Dow Coverter / Quasi-Coheret Detector I Q Adaptive Processig I Q Demodulatio NCO : Numerical Cotrol Oscillator Fig. -: Receiver Architecture with IF Samplig ad DDC 3

18 ..3 Future Treds ad Software Defied Radio (SDR I the ext steps, the ideal architecture as show i Fig. -3 is promisig. This approach places a ADC toward atea as close as possible. Atea ad RF frot-ed are required to be suitable for receivig widebad sigal ad ADC must be also able to digitize wide bad sigal at samplig rates. The other radio fuctios such as IF, basebad ad bit stream processig are carried out usig programmable digital processor like a DSP or a FPGA. This is the cocept of a software defied radio (SDR. By usig programmable or recofigurable digital sigal processig devices multi-mode ad multi-bad services ca be provided ad by applyig adaptive atea sigal processig it is possible to maximize the system performace ad optimize the commuicatio eviromet. Widebad Atea RF Froted Widebad ADC Programmable Processor I Q Fig. -3: Software Defied Radio Cocept.3 Developmet of Prototype System A few available architectures of a adaptive atea system were discussed i the previous sectio. The IF samplig architecture has may advatages over the basebad samplig. The digital dowcoversio must be the key process to realize a system toward a software defied radio. This sectio itroduces the digital prototype system of IF samplig architecture, which performs I/Q detectio digitally o FPGAs..3. System Cofiguratio The digital prototype evaluatio system is developed to apply to various adaptive atea sigal processig. It cosists of ADC board with ADCs (SPT7938, SPT, ad CPU board with a CPU (SH4, HITACH as a cotroller. Fig. -4 shows the photographs. A ADC board has chaels of ADC, buffer memory ad 3 FPGAs (total about 3, equivalet gates. The CPU board that has CPU, SH4 operatig at MHz ad whose operatig system is NetBSD, plays a part i ADC cotrol ad as a umerical computatio coprocessor. It also offers moitorig 4

19 iterface ad data commuicatio iterface betwee plural ADC boards via Etheret. A block diagram of the whole system is as show i Fig. -5. ADCs have bit resolutio ad up to 4 MHz samplig rates. The samplig rates ad samplig clock ca be cotrolled by FPGAs o ADC board [5]. (a (b Fig. -4: Photographs of (a ADC Board ad (b CPU Board As show i Fig. -5 received RF (Radio Frequecy sigals at each atea elemet are dowcoverted ito IF (Itermediate Frequecy. The this system performs dow-coversio ad quasi-coheret detectio fuctios by digital sigal processig. These features are distiguishig characteristic of a software-defied radio that places ADCs as close to the atea as possible. I the software radio receiver, the objective is to digitize a etire bad ad to perform IF processig, basebad, bit stream ad all other fuctios completely i software. However it may be very difficult to implemet because such digital radio based IF processig requires such capabilities as high-speed digital filterig, correlatio or FFT processig to pass smoothly to the ext basebad stages sample by sample i realtime. This prototype system is desiged cosiderig the IF processig architecture, key feature of software-defied radio. It ca process IF sigal up to MHz by 4 times over-samplig i realtime. The examiatio of samplig scheme is described i the ext sectio. By replacig aalog IF dowcoversio stages to digital sigal processig, dowsizig of system scale, reducig power cosumptio ad etc ca be achieved. After digital dowcoversio (DDC / quasi-coheret detectio, FPGAs perform adaptive sigal processig with dow-coverted complex basebad I/Q sigals. Table - illustrates the detail characteristics of the system. This system has oly chaels of ADCs but multi-chael more tha elemets ca be also cofigured as Fig. -6. It provides samplig clock sychroizig iterface with other ADC boards. 5

20 They operate at master s samplig clock i commo. A data commuicatio bus betwee them is Etheret. By this operatio the system ca exted the umber of atea elemets up to. ( x t # # x ( t Receiver A/D A/D Offset Cotrol Offset Cotrol Quasi- Coheret Detect Quasi- Coheret Detect I Q I Q Adaptive Processor W* W* Y(t A/D BOARD Obtai Weights Etheret SH4 (CPU Moitorig / Simulatio CPU BOARD Fig. -5: Block diagram of Basic -Chael Cofiguratio Table - DETAIL SPECIFICATION ADC Digital Dowcoversio / Quasi-Coheret Detectio (o FPGAs Iput Rage (IF frequecy Samplig rate Resolutio Chael Iput Output NCO (Numerical Cotrolled Oscillator LPF (Low Pass Filter ~ MHz (x4 Oversamplig ~ 4 MHz bits CHs / Board Passbad ( bits Basebad I / Q ( bits Switchig Circuit (,,, - 8 Taps 8 bits Coefficiet FPGAs or CPU Adaptive Processig 6

21 Ch. Ch. A/D A/D FIFO FPGA FIFO Master CPU (SH4 #6 #5 CLK Slave #4 #3 CLK Slave # # CLK Master Trigger Clock. Etheret PC Frot View Ch.x A/D FIFO Slave Slave Slave Ch.y A/D FPGA FIFO CPU (SH4 CLK Master Rear View (a (b N Chaels cos( ω c LPF w I RF x ( IF A/D A/D I/Q-Detectio x ( IF A/D A/D I/Q-Detectio NCO j si( ω c cos( ω c NCO j si( ω c LPF LPF LPF Decimatio Decimatio wi xi xq wq xi xq wq Demodulatio Data Decodig DOA Estimatio Beamformig (c Fig. -6: (a Cotrol via Etheret, (b 6-elemet Cofiguratio ad (c Block Diagram of Multi-chael Cofiguratio 7

22 .3. Digital Dow Coversio (DDC / Quasi Coheret Detectio Digital Dow Coversio / Quasi-coheret detectio is implemeted by usig NCO (Numerical Cotrol Oscillator, mixer ad lowpass filters as show i Fig. -7. It cosists of siusoidal sigal geerator by NCO ad FIR (Fiite Impulse Respose lowpass filters, where ω c is agular carrier frequecy. If a samplig frequecy is 4 times of IF ceter frequecy, NCO ad mixer ca be easily implemeted. I this paper, NCO ad mixer are simply implemeted by sequece switchig circuit (,,, - as show i Fig. -8. The FIR filters of 8 taps are used. I digitizig the aalog received sigals at IF (Itermediate Frequecy oly oe ADC is required for each atea elemet so it ca make the system scale by half. I this part, digital sigal processig dowcovert the sampled badpass sigals from ADC ito a complex basebad sigal [6]. Badpass sigals ca be expressed as a sum of two quadrature compoets which are π/ out of phase. Geerally badpass sigal is represeted by x( = x ( cos w + x ( si w, (. I c Q c where x I ( is the i phase compoet, x Q ( is the quadrature compoet of the sigal x( ad ω c is the ceter frequecy of the bad pass sigal (carrier frequecy. The dowcoversio process shifts the carrier frequecy ω c to basebad. It performs multiplicatio of the icomig badpass sigal x( with the complex phasor [cosω c - siω c ] ad the lowpass filters the result as (.. x ( = x( [cos wc si wc ] = [ xi ( + xi ( cos wc j x j x ( + x ( si w + j x Q Q c I Q ( si w + ( cos w c c ] (. This operatio accomplishs the desired frequecy shift. After lowpass filterig, the secod harmoic compoets are filtered out ad the result is the desired complex basebad sigal represetatio of x( as (.3 [7]. LPF( x ( = [ xi ( j xq ( ] (.3 Fig. -7 illustrates the block diagram that represets the frequecy spectrum as well as this mathematical process. Next sectios describe the FPGA implemetatio details. 8

23 x ( IF A/D cos( ω c NCO xi ( NCO : Numerical Cotrol Oscillator j si( ω c xq ( f c f c f s f c f c Fig. -7: Digital Dowcoversio / Quasi-Coheret Detectio.3.3 NCO ad Mixer The dowcoversio process requires a NCO (Numerical Cotrolled Oscillator ad a mixer multiplyig badpass sigal ad digital local sie/cosie sigal geerated by NCO as show i Fig. -7. There are various methods to implemet them. The method geeratig quadrature sigals by DDS (Direct Digital Sythesizer is usually used. But if clock sigal of exactly N times of carrier frequecy is achievable, the NCO ad mixer are o more tha a simple switchig circuit as Fig. -8. This system performs dowcoversio fuctio at 4 times of carrier frequecy of badpass sigal. 9

24 CLK (4 IF x ( - - x( -x( -x( x( π x( cos( 4 π x( si( 4 x( π x( cos( 4 π x( si( 4 period x(-3 x(- x(- x( x(-3 -x(- -x(- x( Fig. -8: Implemetatio of Mixer ad NCO.3.4 Lowpass Filter Digital filter implemetatio o FPGAs has may advatages over the other solutio such as geeral DSP. It is said that a DSP ad microprocessor ca implemet a 8-tap FIR filter at 5 Msps, while a off-the-shelf FIR filter 3 Msps but FPGA ca implemet the same filter at over Msps because a FPGA is suitable for parallel processig ad distributed arithmetic as described i Chapter [8]. Digital dowcoversio requires two lowpass filters a chael. The iputs are mixed sigals of NCO ad badpass sigal ad the outputs are complex basebad sigals of i phase ad quadrature. Lowpass filters suppress a secod harmoic compoet ad obtai oly frequecy-shifted sigals ito basebad. They are FIR (Fiite Impulse Respose filters of 8 taps. I this system, the FIR filter has -bit registers arraged i a shift register cofiguratio. The output of each register, called a tap, is represeted by x(, where is the tap umber. Each tap is multiplied by a coefficiet h( ad the all the products are summed. The equatio for this filter is 8 y ( = h( x(. (.4 = For a liear phase respose FIR filter, the coefficiets are symmetric aroud the ceter values. Takig advatage of the symmetry FIR filter ca be recostructed as Fig. -9 (a, which reduces the circuitry required to implemet the filter. I additio Fig. -9 (a ca be optimized by a FPGA

25 usig look-up tables (LUTs. The multiplicatio ad additio ca be performed i parallel usig LUTs [8]. The characteristics of FIR filter are show i Fig. -. X(-7 Q D X(-6 Q D X(-5 Q D X(-4 Q D X(-7 Q D X(-6 Q D X(-5 Q D X(-4 Q D x(+ X( X(- X(- D Q D Q D Q D Q X(-3 x(+ X( X(- X(- X(-3 D Q D Q D Q D Q h h h 3 h 4 s s s 3 m+w s 4 LOOK UP TABLE (LUT m+w+ m+w+ Y t Y t (a (b Fig. -9: (a Covetioal FIR filter usig Symmetry ad (b FIR Filter usig LUT (Look Up Table Kaiser β=.5 Magitude - db Time Step Frequecy (a (b Fig. -: (a Time Domai ad (b Frequecy Domai Impulse Respose of Lowpass Filter

26 .4 Examiatio of Aalog to Digital Samplig Schemes The system metioed i previous sectio provides two schemes of ADC samplig: oversamplig icludig Nyquist samplig ad udersamplig (also called subsamplig or badpass samplig. This sectio discusses them ad examies the applicatio to our system. This prototype system has the ADC (SPT7938, SPT which allows a widebad aalog iput up to 5 MHz ad has the samplig rate up to 4 MHz. The diagram of samplig schemes is illustrated i Fig. -. f c = MHz IF Badpass Sigal Over samplig 4 Msps f c = MHz IF Badpass Sigal DDC Basebad I / Q Sigal f c = 7 MHz Uder samplig Low-IF Badpass Sigal f c = MHz Fig. -: Flows of Each Samplig Scheme.4. Oversamplig Scheme The samplig rate i aalog to digital coversio is determied by Nyquist samplig criterio which specifies the required samplig rate for sigal recostructio as f s > f, (.5 max where f s is the samplig rate ad f max is the maximum frequecy of a sigal to be digitized. Geerally samplig at rates greater tha f max is called oversamplig. The advatage of this approach is that the aliase that appears aroud f s becomes icreasigly separated as the samplig rate f s is icreased beyod f max. By samplig at a higher rate, a simpler ati-aliasig filter with a more moderate trasitio ad less stopbad atteuatio ca be used without ay icrease i the distortio due to spectrum overlap. Therefore, oversamplig ca miimize the performace requiremets of the ati-aliasig filter whereas faster ADC s are required to digitize relatively low frequecy sigals. Usig the oversamplig scheme this system samples the IF sigal (cetered at MHz at 4 Msps ad the the DDC (Digital Dow Coversio performs the frequecy dowcoversio ito the complex basebad sigal. Fig. - (a shows the frequecy spectrum of sampled IF sigal which is siusoidal sigal of. MHz assumig cetered at f IF = MHz. Fig. - (b shows the frequecy spectrum of dowcoverted basebad sigal.

27 3 Frequecy Display 3 Frequecy Display Magitude (db Magitude (db Frequecy Frequecy (a IF sigal (b Dowcoverted Basebad sigal Fig. -: Experimet Result of Oversamplig (f IF = MHz, f s = 4 Msps.4. Udersamplig Scheme O the other hads, if samplig aalog sigals at higher frequecy area, oliear aalog fuctios ca be cotrollable to the extet by digital sigal processig so that the cocept of a software defied radio ca be realized. Less aalog compoets are used ad digital sigal processig fuctios replace them. But the performace of a ADC as well as a digital sigal processig device is ot so high ad i additio impractically high cost. I fact it may take Giga-hertz ADC may years to be used usually at reasoable price. The alterative is a udersamplig. As a matter of fact, for a badpass sigal, more tha two times of the badwidth of the iformatio ca recostruct the iformatio of the sigal. The desired sigals will be aliased i bad by the udersamplig. For the udersamplig the samplig rate f s must satisfy the coditio as ( f IF + B / k f s ( f IF + B /, (.6 k where f IF is the ceter frequecy of a IF sigal ad k is a iteger umber [5][9]. Because covetioal ADCs are desiged to operate o sigals with maximum frequecies up to oe-half the samplig rate, covetioal ADCs typically are ot suitable for badpass samplig applicatios where the maximum iput frequecies are greater tha the samplig rate. I geeral, performace of ADCs typically degrades with icreased iput frequecy. I additio, striget requiremets o aalog badpass filters are eeded to prevet distortio of the desired sigal from 3

28 strog adjacet chael sigals. ADCs at low samplig rates are relatively iexpesive ad available ad hece this appears promisig approach. Usig the udersamplig scheme this system samples the IF sigal (cetered at 7 MHz at 4 Msps. Fig. -3 shows the process of the digital frequecy dowcoversio ad the frequecy spectrums. I this figure, the aliasigs caused by udersamplig appear accordig to k s value i (.6. The aliasig appearig i-bad is the same spectrum of the oversamplig. Therefore whe sigals digitized by udersamplig, the frequecy is also dowcoverted ito low-if simultaeously. I this system, IF sigal cetered at 7 MHz is dowcoverted ito low-if cetered at MHz. The DDC (Digital Dow Coversio performs the frequecy dowcoversio ito basebad i the same maer as the oversamplig. Fig. -4 (a shows the frequecy spectrum of sampled IF sigal which is siusoidal sigal of 7. MHz assumig cetered at f IF = 7 MHz. Fig. -4 (b shows the frequecy spectrum of dowcoverted basebad sigal. I the spectrums of Fig. -4 more oise ad adverse aliasig caused by a spurious compoets appear tha whe oversamplig. Actually whe udersamplig, striget requiremets o aalog badpass filters (steep roll-offs are eeded to prevet distortio of the desired sigal from strog adjacet chael sigals ad hece the filter before ADC must be examied sigificatly. Aalog Digital Digital Dow Coverter 8.45 GHz LNA BPF Mixer LO (8 GHz BPF 45 MHz AMP Mixer 7 MHz LO (38~44 MHz 4 Msps A/D cos( ω c NCO LPF LPF I Q Adaptive Processig I Q Demodulatio j si( ω c f IF f c f s f IF f c f c Fig. -3: Frequecy Dowcoversio by Udersamplig 4

29 3 Frequecy Display 3 Frequecy Display Magitude (db Magitude (db Frequecy Frequecy (a IF sigal (b Dowcoverted Basebad sigal Fig. -4: Experimet Result of Udersamplig (f IF = 7 MHz, f s = 4 Msps.5 Summary This chapter itroduced the digital prototype system for the evaluatio of a adaptive atea. The architecture was desiged based o FPGAs cosiderig IF sigal processig ad the recofigurablity of software defied radio (SDR ad the performace of realtime processig required to a adaptive atea system. The architecture of a adaptive atea system were discussed ad the developmet processes were described i detail. 5

30 Chapter 3 Examiatio of Applicatios Implemetatio: MRC Beamformig Atea 3. Itroductio This chapter describes the simple digital phased array atea usig digital beamformig cofiguratio ad itroduces its DSP implemetatio o FPGAs usig the prototype system itroduced i Chapter. This atea ca steer its mai beam toward the DOA (Directio of Arrival of icidet sigal ad track automatically. It icorporates MRC (Maximal-Ratio Combiig beamformig techique that recombies the output power at maximal ratio by co-phasig received sigals at each elemet like phased array atea. I this paper, for the sake of implemetatio simplicity ad use i mobile termial, it cofies oly elemets. This system uses FPGAs as digital sigal processor to obtai the realtime processig performace of parallel processig. 3. -Elemet MRC Beamformig Atea This paper uses arrowbad model for array processig of far-field sources. The icidet wave at k-th elemet ca be represeted as π x k ( = A( exp j ( k d siθ, for k =,, (3. λ where A(, λ ad θ is the evelop, wavelegth ad DOA agle of a icidet wave respectively ad d is the distace spaced betwee each atea. 6

31 After dowcoversio of the sigal (3. at each brach, with the complex basebad sigal represetatios (3. at each elemet ca be rewritte as B ( = I + = a B ( = I + j Q j Q ( exp = a( exp[ j( Φmod + φ ] = a ( exp[ j( Φmod + φ ] [ j( + φ + φ ] Φ mod, (3. where Φ mod is the modulated phase, φ, φ are the phase offset ad φ is the phase differece betwee elemet ad. Supposig the receivig power at elemet is almost same as that of the elemet ad the differece betwee them is egligible, the sampled data at elemet ca be writte as ( j φ B( B( exp π. (3.3 B ( exp j d siθ λ Geerally atea ca steer beam toward iteded directio of icidet wave by usig its steerig vector as the beamformig optimum weight vector. It is certai that beamformig is achieved by computig the phase differece betwee elemets. The optimum weight ca be obtaied with oly correlatios betwee sigals icomig from each elemet as w w = B( B = B( B ( = ( = B( B( π. exp( j d siθ λ It is based o the fact that the correlatios betwee sigals icomig from each elemet ad the referece sigal (i this case the sigal at elemet represet the steerig vector with phase delay caused by DOA of icidet sigal []. The the optimum weight obtaied by correlatios betwee elemets are multiplied to iput sigals as show i Fig. 3-. (3.4 x ( x ( From AD CH ( x D Q x ( x ( W* y( From AD CH ( x D Q W* Fig. 3-: Digital Phased Array Atea 7

32 From which, this system ca combie output power at the maximum ratio by multiplyig the weights to the iput sigals as y ( = w ( B ( = W k= k k H B, (3.5 ad coversely it ca also fid a DOA of icidet sigal by solvig above equatio (3.4 of θ. Fig. 3- shows the features that steers its mai beam toward the DOA of icidet wave ad tracks automatically. DOA (-5 DOA ( DOA (5 Magitude (db Array Respose of Optimum weight Agle (degree ( x t ( x t # # W W y(t Fig. 3-: Calculated MRC Beamformig Patters ad Automatic Trackig Feature 8

33 3.3 Hardware Implemetatio I this sectio, the hardware implemetatio of MRC beamformig atea usig the prototype system metioed i Chapter is described. All digital sigal-processig processes are implemeted o FPGAs i parallel architecture Weight Calculatio / MRC (Maximum Ratio Combiig Processor Accordig to Fig. 3- weight calculatio processor eeds some correlators, multipliers ad adders. The real part of correlators ca be implemeted 6 multipliers ad 3 adders as show i Fig. 3-3 from Eq. (3.4. Multiplyig optimum weights to sigals from each elemet the receivig sigal ca be recombied at maximal ratio i the output power. Fig. 3-3 shows the circuit of producig oly real part of outputs ad the imagiary part is easily produced i the same circuit structure. All computatios o FPGAs are fixed-poit operatios. The detail I/O data specificatios i Hardware desig (VHDL descriptio: Very high speed itegrated circuit Hardware Descriptio Laguage are preseted by Table 3-. From AD CH System Clock From AD CH x( x( cos( ω c j si( ω c Quasi-Coheret Detectio cos( ω c j si( ω c Quasi-Coheret Detectio ( x I ( x Q ( x I ( x Q Multipliers x I ( x I ( x Q ( x Q ( D Q Delay 4 Multipliers x I ( x I ( x Q ( xq ( x I ( xq ( x Q ( x I ( D Q D Q Delay 5 5 W(I w I xi ( W(I -W(Q w xi ( I wq xq ( MRC Part 6 ( y I Fig. 3-3: Weight Calculatio / MRC Processig Processor (Real-part of outputs 9

34 TABLE 3- HARDWARE DESCRIPTION SPECIFICATIONS OF COMPUTATIONS Module Fuctio Specificatios Qty / Remarks A/D Output bits usiged iteger ~ 495 NCO Features,,, - sequetially switchig Features FIR, 8 taps, 8 bits coefficiet. Iput bits usiged iteger from ADC DDC / Quasi- Coheret Detectio LPF Weight Calculatio MRC Multiplier Adder Usig LUT (Look Up Table Istead of Multipliers bits 5 bits 6 bits bits 6 bits elemets (8 bits iteger table Output MSB bits of 6 bits (I, Q Iput bits siged iteger from Quasi-coheret Detector (I, Q of CHs Multiplier : scaled 5 bits 6 Adder 6 bits 3 Output Iput 6 bits Weights bits siged iteger from Quasi-coheret Detector 6 bits siged iteger from weight calculatio 3 (RE of CH IM, RE of CH 3 (I of CH I, Q of CH 3 (RE of CH IM, RE of CH Multiplier 6 : scaled 5 bits 3 Adder 6 bits DOA Calculatio Output 6 bits Y( Arctaget Arcsie 3 bits floatig poit calculatio by CPU 3

35 3.3. Circuit Desig / Logic Sythesis (Scale of Circuit The result of logic sythesis of the hardware descriptios writte i VHDL (Very high speed itegrated circuit Hardware Descriptio Laguage, a stadard laguage i H/W descriptio of ASIC or FPGA, is show i Table 3-. I this result, it ca be expected that the scale of circuit eeded i implemetatio of this system is reasoable size to be covered with oly oe medium scale FPGA i recet techology. If it is used practically, the beam steerig fuctio ca provides the high quality commuicatio. TABLE 3- RESULTS OF LOGIC SYNTHESIS Module Equivalet Gates DDC NCO,,, - sequetially switchig (Q-DET LPF About 5,93 Gates (8 tap, FIR Weight / MRC Total Gates About 3,848 Gates NCO, Q-Detectors, MRC = 5,93 + 3,848 Gates = aroud 6,5 Gates 3

36 3.4 Experimetal Results This sectio itroduces the experimetal results. This experimet is DOA estimatio with obtaied optimum weight. MRC beamformig fuctio steers beam toward DOA of icidet sigal. Coversely the DOA agle ca be obtaied from the MRC optimum weight. From (3.4 the phase differece Θ betwee sigals ca be obtaied by the arctaget of the imagiary part to real part ratio of optimum weight. π Θ = d siθ = ta λ Im( w Re( w (3.6 Ad the DOA θ ca also computed by solvig as λ Im( w θ = si ta. (3.7 πd Re( w From (3.7 the DOA of icidet sigal ca be foud by MRC optimum weight because MRC steers the mai beam toward the directio of icidet wave. This operatio cofirms the beamsteerig fuctio of MRC processor. The experimetal cofiguratio is show as Fig Experimets were performed i a radio aechoic chamber to validate the fuctioality of the desig. Array ateas of elemets are omi-directioal ad spaced by λ/ betwee each other. The RF frequecy is 8.45 GHz ad received RF sigals are dowcoverted ito IF ( MHz i the RF receiver. Samplig rates ad resolutio of ADCs is 4 MHz ad bits respectively. This experimet was performed supposig that there is oly icidet wave ad decimatio factor is. All digital sigal processig stages such as DDC, weight calculatio ad maximal ratio combiig are performed o FPGAs. The detail experimetal parameters are illustrated i Table