SP721 Series 3pF 4kV Diode Array

Transcription

1 SP7 Series 3pF 4kV Diode Array RoHS Pb GREEN Description Pinout SP7 (PDIP, SOI) TOP VIEW Functional Block Diagram V+ V- 4 8 V , V+ The SP7 is an array of SR/Diode bipolar structures for ESD and over-voltage protection to sensitive input circuits. The SP7 has protection SR/Diode device structures per input. There are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. Overvoltage protection is from the (Pins - 3 and Pins 5-7) to V+ or V-. The SR structures are designed for fast triggering at a threshold of one +V BE diode threshold above V+ (Pin 8) or a -V BE diode threshold below V- (Pin 4). From an input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one V BE above V+. A similar clamp to V- is activated if a negative pulse, one V BE less than V-, is applied to an input. Standard ESD Human Body Model (HBM) apability is: Features - MIL STD kV - IE , Direct Discharge, - Single Input... 4kV (Level ) - Two Inputs in Parallel... 8kV (Level 4) - IE , Air Discharge...5kV (Level 4) - IE (8/0μs)... ±3A - Single Pulse, 00μs Pulse Width... ±A - Single Pulse, 4μs Pulse Width... ±5A - Single-Ended Voltage Range to V - Differential Voltage Range to... ±5V...ns Rise Time...nA at 5º Typical...3pF Typical...-40º to 05º Lead-Free/Green SP7 Applications Input Protection Protection 69

2 Absolute Maximum Ratings Parameter Rating Units ontinuous Supply Voltage, (V+) - (V-) +35 V Forward Peak urrent, I to V, I to GND (Refer to Figure 5) ±, 00μs A AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Note: ESD Ratings and apability (Figure, Table ) Load Dump and Reverse Battery (Note ) Thermal Information Parameter Rating Units Thermal Resistance (Typical, Note ) JA o /W PDIP Package 60 o /W SOI Package 70 o /W Maximum Storage Temperature Range -65 to 50 o Maximum Junction Temperature (Plastic Package) 50 o Maximum Lead Temperature (Soldering 0-40s)(SOI Lead Tips Only) 60 o. JA is measured with the component mounted on an evaluation P board in free air. Electrical haracteristics = -40 o to 05 o, V = 0.5V, Unless Otherwise Specified Parameter Symbol Test onditions Min Typ Max Units Operating Voltage Range, V SUPPLY - to 30 - V V SUPPLY = [(V+) - (V-)] Forward Voltage Drop to V- V FWDL I = A (Peak Pulse) - - V to V+ V FWDH - - V Input Leakage urrent I na Quiescent Supply urrent I QUIESENT na Equivalent SR ON Threshold Note V Equivalent SR ON Resistance V FWD /I FWD ; Note Ω Input apacitance pf Input Switching Speed t ON - - ns. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- Pins are connected to het same supply voltage source as the device or control line under protection, a current limiti ng resistor should be connected in series between the external supply and the SP7 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.0μF or larger romf the V+ and V- Pins to ground are recommended. 3. Refer to the Figure 3 graph for definitions of equivalent SR ON Threshold and SR ON Resistance. These characteristics are given here for thumb-rule nformation to determine peak current and dissipation under EOS conditions. Typical Application of the SP7 (Application as an Input lamp for Over-voltage, Greater than V BE Above V+ or less than -V BE below V-) +V +V PUT DRIVERS OR SIGNAL SOURES LEAR OR DIGITAL I TERFAE TO +V V+ SP7 V- SP7 PUT PROTETION IRUIT ( OF 6 SHO WN) 70

3 ESD apability ESD capability is dependent on the application and defined test standard.the evaluation results for various test standards and methods based on Figure are shown in Table. For the Modified MIL-STD condition that is defined as an in-circuit method of ESD testing, the V+ and V- pins have a return path to ground and the SP7 ESD capability is typically greater than 5kV from 00pF through.5kω.by strict definition of MIL-STD using pin-to-pin device testing, the ESD voltage capability is greater than 6kV.The MIL-STD results were determined from AT&T ESD Test Lab measurements. The HBM capability to the IE standard is greater than 5kV for air discharge (Level 4) and greater than 4kV for direct discharge (Level ).Dual pin capability ( adjacent pins in parallel) is well in excess of 8kV (Level 4). For ESD testing of the SP7 to EIAJ I Machine Model (MM) standard, the results are typically better than kv from 00pF with no series resistance. Figure : Electrostatic Discharge Test H.V. SUPPLY V D Standard Type/Mode R D D ±V D MIL STD HARGE SWITH R DUT Modified HBM.5kΩ 00pF 5kV Standard HBM.5kΩ 00pF 6kV HBM, Air Discharge 330Ω 50pF 5kV IE HBM, Direct Discharge 330Ω 50pF 4kV HBM, Direct Discharge, Two Parallel Input Pins 330Ω 50pF 8kV EIAJ I Machine Model 0kΩ 00pF kv D R D IE : R 50 to 00M MIL-STD-305.7: R to 0M Table : ESD Test onditions DISHARGE SWITH Lead-Free/Green SP7 Figure : Low urrent SR Forward Voltage Drop urve Figure 3: High urrent SR Forward Voltage Drop urve FORWARD SR URRENT (ma) = 5º SGLE PULSE FORWARD SR URRENT (A) = 5º SGLE PULSE EQUIV. SAT. ON THRESHOLD ~.V V FWD IFWD FORWARD SR VOLTAGE DROP (mv) FORWARD ST VOLTAGE DROP (V) 7

4 Peak Transient urrent apability of the SP7 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP7 s ability to withstand a wide range of peak current pulses vs time. The circuit used to generate current pulses is shown in Figure 4. The test circuit of Figure 4 is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP7 input pin and the (+) current pulse input goes to the SP7 V- pin. The V+ to V- supply of the SP7 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 5 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of 5º and 05º and a 5V power supply condition. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of Figure 5. Note that adjacent input pins of the SP7 may be paralleled to improve current (and ESD) capability. The sustained peak current capability is increased to nearly twice that of a single pin. PEAK URRENT (A) Figure 4: Typical SP7 Peak urrent Test ircuit with a Variable Pulse Width Input + V X - R VOLTAGE PROBE R ~ 0 TYPIAL V X ADJ. 0V/A TYPIAL ~ 00 μf (+) 3 4 VARIABLE TIME DURATION URRENT PULSE GENERATOR URRENT SENSE V- V+ 8 SP Figure 5: SP7 Typical Single Peak urrent Pulse apability Showing the Measured Point of Overstress in Amperes vs pulse width time in milliseconds = 05 = 5 (-) + - AUTION: SAFE OPERATG ONDITIONS LIMIT THE MAXIMUM PEAK URRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 75% OF THE VALUES SHOWN ON EAH URVE. V+ TO V-SUPPLY = 5V PULSE WIDTH TIME (ms) 7

5 Temperature TVS Diode Arrays (SPA Family of Products) Soldering Parameters Reflow ondition - Temperature Min (T s(min) ) 50 Pb Free assembly T P Ramp-up t P ritical Zone TL to TP Pre Heat - Temperature Max (T s(max) ) 00 - Time (min to max) (t s ) secs Average ramp up rate (Liquidus) Temp (T L ) to peak 5 /second max T S(max) to T L - Ramp-up Rate 5 /second max Reflow - Temperature (T L ) (Liquidus) 7 - Temperature (t L ) seconds Peak Temperature (T P ) 60 +0/-5 Time within 5 of actual peak Temperature (t p ) 0 40 seconds Ramp-down Rate 5 /second max T L T S(max) T S(min) 5 t S Preheat time to peak temperature t L Ramp-down Time Lead-Free/Green SP7 Time 5 to peak Temperature (T P ) 8 minutes Max. Do not exceed 60 Package Dimensions Dual-In-Line Plastic Packages (PDIP) DEX AREA BASE PLANE SEATG PLANE D B -- -A- N 3 N/ B D e D E -B- A 0.00 (0.5) M A. ontrolling Dimensions: H. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.5M Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDE seating plane gauge GS D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum e B and e are measured at the lead tips with the leads unconstrained. e must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is t he maximum number of terminal positions. 0. orner leads (, N, N/ and N/ + ) for E8.3, E6.3, E8.3, E8.3, E4.6 will have a B dimension of inch ( mm). A L B S A e E L e A e B Package PDIP Pins 8 Lead Dual-in-Line JEDE MS-00 Millimeters Inches Min Max Min Max Notes A A A B B , D D E E e.54 BS 0.00 BS - e A 7.6 BS BS 6 e B L N

6 Package Dimensions Small Outline Plastic Packages (SOI) N DEX AREA 3 e D B 0.5(0.00) M A E SEATG PLANE M -B- -A- -- A B S H 0.5(0.00) M B A. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.5mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.04 inch). 0. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. μ 0.0(0.004) L M h x 45 o Package SOI Pins 8 JEDE MS-0 Millimeters Inches Min Max Min Max Notes A A B D E e.7 BS BS - H h L N μ 0º 8º 0º 8º - Part Numbering System Silicon Protection Array (SPA TM ) Family of TVS Diode Arrays Series SP 7 ** ** G = Green P = Lead Free TG= Tape and Reel Package AB = 8 Ld SOI AP = 8 Ld PDIP Product haracteristics Lead Plating Matte Tin Lead Material opper Alloy Lead oplanarity inches (0.0mm) Substitute Material Silicon Body Material Molded Epoxy Flammability UL 94 V-0 Ordering Information Part Number Temp. Range (º) Package Environmental Informaton Marking Min. Order SP7APP -40 to 05 8 Ld PDIP Lead-free SP7AP(P) 000 SP7ABG -40 to 05 8 Ld SOI Green SP7A(B)G 960 SP7ABTG -40 to 05 8 Ld SOI Tape and Reel Green SP7A(B)G 500. SP7AP(P) means device marking either SP7AP or SP7APP.. SP7A(B)G means device marking either SP7AG or SP7ABG which are good for types SP7ABG and SP7ABTG. 74