Digital Control Technologies for Switching Power Converters

Transcription

1 Digital Control Technologies for Switching Power Converters April 3, 2012 Dr. Yan-Fei Liu, Professor Department of Electrical and Computer Engineering Queen s University, Kingston, ON, Canada yanfei.liu@queensu.ca

2 Outlines 1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion 2

3 Advantages of Digital Control Intelligence Better system level performance Better steady state performance Better dynamic performance 3

4 Challenges of Digital Control Output voltage resolution Output voltage not continuously adjusted Resolution of digital PWM generator not enough for high switching frequency Dynamic analysis of digital controller Digital design method is not suitable for power supply New control methods for digital control To achieve better dynamic performance NOT the digital implementation of analog method 4

5 Brief History of Digital Control Output voltage resolution Catch even with analog control No customer value New control technologies Better performance Customer value Smaller board area PID implemented digitally No need for Rs, Cs 5

6 Evolution of Power Supply Isolated converter Board Mount PS 6

7 Evolution of Power Supply Point of Load (POL) Power Supply on Chip (PwrSoC) No space for feedback R, C Digital control a must! 7

8 Digital PWM Block diagram of a DC-DC converter with digital control Vin DC-DC Converter Vo D I ind Vo Digital PWM Vcon Digital Compensator 8

9 Block Diagram of Digital Controlled Buck LSB ΔTon Limit Cycle Oscillation: Should be avoided ΔVo (ΔTon ) < LSB(ADC) 9

10 Basic Block Diagram of DPWM Digital Duty Cycle Bits MSB bits Coarse adjust Enable Delay Line LSB bits Fine adjust Ton Counter AND R PWM out System Clock, 50M Ts Counter S MSB bits: coarse adjustment, based on system clock LSB bits: fine adjustment: based on gate delay 10

11 Fine DPWM: ASIC Tapped Delay Line enable LSB bits Use the input-output time delay of logic gate Increase the resolution of on time, or duty resolution 11

12 Fine DPWM: FPGA Implementation 3 LSB Duty Cycle Input (0 1 1) Enable Signal bit 7 bit 6 bit 5 bit 4 Shift Register bit 3 bit 2 bit 1 bit Bit A7=1 Adder 7 C7=0 2 Bit A6=1 Adder 6 C6=0 2 Bit A5=1 Adder 5 C5=0 2 Bit A4=1 Adder 4 C4=0 2 Bit A3=0 Adder 3 C3=1 2 Bit A2=0 Adder 2 C2=1 2 Bit A1=0 Adder 1 2 Bit Adder 0 C1=1 A0=0 Delay τ Output Enable 12

13 Digital Pulse Width Modulator Bottom Line: Achieve fine enough on time (Ton) resolution Accurate control of output voltage Impact Catch even with analog control 13

14 Introduction Value of Digital Control Intelligence Complicated calculation capability Mission Explore the digital capability Achieve better performance Steady state, dynamic and system level 14

15 Seminar Outlines 1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion 15

16 2. Steady State Performance Improvement Light Load Efficiency Improvement Phase shedding control Logarithmic Current Sharing Heavy Load Efficiency Improvement Automatic dead time adjustment 16

17 Phase Shedding Control Reduce the activated phase number to improve efficiency Problems to be solved: Current balance during load transient Current sensing 17

18 Light Load Efficiency Optimization Two Buck converters for 60A load current 95% Eff 95% Eff 90% 90% 85% 85% 80% 80% 75% 75% 70% 70% 65% % Eff curve for one Buck converter Eff curve for two Buck converters 18

19 Light Load Efficiency Optimization Efficiency curve for two Buck converters in parallel: Io < 25A, one Buck operating, Io > 25A, two Buck converters operating 95% 1 Buck operation 2 Buck in parallel 90% 85% 80% 75% Eff Eff (shedding) 70% 65%

20 2. Steady State Performance Improvement Light Load Efficiency Improvement Phase shedding control Logarithmic Current Sharing Heavy Load Efficiency Improvement Automatic dead time adjustment 20

21 Block Diagram 0 1 A 1A Current command No current ADC 2A 4A Tight current regulation Phase enabler 21

22 Heavy Load Efficiency Optimization Buck converter Dead time between Vgs1 and Vgs2 Too long: body diode of Q2 conducts Too short: shoot through between Q1 and Q2 v gs1 v gs2 t d,on t d,off t d,on t d,off Q 1 L o i L C o + V in Driver Q 2 A/D Converter ic ESR Io R Load v o -... Digital PWM... d[n] i L [n] Digital Control Law e[n] S + - v o [n] A/D Converter V ref [n] 22

23 Heavy Load Efficiency Optimization How to determine optimal dead time Highest efficiency = optimal dead time Minimum input current = highest efficiency, Iin = D * Io Minimum duty cycle = highest efficiency 23

24 Dead Time Optimization in SR Buck Strategy Changing the dead time and monitor the duty cycle Search algorithm to minimize the duty cycle with respect to Td,on, Td,off 24

25 Implementation Block Diagram 25

26 Outlines 1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion 26

27 3. Auto Tuning with Digital Control Auto Tuning Change certain parameters in order to improve certain performance Unique to digital control, intelligence What can be achieved? Power train circuit estimation Compensating parameter design Plug and play, no feedback design needed Better dynamic performance 27

28 3. Auto Tuning Technology With Limit Cycle Oscillation Oscillation caused by Limit Cycle Oscillation Identify power circuit parameters Design PID parameters With nonlinear relay oscillation With Phase Margin measurement 28

29 LCO Based Auto Tuning Limit Cycle Oscillation should be avoided Caused by ΔVo (ΔTon ) > LSB(ADC) 29

30 LCO Based Auto Tuning LCO frequency contains power circuit information The relationship is: Gain of DPWM Control to output transfer function ADC transfer function 30

31 Advantages Optimal dynamic performance with parameter tolerance Estimation of load current For better current sharing 31

32 3. Auto Tuning Technology With Limit Cycle Oscillation With nonlinear relay oscillation Oscillation caused by relay Design PID parameter directly With Phase Margin Measurement Emulate human operation 32

33 Auto Tuning Discussion Why Auto Tuning? Get power train parameter Design optimal PID parameters Under different operating conditions, power parameters Benefits of Auto Tuning Shorter design cycle (no or little loop design work) Compensation for parameter changes over temperature, aging Value of Auto Tuning Why customers want to pay for auto tuning Compensation for parameter change Good for shorter design cycle 33

34 Seminar Outlines 1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion 34

35 Dynamic Performance Improvement Feature of Digital Control? Intelligence Complicated calculation capability Adoption, changing control parameters based on the changing conditions Potential to achieve better performance Steady state and dynamic What I would do if I were the controller? 35

36 Dynamic Performance Improvement Charge Balance Control Minimum time control, Time optimal control, Optimal control, Continuous time control Basic idea Force inductor current and capacitor voltage recover at same time 36

37 Conventional Control with Buck Given circuit parameters: L, C, Vin, Vo, Fs, Io Different dynamic response for different control methods R L L i L i o S 1 ESR Vin S 2 C i C Ro 37

38 Response of Conventional Controller A discharge A charge i L3 i L_end i o2 i o1 t 0 i L0 t 1 Load current step V ref Transition time Point 0 Point 1 Point 2 Point 3 Point 4 38

39 Charge Balance Control (CBC) Given circuit parameters: L, C, Vin, Vo, Fs, Io Different dynamic response for different control methods One possible best dynamic response and find it R L L i L i o S 1 ESR Vin S 2 C i C Ro 39

40 Capacitor Charge Balance (over Ts) Used extensively in steady-state analysis of DC-DC converters Vin S 1 S 2 i c R L = i L i o L i L ESR C + Vc - io i Ro C + Vo - v c ( T s ) v c (0) = i inductor current = 1 T s ic ( t) dt = 1 C 0 cavg T 0 0 s - + T s load current output voltage reference voltage 40

41 Capacitor Charge Balance (Dynamic Period) Extend principle to transient period t b 1 1 vc ( tb) vc ( ta ) = C i = 0, or ic ( t) dt = 0 cavg t t ta b Voltage recovers to original value when net charge balanced a reference voltage output voltage Goal: Balance the charge in shortest possible time t a t b 41

42 Implementation of CBC Set PWM high immediately Inductor current increases at fastest slew rate Minimizes T dis Minimizes A discharge Minimizes Δv o Set PWM low at t 2 such that A charge = A discharge Minimizes T ch Minimizes settling time load current A discharge A charge reference voltage inductor current output voltage How do we obtain t 2? T dis T ch t 0 t 1 t 2 t 3 42

43 Discharge Area Calculation A discharge = A 1 A charge = A 2 + A 3 inductor current i L A 3 I o2 A 1 A 2 load current i o A 1a I o1 I L0 T 0 T 1 T 2 t 0 t 1 t 2 t 3 Note: 43

44 Charge Area Calculation A discharge = A 1 A charge = A 2 + A 3 inductor current i L A 3 I o2 A 1 A 2 load current i o A 1a I o1 I L0 T 0 T 1 T 2 t 0 t 1 t 2 t 3 44

45 Balancing the Charge Area A discharge = A 1 A charge = A 2 + A 3 inductor current i L A 3 I o2 A 1 A 2 load current i o I o1 I L0 A 1a discharge Charge T 0 T 1 T 2 t 0 t 1 t 2 t 3 45

46 Physics of the Double Integration Vo integrated two times from t 0 to t 1 Re-write the integrations as: t1 t1 t1 dtdt = dt V O V 0 O t t0 t 0 dt -Vin integrated two times from t 1 to t 2 - V At t = t 2, these two terms added together is zero (- ) t2 t2 t2 dtdt = dt in V in t t1 t1 1 dt The second integrations can be combined. 46

47 Double Integrator Implementation v int1 v int2 t t V o Reset: t<t 0 or t>t 1 -V in t 0 t 1 t 0 t 1 t 2 1a Multiplexer 0 2 1b Reset: t<t 1 or t>t 2 t>t 1 1 v int1 v int2 Reset: t<t 0 or t>t 2 47

48 Block Diagram of CBC with Analog Q 1 L o R L I o + V in Driver Q 2 I L Ic C o ESR Load V o - PWM Multiplexer PWM Output Steady-State / Transient Vin Conventional Controller Charge Balance Controller Linear Control Voltage Hold Vout 48

49 Other Considerations Equations for a positive load current step For a negative load current step, the derivation is similar Before completion, algorithm calculates the new steady state duty cycle d and inductor current i L to be passed to the PID current-mode controller Allows for a smooth transition 49

50 Importance for Detection of t 1 and t 2 At t = t 1 : I_load = I_ind Icap = 0 Vout = min load current A discharge A charge inductor current Critical to detect t 1 : reference voltage t 2 depends on t 1 output voltage T dis T ch t 0 t 1 t 2 t 3 50

51 Technologies to Detect t 1 and t 2 Analog Icap sensing Trans-impedance amplifier for t 1 Double integrator falls to zero As discussed before Digital Icap information Digital Icap rebuilding Digital double integrator falls to zero Suitable for AVP 51

52 Other Technologies to Detect t 1 and t 2 Time domain detection Asynchronous ADC operation for t 1 Calculate t 2 based on t 1 Continuous time DSP structure Voltage domain detection Voltage value calculated to determine t 1 Voltage value calculated to determine t 2 AVP achieved 52

53 Other Technologies to Detect t 1 and t 2 Time domain detection Asynchronous ADC operation for t 1 Calculate t 2 based on t 1 Continuous DSP structure Voltage domain detection Extreme voltage detector for t 1 Parabolic Curve Fitting for t 1 to determine t 2 AVP can be achieved 53

54 Digital Parallel Current Mode Control v 1( t) kx vg ( t) vcontrol ( t) ref = Reference signal for inductor current When v in (t) v g (t), v ref1 (t), i g (t), p in (t), V C (t). This is not a desired situation. We need to wait the voltage loop to bring down the output voltage. 54

55 Digital Parallel Current Mode Control Basic idea of parallel current mode control: + L D + + i L L + + i L L + V in (t) S C V o Ro V in (t) C V o Ro V in (t) C V o Ro Boost Converter On state Off state Inductor current: di t t < t + d L L = Vin n n n s dt dil L dt t = Vin V n + n s < n+ 1 o d T t T t

56 Digital Parallel Current Mode Control L T n d V L T n V n i n i s o s in L L + = + )) ( (1 ) ( ) ( 1) ( Inductor current in discrete form: At duty cycle d, the inductor current at the end of switching cycle Rewrite the above equation as: o in o o L L s V n V V V n i n i T L n d ) ( ) ( 1) ( ) ( + + = Required duty cycle in order to drive inductor current from i L (n) at the beginning of switching cycle to i L (n+1) at the end of switching cycle.

57 Digital Parallel Current Mode Control For a properly designed system, we want: V o = V ref i L ( n + 1) = i ( n + 1) ref Substitute the above two relations into duty cycle equation: d( n) = L T s i L ( n + 1) i V o Proposed power factor correction algorithm: L ( n) V + o V V o in ( n) d( n) = L T s i ref ( n + 1) i V ref L ( n) + V ref V V ref in ( n)

58 Digital Parallel Current Mode Control Block diagram: parallel operation. V in Boost Converter Vo d(n) V in (n) i L (n) Voltage Term Calculation Current Term Calculation V ref V ref i ref (n+1)

59 Digital Parallel Current Mode Control Reference current for PFC implementation: i ref ( n + 1) = I sin( ω t( n + 1)) PK I PK is the peak inductor current, from voltage error amplifier sin (ω t(n+1) ) is sine waveform, from lookup table Therefore, direct duty cycle control for PFC: d( n) = I PK sin( ω t( n + 1) K c i L ( n) V + ref V V ref in ( n) where Kc=TsVref /L, is a constant

60 Digital Implementation Vin L i L D Vo + R1 R3 AC C1 S C2 Load R2 R4 - i L Vin Gate Driver Vo A/D A/D PWM A/D d(n) Input Voltage fed-forward i L (n) V in (n) Duty Cycle Calculation i ref = k pid line n+ sin( ϖ t 1) Multiplier sin( ϖ line t n+ 1) k pid PID error V ref Zero Cross Detection Sine Wave Look up Table DSP

61 Digital Implementation V in L Current sensor i L (t) D Vo Iac D1 D3 Vac Gate drive Q C Load D4 D2 i L (t) PWM V in - OpAmp2 V term + OpAmp3 Adder - OpAmp1 I term + i L_avg (t) Vo - OpAmp4 Voltage Loop + V ref I ref = K* V ac_pk *I PK * sin(w line t) K*V ac_pk * sin(w line t) Multipier V ref I PK d( n) = I PK sin( ω t( n + 1) K c i L ( n) V + ref V V ref in ( n) Kc=TsVref /L

62 Outlines 1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion 62

63 Future Work for Digital Control Take advantage of digital circuits Provide value to end customers Lower cost, better (same) performance at lower cost Better performance at same cost Dynamic performance improvement Reduced undershoot and overshoot Smaller output capacitor value Digital only implementation Analog circuit cannot make it 63

64 Conclusion Take advantage of digital circuits Intelligence, calculation capability, lower cost Provide value to end customers More cost effective product Auto tuning Reduced design effort, better performance Charge Balance Control (or TOC) Reduced output capacitor, faster response 64