Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Transcription

1 Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended (Differential) operation the output is measured between, two nodes those have opposite signal excursions around a fixed point. An important advantage of differential operation over single ended is higher immunity to environmental noise. Another common mode rejection advantage at differential operation occurs with noisy power supply The Difference Amplifiers The convenient way to represent the two input voltages is by their mean and difference values. The definition of the differential and common mode input voltages by the relations is given as, (5.1) (5.2) One way of implementing a difference amplifier is to use to single ended amplifier as shown in Fig The output would be the difference of two outputs (v o1 and v o2 ). Similar to the definition of common mode and differential signals, the common mode and differential output can be defined as, (5.3) (5.4) The common mode and the differential gains then become as, (5.5) 66

2 Figure 5.1. Possible implementation of a difference amplifier (5.6) A good differential amplifier has high differential gain independent of input common mode voltage, while the common mode gain should be as low as possible. The common mode rejection ratio, a figure of merit is defined as, (5.7) In simple suggested circuit (Fig. 5.1) the MOSFET currents, and hence the differential gain will depend on common mode voltage. A good difference amplifier will amplify only difference signal and not common mode signal. Hence, a better difference amplifier can be implemented by adding a current source to keep total MOSFET currents constant as shown in Fig.5.2. When the common mode voltage applied at two inputs changes, the voltage will get changed only at the node where two sources join (V s ). The current remains unchanged due to current source and hence the differential gain is unaffected by the common mode voltage. This gives a high CMRR. 67

3 Figure 5.2. A better implementation of the difference amplifier Single Ended Differential Amplifier A single output, which is proportional to the difference between two inputs, is needed very often. Thus, we need to combine the two outputs. This is achieved using current mirror loads, as shown in Fig.5.3. We can write, Figure 5.3. A difference amplifier with single-ended output 68

4 Due to current mirror action, I(M p2 ) = I(M p1 ). As Mp1 and Mn1 are in series, I(M p1 ) = I(M n1 ). Therefore, (5.8) Thus, we have single output proportional to difference of inputs. By definition we can write, Where, G m is the equivalent transconductance of differential amplifier stage. The effective G m is just the g m of either of the differential pair MOSFETs. Here the output being current, the circuit is also known as a differential transconductance amplifier. The output voltage of this circuit is the output current multiplied by the effective output resistance of the stage [46]. (5.9) Thus voltage gain can be given analogous to single stage CS amplifier as, and, Where, C tot includes C dg and C d of M n2 and M p2 respectively and the load capacitance if any Double Ended (Fully) Differential Amplifier An important application of fully differential amplifiers is their ability to suppress the effect of common mode interferences [40]. Like CS stage, linear resistors need not be implemented as the load of a differential pair. The differential amplifier can employ active load like diode connected or current source as shown in Fig

5 Figure 5.4 Differential pair with (a) Diode connected and (b) Current source load The small signal gain of differential amplifier can be obtained using the half circuit concept. For Fig.5.4 (a), the load is a MOSFET with gate and drain shorted which becomes a diode. The impedance offered by diode is (1/g m r o ) 1/g m. Where g m is a transconductance and r o is output resistance of diode connected MOSFET. The differential gain then becomes (5.10) Neglecting r o compared to 1/g m, (5.11) However, from (4.16) g m1 is given as (5.12) Also realizing the fact that M 1 and M 3 carry equal currents, voltage gain becomes as (5.13) 70

6 Similarly the small signal differential gain of current source load differential amplifier can be found out. The impedances offered by current sources will be r o3 and r o4. Thus the voltage gain becomes, (5.14) The diode-connected load consumes voltage headroom, thus creating a tradeoff between the output voltage swings, the voltage gain and ICMR. For given bias current and input device dimensions, the value of gain is decided by overdrive of PMOS diode-connected device. To get higher gain the aspect ratio of PMOS device must decrease thereby increasing the overdrive voltage and decreasing the common mode level at the output. The current source load can provide a relatively higher gain due to the output resistance of current source device. However, this limits the output voltage swing. To raise the voltage gain, the output resistance of current source device should be high. This increase in output resistance maintaining same overdrive voltage is brought by increasing W and L of the device, which leads to the large capacitance at output node [41]. To alleviate the above difficulty, part of bias currents of input MOSFETs can be provided by current sources with diode-connected loads as shown in Fig.5.5. The idea here is to lower the g m of load devices by reducing their current instead of aspect ratio. If M 5 and M 6 carry eighty percent of drain current of M 1 and M 2, the current through M 3 and M 4 is reduced by five times. For given overdrive of load devices, the transconductance of M 3 and M 4 is reduced by five times. Due to this, the differential gain is now five times as that of only diode-connected load. Figure 5.5. Differential pair with diode connected and current source load 71

7 5.1.4 Implementation of Single Ended Differential Amplifier The basic single ended differential amplifiers play a very important role in Monolithic IA. Hence, we started designing of single ended differential amplifier by replacing source resistance by improved current sources. The differential amplifier with active load and single ended output is the commonly used differential amplifier in CMOS analog circuits (Fig.5.6). This single ended differential amplifier has excellent features in terms of selfbias capability, common mode rejection, voltage gain and the gain-bandwidth product. In reference books, the simplified analysis of differential amplifier with active load and single ended output is specified. The differential voltage gain is evaluated by means of easy procedure, by replacing MOSFETs with small signal equivalent model. The analysis shows that the sources at input are at virtual ground for signal in case of pure differential input [47]. The circuit shown in Fig. 5.6 can be analyzed with some approximations. Using half circuit concept and replacing MOSFETs with small signal equivalent circuit the differential mode gain can be found out as, Figure 5.6. Single ended CMOS differential amplifier with active load and current source 72

8 Similarly, the common mode gain of differential amplifier in Fig. 5.6 can be derived as, The CMRR is directly proportional to differential mode gain and inversely proportional to common mode gain. Hence, keeping desired differential mode gain constant, the CMRR can be increased by using a tail current mirror source with higher output resistance. Hence, we are replacing tail current source by Wilson current mirror source that has higher output resistance. The output resistance R o of Wilson current mirror source from small signal equivalent model as per (4.73) is given by, (5.15) Figure 5.7. Single ended differential amplifier with current source replaced by Wilson mirror current source. 73

9 This shows that the output resistance of Wilson mirror current source is too larger as compared to the tail current mirror source in Fig Thus, improvement in CMRR can be expected. The complete circuit of single ended differential amplifier with modified current source is shown in Fig The simulated results are shown in Table 5.1 with the size of MOSFETs selected as M 1,2 = 40/1 µm/µm, M 3,4 = 58/0.25 µm/µm, M 5,6,7,8 = 10/0.25 µm/µm. The CMRR is seen to be increased by 10 times. Table 5.1: Simulated Results Parameters Differential amplifier with Differential amplifier with Wilson current mirror source mirror current source. V d 1mV 5mV V od 113mV 555mV A d V c 1V 1V V oc 40mV 3.02mV A c CMRR 69 db db Implementation of Double Ended (Fully) Differential Amplifier The load of a double differential amplifier can be diode connected or current source. The diode-connected load consumes voltage headroom thus reducing the output voltage swing, voltage gain and input CM range [50]. The current source load can provide higher voltage gain but at the cost of higher drain to source voltage required to keep MOSFET in saturation. In order to overcome the difficulty with diode connected and current source loads the part of bias current of input MOSFETs M 1, M 2 can be provided by PMOS current sources as shown in Fig

10 Figure 5.8. Double ended Differential Amplifier with diode connected and current source Loads The idea is to lower the g m of load devices by reducing their current instead of their aspect ratio (W/L) P. If M 5 and M 6 carry 80% of drain current of M 1 and M 2, the current through M 3 and M 4 gets reduced by five times. This translates to a factor of five reduction in transconductance of M 3 and M 4, hence as per (1) the differential gain increases by five times. The small signal gain of above balance differential amplifier will be in the range of 10 to 20 and the common mode gain will get reduced by five times as compared to diode connected loads [11][18]. The simulated results are as shown in Table 5.2. Table 5.2: Simulated Results of Double Ended Differential Amplifier Simulated results for Parameters Current source Diode Load Load Combined Load Ad Ac CMRR db db db 5.2 Operational Amplifiers (Op Amp) An operational amplifier is roughly defined as a high gain difference amplifier. High means a value adequate for the applications, typically in the range of 10 1 to Op amps 75

11 are usually employed in a feedback system; hence, their loop gain is selected according to the precision required for the closed loop system blocks. The efforts to serve as generalpurpose building block sought to create an ideal op amp, with very high voltage gain, high input impedance, and low output impedance but at the cost of speed, output voltage swings, and power dissipation [48]. Nowadays op amp design proceeds with realizing the trade-off between the parameters. Let us consider following op amp design parameters with importance and significance of each [42]. Gain The open loop gain of op amp determines the precision of the feedback system utilizing the op amp. Depending on application, the required gain may vary by four orders of magnitude. To compromise with speed and output voltage swings, the minimum required gain must be known. A high open loop gain may also be necessary to reduce nonlinearity. Small-Signal Bandwidth The high frequency behavior of op amp is desired in many applications. The open loop gain begins to drop with increase in frequency of operation, thus creating larger errors in the feedback system. The small signal bandwidth is usually defined as the unity-gain frequency f u, which is greater than 1 GHz for today s op amps. Sometimes the 3-dB frequency, f 3-dB, may also be specified. Large-Signal Bandwidth Op amps must operate with large transient signals in many modern applications. The nonlinear phenomena of op amp make it difficult to characterize the speed by simply small signal properties such as the open loop response. The large signal analysis shows that a large difference momentarily drives op amp into a nonlinear region of operation. Output Swing Many applications of op amp require large voltage swings to accommodate a wide range of signal amplitudes. Fully differential op amps became quite popular with need for large voltage swings. The double-ended differential amplifier circuits generate complementary outputs, thereby doubling the available swing. As seen from analog design octagon and 76

12 chapter earlier, the maximum voltage swing trades with device size and bias currents and hence speed. Achievement of large swings is also one of the challenges in today s op amp design. Linearity Op amps if operated in open loop suffer from substantial nonlinearities. In large gain differential amplifiers, the input pair of MOSFETs exhibits a nonlinear relationship between its differential drain current and input voltage. This problem of nonlinearity is tackled by two approaches one using fully differential form to suppress even-harmonics and secondly setting high open loop gain such that closed loop feedback system achieves adequate linearity. Actually, in many feedback systems linearity rather than the gain error requirement decides the choice of the open-loop gain. Noise and Offset The minimum signal level processed faithfully is determined by the input noise and offset of op amp. In op amp circuits, several devices decide noise and offset thus requiring large dimensions or bias currents. The trade off also exists between noise and output swing. With a given bias current, the overdrive of the load devices is lowered to permit larger swings at the output, thus transconductance increases and also drain noise current. Supply Rejection Many times op amps are used in mixed-signal systems and connected to noisy digital supply lines. The performance of op amps in presence of noise is quite important especially with increase in noise frequency. Fully differential topologies are used for this purpose One Stage Op-Amps All the differential amplifiers studied in earlier sections can be considered as op amps. Two topologies of differential amplifiers are shown in Fig. 5.9, single-ended and doubleended (differential) outputs. The small-signal low-frequency gain of both the circuits is given by g mn (r on r op ), where the P and N subscripts denote NMOS and PMOS devices. This value of gain provided by single stage differential amplifiers scarcely exceeds 20 in 77

13 submicron devices with typical currents. Generally, the bandwidth is determined by inter electrode capacitances and load capacitance, C L. The single-ended differential amplifier circuit exhibits a mirror pole whereas the double-ended does not. This difference is critical as far as stability of circuit is concerned. Both the circuits suffer from noise contributed by MOSFET devices. To achieve high gain the differential cascode topologies can be used as shown in Fig These cascode configurations of both single-ended and differential Figure 5.9. Simple op-amp topologies output op amps provide a gain of the order of g mn [(g mn r 2 on) (g mp r 2 op), but at the cost of reduced output swing and added pole. These configurations are known as telescopic cascode op amps. The single-ended cascode op amp circuit offers a mirror pole at node X, thus creating stability issue. The output swing of differential output cascode op amp is given by 2[V DD - (V OD1 +V OD3 +V CSS + V OD5 + V OD7 )]. This shows that the output swings of telescopic cascode op amps are limited compared to simple op amps. 78

14 Figure Cascode op amps The difficulty in shorting inputs and outputs is another drawback of the telescopic cascode op amp. This is required when op amp is used as a buffer but then cascode op amp will work for certain range of input as a buffer. Above two drawbacks of telescopic cascode op amps are overcome by folded cascode op amp. The folded cascode op amp also will offer the capability of handling input commonmode levels close to supply voltage. Telescopic cascode op amps can also be designed to provide a single-ended output. The cascode current mirror load converts the differential currents of main devices M 3 and M 4 to the single-ended output voltage as depicted in Fig.5.11 (a). However, here the voltage at X is given as V X =V DD - V GS5 - V GS7 and the output voltage V OUT is limited to V DD - V GS5 - V GS7 + V TH6. Thus one PMOS threshold voltage is wasted in the output swing. To improve the output voltage swing the PMOS load can be modified as shown in Fig (b). Here the MOSFETs M 7 and M 8 are biased at the edge of the triode region. Actually the circuit of Fig. 5.11(a) suffers from two disadvantages as compared to its counterpart in Fig. 5.11(b). First, it provides only half the maximum output voltage swing. Secondly, it includes a mirror pole at node X, thus limiting the speed of feedback systems using such amplifier. 79

15 Figure 5.11.Cascode op amps with single-ended output Design Example Statement: Design a fully differential telescopic op amp with specifications as : V DD = 3V, differential output maximum swing = 3V, power dissipation less than 0.5 mw, Voltage gain Assume µ n C ox = 60µA/V 2, µ p C ox = 30µA/V 2, λ n = 0.11V -1, λ p = 0.22V -1 (for effective channel 0.5µm), body effect coefficient γ = 0, V THN = V THP = 0.7V. Design Steps - The op amp topology along with two current mirrors fixing the drain currents of M 7 - M 9 is shown in Fig Let us begin with power dissipation, total current available is 0.167mA out of which half will be required for current mirrors and half available for the circuit. Each cascode branch thus carries a current around 40µA. The required output swing is 3V differential, thus each output node must be able to swing by 1.5V without driving any of the MOSFET into triode region. Therefore the total voltage available for M 9 and each cascode branch is equal to 1.5V. Hence, V OD7 + V OD5 + V OD3 + V OD1 + V OD9 = 1.5V. As M 9 carries maximum current 80µA, choosing V OD9 = 0.5V, leaving 1V for remaining four MOSFETs in cascode branch. Also M 5 - M 8, being PMOS suffer from low mobility, thus allocating over drive of 300mV approximately to each. Finally remaining 400mV is allocated between M 1 and M 3, 200mV each. 80

16 Figure Op amp topology along with two current mirrors With drain current and overdrive voltage known of each MOSFET, the aspect ratio can be found out from (4.6) of drain current. To get lower device capacitances the minimum channel length of MOSFET is selected 0.5µm. Thus we get the aspect ratios as (W/L) 1-4 = 11, (W/L) 5-8 = 14, (W/L) 9 = 4. Now to find out theoretical voltage gain, g m and r o will be required of MOSFETs which can be calculated using (4.15) and (4.17) g m1-4 = 4 x 10-4 A/V, g m5-8 = 2.67 x 10-4 A/V r o1-4 = 227.2kΩ, r o5-8 = kΩ The voltage gain of telescopic cascode op amp A g m1 [(g m3 r o1 r o3 ) ( g m5 r o5 r o7 ) = 1179 This gain is much lower than the desired gain To increase the gain we recognized that g m r o (WL/I D ). Thus keeping I D constant the gain can be increased by scaling W and L simultaneously keeping ratio constant. 81

17 Figure 5.13 Schematic of Telescopic cascode op-amp As M 1 M 4 appear in signal path, to keep their capacitances minimum their size will not be scaled. The PMOS devices M 5 M 8 affect the signal to smaller extent and hence are scaled. By scaling W and L, r o gets scaled while g m remains constant. Let us assume that scaling is done 1.4 times, therefore (W/L) 5-8 will be 21/0.7. Also λ p gets reduced by 1.4 times that is Modified PMOS devices, now will require slightly larger overdrive due to increase in dimension. Thus allotting 50mV more to M 5-8 and reducing overdrive of M 9 by 100 mv. The new dimension of M 9 comes out to be (W/L) 9 = 16. Now calculated gain comes out to be around The schematic of telescopic cascode op-amp simulated is shown in Fig and frequency and phase response comes out to be as shown in Fig

18 Figure 5.14 Frequency and phase response of Telescopic cascode op-amp 5.3 Source Followers A high voltage gain can be achieved from common source amplifier with high load impedance. If amplifier is required to drive a low impedance load then a buffer must be placed after amplifier. A buffer will drive the low impedance load with negligible loss of signal strength [53]. The common drain stages (source followers) are used as building blocks in a large number of high speed or high frequency applications, due to their intrinsic simplicity and wideband characteristics. The source followers suffer from non-ideal effects such as body effects, channel length modulations, signal-dependent capacitive effects and frequency distortions arising from capacitive loads. These non-ideal effects create a trade off among linearity, bandwidth and power dissipation. The analysis of source followers is based on non-linear parameters g m, g mb and r o in a low frequency small signal model. For NMOS source follower (NSF) as well as PMOS source follower (PSF), the input signal is applied to the gate and output is taken from the source. For signal levels above threshold voltage, the output voltage is equal to input voltage minus gate source voltage [52]. The gate source voltage consists of threshold and over drive voltage. If both these 83

19 voltages are constant, then output voltage is simply input voltage added with offset. The small signal gain would then be unity. Thus, the source follows the gate and circuit is known as a source follower. Actually threshold voltage depends on the body effect and the over drive depends on drain current. Also even if the drain current is kept constant, the overdrive depends to some extent on the drain-source voltage. Small signal equivalent circuits of MOSFETs with body effect can be used to evaluate the analysis of source follower circuits NMOS and PMOS Source Follower A. Small Signal Analysis of NSF The NSF in Fig consists of NMOS input transistor and NMOS current source as a load. The input signal V i consists of the DC biasing voltage V TH and the ac signal v i whereas the output signal V o consists of a DC biasing voltage V DS and the ac signal v o. For n-well process, the bulks of M 1 and M 2 share the same substrate. Hence, NSF suffers from the body effect. Figure 5.15 NMOS Source follower (NSF) circuit The small signal equivalent circuit of NSF is shown in Fig The body terminal is connected to lowest supply voltage (ground) to maintain source-body pn junction reverse biased. Since source is connected to output, v bs changes with output and g mb generator is active [1]. The load current source formed with M 2 is replaced by its drain resistance r o2. 84

20 Applying KVL around input loop, Figure 5.16 Small signal equivalent circuit of NSF (5.16) When the output is open circuited, i o = 0 and applying KCL at output node gives (5.17) From (5.16) substituting for v gs into (5.17) and rearranging, (5.18) If load current source is ideal,, (5.18) simplifies to (5.19) If r o1 is finite, the open circuit voltage gain of source follower is less than unity even if body effect is neglected. The variation in output voltage changes the drain-source voltage and the current through r o1. The large signal analysis shows that the over drive on gate also depends on the drain source voltage unless channel length modulation is negligible. This causes the small signal gain to be less than unity. 85

21 If, (5.20) Equation (5.20) shows that the voltage gain of the source follower is less than unity and it depends on =, which is typically in the range of 0.1 to 0.3. In addition, χ depends on source-body voltage, which is equal to v o when the body is grounded. Hence, gain found out in (5.20) depends on output voltage, causing distortion for large signal changes in the output. This can be overcome by selecting the type of source follower n-channel or p- channel fabricated in an isolated well. The well can be connected to source making v sb =0. In this case the parasitic capacitance from well to substrate increases reducing the bandwidth of source follower. The output resistance of source follower can be calculated from Fig by driving the output with a voltage source v o and setting v i = 0. (5.21) Then, (5.22) It is seen that the body effect reduces the output resistance, which is desirable as the source follower produces a voltage output. This desired effect results from the nonzero small signal current drawn by the g m generator. As and, this output resistance becomes, same as input resistance of common gate amplifier. The source followers are used as buffers and level shifters. They are more flexible as a level shifter because the dc value of V GS can be adjusted by changing aspect ratio W/L. B. Small Signal Analysis of PSF With the circuit of PSF, the most of designs have utilized a body tied PMOS input transistor to remove the bulk modulation effect and to improve the precision. This is possible as PMOS and NMOS transistors share the same substrate. Due to lower mobility 86

22 of PMOS devices, this results in higher output impedance than NSF. Also the transconductance efficiency is low in PSFs which results into small drive ability and a larger silicon area. Fig shows a conventional PSF in an n-well process which includes a PMOS input transistor and a PMOS current source. The small signal equivalent model for PSF will be same as NSF. In high frequency equivalent model, PSF will have additional capacitance due to bulk-well. In addition, the channel length modulation coefficients of M 1 and M 2 in PSF are smaller than that of NSF. This gives better linearity of PSF. Figure PMOS Source follower (PSF) circuit The Super Source Follower The output resistance of source follower is approximately 1/(g m +g mb ). As MOSFETs have much lower transconductance, this output resistance may be too high especially when a resistive load is to be driven. The output resistance can be reduced by increasing transconductance with increase in aspect ratio W/L of source follower and its dc bias current. This requires a proportionate increase in the area and power dissipation. To minimize the area and power dissipation required for low R o, the source follower configuration is used as shown in Fig The super follower as shown in Fig uses negative feedback through M 2 to reduce the output resistance [36].The qualitative analysis shows that, when the input voltage is constant and the output voltage increases; the drain 87

23 current of M 1 also increases, resulting into increased gate-source voltage of M 2.As a result, the drain current of M 2 increases, reducing the output resistance. Figure 5.18 Super-source follower circuit The dc bias current in M 2 is the different between I 1 and I 2, thereforei 1 > I 2 is required for proper operation. This condition can be used to find small signal parameters of MOSFETs. The small signal equivalent circuit is shown in Fig The body effect of M 2 is neglected becausev bs2 = 0. The polarities voltage controlled current sources for NMOS and PMOS are identical. The current sources I 1 and I 2 are replaced by their internal resistances r 1 and r 2 respectively. If the current sources I 1 and I 2 are ideal, r o1 and r o2. For practical current sources these resistances are large but finite. To find output resistance of the super source follower, set v i =0 and find the current i o that flows into the output node when it is driven by a voltage vo. Applying KCL at output under these conditions to Fig. 5.19, (5.23) Similarly applying KCL at drain of M 1 with v i = 0, (5.24) 88

24 Substituting for v 2 from (5.24) into (5.23) and rearranging gives, (5.25) Consider I 1 and I 2 ideal, r 1 and r 2. Also if r o2 and (g m1 +g mb1 ) r o1 >>1, (5.26) Figure 5.19 Small signal equivalent circuit of super source follower This is the output resistance of super source follower. Comparing (5.26) with (5.22), shows that the negative feedback through M 2 reduces the output resistance by a factor of about g m2 r o1. The open circuit voltage gain of super source follower can be found out from small signal equivalent circuit with the output open circuited. Applying KCL at the output node gives, (5.26) Also applying KCL at drain of M 1 gives, (5.27) 89

25 Substituting for v 2 from (5.26) into (5.27) and rearranging gives, (5.28) Assuming ideal current sources gives, (5.29) Comparing the open circuit voltage gain of the super source follower (5.29) with the open circuit voltage gain of a simple source follower (5.19) it is seen that the deviation of this gain from unity is greater in super source follower than a simple source follower. If,, this difference is small and the conclusion is that the super source follower has little effect on the open circuit voltage gain. The product g m r o for MOSFET is given by relation Where µ is mobility of charge carriers, C ox is gate oxide capacitance, λ is channel length modulation coefficient and W/L is aspect ratio. In addition, λ α 1/L, hence we get Therefore, the width and length can be adjusted to get desired product g m r o without changing I d Design Example Statement: Design a source follower with V DD = 3V, I D = 1 ma, having voltage gain close to unity output resistance not more than 100Ω and to handle input 2V p-p. Design steps - 90

26 As voltage gain desired is close to unity, the PMOS source follower with current source load as shown in Fig.5.17, will be preferred which has got less severe body effect compared to NMOS. Now from data given, And (Say which is close to unity) Thus we get, g m1 = To find overdrive, Therefore, The overdrive for M 1 can be calculated using relation, Thus V od1 =0.202 V Now the drain currents of both MOSFETs will be equal and given as, And As both MOSFETs carry same current above equations can be equated giving, We get, 91

27 Thus, Assuming wide band application let L= 0.5 µm, maximum value of V od2 is V, but allotting V od2 = 0.65 V. Then we get, Figure 5.20 Schematic of PSF 92

28 Figure 5.21 Frequency and phase response of PSF If (W/L) 1 =1000, (W) 1 = 500 µm. (W/L) 2 = let take 120, (W) 2 =60 µm. The schematic of PSF simulated is shown in Fig and as expected, the wide band frequency response is obtained as shown in Fig This chapter deals with the different configurations of the differential amplifiers used in the schematic of IA. The detailed designing of the telescopic cascode op amp is carried out which forms basis for the designing of various circuits in the IA. The last stage in most of the monolithic circuits is a buffer. The buffer can be designed using NMOS or PMOS source followers but one designed with PMOS gives properties close to a good buffer. The function of level shifter also is well accomplished by source follower. ***** 93