Features. Applications

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1 Data Sheet ACSL-0 Dual-Channel (Bidirectional) -MBd CMOS Buffered Input Digital Optocoupler Description The ACSL-0 is a dual-channel bidirectional -MBd digital optocoupler that uses CMOS IC technology and patented packaging technologies to achieve high isolation voltage 0 V RMS in a < mm low profile narrow-body SOIC- package. The device optimizes for bidirectional industrial communication networks, such as Fieldbus (PROFIBUS) and Serial Peripheral Interface (SPI) applications. The main building blocks of the ACSL-0 for each channel are a CMOS LED driver IC that is controlled by a CMOS logic input signal, a high-speed LED, and a CMOS detector IC. These building blocks allow fast propagation delay of 0 ns and short pulse width distortion of 0 ns maximum. The ACSL-0 has common-mode noise immunity of typical kv/µs at 000 V CM, with UL recognized with isolation voltage of 0 V RMS for minute, and IEC/EN/ DIN EN 0-- working insulation voltage V IORM of V PEAK with reinforced insulation. Features Dual-channel (opposite direction orientation) High-speed: DC to MBd.V and V CMOS compatibility CMOS input and output kv/µs minimum common mode rejection (CMR) at V CM = 000V Guaranteed AC and DC performance over wide temperature: 0 C to +0 C Safety and regulatory approvals: UL 0 V rms for minute IEC/EN/DIN EN 0-- for reinforced insulation V PEAK Applications Digital field bus isolation: PROFIBUS, CC-Link, DeviceNet, SDS Multiplexed data transmission General instrument and data acquisition Computer peripheral interface Microprocessor system interface CAUTION! Take normal static precautions in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. February, 09

2 Functional Diagram Truth Table VDD VO A VI B VDD VI A VO B Input Side V DD State Power Supplied No Power Output Side V DD State V I LED V O Power Supplied Power Supplied HIGH OFF HIGH LOW ON LOW X OFF HIGH GND Shield ACSL-0 GND NOTE: A 0.-μF bypass capacitor must be connected as close as possible between the power supply pins, VDD and GND, VDD and GND. Ordering Information Option IEC/EN/DIN EN Part Number RoHS Compliant Package Surface Mount Tape and Reel 0-- Quantity ACSL-0-00RE SO- X 00 per tube -0RE X X 00 per tube -0RE X X 00 per reel -RE X X X 00 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACSL-0-0RE to order RoHS-compliant Surface Mount -pin package in Tape-and-Reel packaging. Option data sheets are available. Contact your sales representative or authorized distributor for information.

3 Package Outline Drawings ACSL-0 SO- Package * 0.9 (.0) 0.9 (.00) DEVICE PART NUMBER LAND PATTERN RECOMMENDATION AVAGO 0. (.0) 0. (.0) LEAD FREE A NNNN YYWW EEE V FOR OPTION xxe 0.0 (.0) 0. (.00) DATE CODE 0. (.) 0.0 (0.) 0.00 (0.) LOT ID 0.0 (0. ) 0.0 (.) 0.00 (0.) 0.00 (0.0) 0.00 (0.9) x 0.00 (0.) 0.0 (.) 0.09 (.) 0.00 (.0) 0.00 (.) 0.00 (0.0) 0.00 (0.) 0.0 (0.0) 0.00 (.) 0 MIN DIMENSIONS: INCHES (MILLIMETERS) MAX * Maximum mold flash on each package side is 0.00 inches (0. mm). Lead coplanarity = 0.00 inches (0. mm) max. Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-00 (latest revision). Non-halide flux should be used. Regulatory Information The ACSL-0 will be approved by the following organizations. UL Approval under UL, component recognition program up to V ISO = 0 V RMS. CSA Approval under CSA Component Acceptance Notice #. IEC/EN/DIN EN 0-- Option 0RE only

4 Insulation and Safety Related Specifications Parameter Symbol ACSL-0 Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) L(0). mm Measured from input terminals to output terminals, shortest distance through air. L(0). mm Measured from input terminals to output terminals, shortest distance path along body. 0.0 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative CTI V DIN IEC /VDE 00 Part Tracking Index) Isolation Group IIIa Material Group (DIN VDE 00, /9, Table ) IEC/EN/DIN EN 0-- Insulation Characteristics (Option 0RE) Characteristic Description Symbol ACSL-0 Installation classification per DIN VDE 00/9, Table for rated mains voltage 0 V rms I IV for rated mains voltage 00 V rms I IV for rated mains voltage 00 V rms I-III Climatic Classification 0/0/ Pollution Degree (DIN VDE 00/9) Units Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b a VIORM.=V PR, 00% Production Test with t m =s, Partial discharge < pc Input to Output Test Voltage, Method a a V IORM.=V PR, Type and Sample Test, t m =0s, Partial discharge < pc V PR 0 V peak V PR 90 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 0s) V IOTM 000 V peak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature T S C Input Current I S, INPUT ma Output Power P S, OUTPUT 00 mw Insulation Resistance at TS, VIO = 00 V R S 0 9 Ω a. Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 0--) for a detailed description of Method a and Method b partial discharge test profiles. NOTE: This optocoupler is suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits.

5 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S C Operating Temperature T A 0 0 C Supply Voltage V DD, V DD 0. V Input Voltage V IA, V IB 0. V DD + 0. V Output Voltage V OA, V OB 0. V DD + 0. V Average Output Current I O 0 ma Input Power Dissipation a P I mw Output Power Dissipation a P O mw Lead Solder Temperature T LS 0 C for 0s,. mm below seating plane a. Per channel. Recommended Operating Conditions Parameter Symbol Min. Max. Units Operating Temperature T A -0 0 C Supply Voltage (.V) V DD, V DD.0. V Supply Voltage (V) V DD, V DD.. V Logic High Input Voltage V IH 0. VDD VDD V Logic Low Input Voltage V IL 0 0. VDD V Input Signal Rise and Fall Times t r, t f ms Electrical Specifications (DC) Over recommended temperature (T A = 0 C to 0 C) and supply voltage (.V V DD.V,.V V DD.V), (V V DD.V, V V DD.V), (.V V DD., V V DD.V) and (V V DD.V,.V V DD.V). All typical specifications are at V DD = V DD = +.V, T A = C, unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Logic Low Supply Current a I DDL, I DDL 9 ma V I = 0V, Figure Logic High Supply Current a I DDH, I DDH.9 ma V I = V DD, Figure Input Current I IA, I IB 0 0 µa Logic High Output Voltage V OH V DD 0.. V I O = 0 μa, V I = V IH V DD.0. V I O = ma, V I = V IH Logic Low Output Voltage V OL 0 0. V I O = 0 μa, V I = V IL a. LED is ON when V I is low and OFF when V I is high V I O = ma, V I = V IL

6 Switching Specifications (AC) Over recommended temperature (T A = 0 C to 0 C) and supply voltage (.V V DD.V,.V V DD.V), (V V DD.V, V V DD.V), (.V V DD.V, V V DD.V) and (V V DD.V,.V V DD.V). All typical specifications are at V DD = V DD = +.V, T A = C, unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low Output a t PHL 0 ns C L = pf, CMOS Signal Levels, Figure, Figure Propagation Delay Time to Logic High Output a t PLH 0 ns C L = pf, CMOS Signal Levels, Figure, Figure Pulse Width t PW 0 ns C L = pf, CMOS Signal Levels Pulse Width Distortion b t PHL t PLH PWD. ns V V DD.V, C L = pf, CMOS Signal Levels, Figure, Figure 0 ns CL= pf, CMOS Signal Levels Propagation Delay Skew c t PSK 0 ns C L = pf, CMOS Signal Levels Output Rise Time (0% to 90%) t R. ns C L = pf, CMOS Signal Levels, Output Fall Time (90% to 0%) t F. ns Figure Common Mode Transient Immunity at Logic High Output d CM H kv/µs V CM = 000V, T A = C, V I = V DD, V O > 0. V DD Common Mode Transient Immunity at Logic Low CM L kv/µs V CM = 000V, T A = C, V I = 0V, Output d V O < 0.V a. t PHL propagation delay is measured from the 0% level on the falling edge of the V I signal to the 0% level of the falling edge of the V O signal. t PLH propagation delay is measured from the 0% level on the rising edge of the V I signal to the 0% level of the rising edge of the V O signal. b. PWD is defined as t PHL t PLH. c. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions d. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V O > 0. V DD. CM L is the maximum common mode voltage slew rate that can be sustained while maintaining V O < 0.V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. Package Characteristics All typical at T A = C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation a, b, c V ISO 0 V RMS RH < 0% for min., T A = C Input-Output Resistance a R I-O 0 Ω V I-O = 00 V Input-Output Capacitance C I-O pf f= MHz, T A = C Input Capacitance d C I pf a. Device is considered a two-terminal device: pins,,, and are shorted together and pins,,, and are shorted together. b. In accordance with UL, ACSL-0 is proof-tested by applying an insulation test voltage 00 V RM S for second (leakage detection current limit, I I-O µa). c. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Application Note 0, Optocoupler Input-Output Endurance Voltage. d. C I is the capacitance measured at pin or pin (V I ).

7 Figure : Typical Logic Low Supply Current vs. Temperature Figure : Typical Logic High Supply Current vs. Temperature IDDL, IDDL - LOGIC LOW SUPPLY CURRENT (ma) 9.0 V. V T A ( C) IDDH, IDDH - LOGIC HIGH SUPPLY CURRENT (ma).0v.v T A ( C) Figure : Typical Propagation Delay vs. Temperature at.v Supply Voltage Tphl, Tplh (ns) 0 Tplh Tphl T A ( C) Figure : Typical Propagation Delay vs. Load Capacitance at.v Supply Voltage Tphl, Tplh (ns) 0 Tplh Tphl 0 C L (pf) Figure : Typical Pulse Width Distortion vs. Temperature at.v Supply Voltage PWD (ns) T A ( C) Figure : Typical Pulse Width Distortion vs. Load Capacitance at.v Supply Voltage PWD (ns) 0 C L (pf)

8 Figure : Typical Rise and Fall Time vs. Temperature at.v Supply Voltage Tr, Tf (ns) Rise Time Fall Time T A ( O C) Application Information Bypassing and PC Board Layout The ACSL-0 optocoupler is extremely easy to use. No external interface circuitry is required because ACSL-0 uses high-speed CMOS IC technology, allowing CMOS logic to be directly connected to the inputs and outputs. The only external components required for proper operation are two bypass capacitors. Capacitor value should be between 0.0 µf and 0. µf. The capacitor should be placed as close as possible to the power supply pins. Figure shows the typical application diagram for -MBd bidirectional ACSL-0 and 0-MBd ultra low-power ACPL-ML, providing isolation in PROFIBUS (RS) communication. ACSL-0 isolates the transmitting and receiving data channels while ACPL-ML isolates the transmit enable signal. Figure : Isolated PROFIBUS (RS) Communication with ACSL-0 and ACPL-ML C 00 nf Rx Tx V DD Isolation U V DD V DD V DD V OA V IA V IB V OB GND GND Rx Tx ACSL-0 V DD V DD V DD Isolation U U R R O V CC AN V DD R E_ B 0 V O D E A R CA GND Tx Enable D I GND 0 Tx Enable ACPL-ML RS Fieldbus Network (Twisted Cable)

9 For the SPI interface, the ACSL-0 is used for serial data in/out isolation (two channels bidirectional). The third channel clock signal isolation is provided by ACPL-0L, -MBd CMOS digital optocoupler. Figure 9 shows the SPI isolated communication between master and slave devices using ACSL-0 and ACPL-0L. Figure 9: Isolated SPI between Master and Slave Devices using ACSL-0 and ACPL-0L VDD VDD VDD VDD C U C U 00 nf C 00 nf C 00 nf 00 nf VDD VDD VDD VDD V NC VOA VIA To master device To slave device To master device To slave device NC VO VIB VOB GND GND GND GND ACPL-0L ACSL-0 9

10 , the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of and/or its affiliates in the United States, certain other countries, and/or the EU. Copyright All Rights Reserved. The term refers to Inc. and/or its subsidiaries. For more information, please visit reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by is believed to be accurate and reliable. However, does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

ACCL High Speed Quad-Channel 3/1 Digital Isolator. Data Sheet. Description. Features. Functional Diagram. Applications GND 1

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