ECOM 4311 Digital System Design using VHDL. Chapter 9 Sequential Circuit Design: Practice

Transcription

1 ECOM 4311 Digital System Design using VHDL Chapter 9 Sequential Circuit Design: Practice

2 Outline 1. Poor design practice and remedy 2. More counters 3. Register as fast temporary storage 4. Pipelined circuit 2

3 1. Poor design practice and remedy Synchronous design is the most important methodology Poor practice in the past (to save chips) Misuse of asynchronous reset Misuse of gated clock Misuse of derived clock 3

4 Misuse of asynchronous reset Poor design: use reset to clear register in normal operation. e.g., a poorly mod-10 counter o Clear register immediately after the counter reaches

5 Misuse of asynchronous reset 5

6 Misuse of asynchronous reset Problem Glitches in transition 1001 (9) => 0000 (0) Glitches in aync_clr can reset the counter How about timing analysis? (maximal clock rate) Asynchronous reset should only be used for power-on initialization Remedy: load 0000 synchronously 6

7 Remedy Remedy: load 0000 synchronously 7

8 Misuse of gated clock Poor design: use a and gate to disable the clock to stop the register to get new value E.g., a counter with an enable signal 8

9 Misuse of gated clock Problem Gated clock width can be narrow Gated clock may pass glitches of en Difficult to design the clock distribution network 9

10 Remedy: use a synchronous enable 10

11 Misuse of derived clock Subsystems may run at different clock rate E.g., second and minutes counter o Input: 1 MHz clock o Poor design: 11

12 o Better design 12

13 2. More counters Counter circulates a set of specific patterns Counter: o Binary o Gray counter o Ring counter o Linear Feedback Shift Register (LFSR) o BCD counter 13

14 Binary counter o State follows binary counting sequence o Use an incrementor for the next-state logic +1 r_next d q r_reg q clk clk reset reset 14

15 Gray counter: o State changes onebit at a time o Use a Gray incrementor 15

16 Gray counter: 16

17 Gray counter: 17

18 Gray counter: 18

19 Ring counter Circulate a single 1 E.g., 4-bit ring counter: 1000, 0100, 0010, 0001 n patterns for n-bit register Non self-correcting design Insert 0001 at initialization and circulate the pattern in normal operation Fastest counter 19

20 Ring counter 20

21 Ring counter 21

22 Ring counter This simple design makes this a very fast counter (much faster than binary cnter) 22

23 Self-correcting design: A self-correcting design ensures that a 1 is always circulating in the ring This is accomplished by inspecting the 3 MSBs if "000", then the combo. Logic inserts a 1 into the low order bit 23

24 Self-correcting design: 24

25 Self-correcting design: 25

26 LFSR (Linear Feedback Shift Reg) An LFSR is a shifter register that contains an XOR feedback network that determines the next serial input value Only a subset of the register bits are used in the XOR operation By carefully selecting the bits, an LFSR can be designed to circulate through all 2n-1 states for an n-bit register 26

27 E.g, 4-bit LFSR Note that the state "0000" is excluded -- if it ever shows up, the LFSR becomes stuck 27

28 Property of LFSR N-bit LFSR can cycle through 2 n -1 states The feedback circuit to generate a maximal number of states exists for any n The sequence is pseudorandom 28

29 Application of LFSR Pseudorandom: used in testing, data encryption/decryption 29

30 4-bit LFSR 30

31 4-bit LFSR 31

32 4-bit LFSR Read remaining of Section (design to including state) 32

33 Decimal Counter A decimal counter circulates the patterns in binary-coded decimal (BCD) format. The BCD code uses 4 bits to represent a decimal number. For example, the BCD code for the three digit decimal number 139 is " ". 33

34 Decimal Counter 34

35 Decimal Counter 35

36 Decimal Counter 36

37 Decimal Counter 37

38 PWM (pulse width modulation) Duty cycle: percentage of time that the signal is asserted PWM: use a signal, w, to specify the duty cycle Duty cycle is w/16 if w is not 0000 Duty cycle is 16/16 if w is 0000 Implemented by a binary counter with a special output circuit 38

39 PWM (pulse width modulation) 39

40 PWM (pulse width modulation) 40

41 PWM (pulse width modulation) 41

42 Register as fast temporary storage RAM RAM cell designed at transistor level Cell use minimal area Behave like a latch For mass storage Need a special interface logic Register D FF requires much larger area Synchronous For small, fast storage E.g., register file, fast FIFO, Fast CAM (content addressable memory) 42

43 Register file Registers arranged as an 1-d array Each register is identified with an address Normally has 1 write port (with write enable signal) Can has multiple read ports 43

44 E.g., 4-word register file with 1 write port and two read ports 44

45 Register file Register array: 4 registers with 16 bits Each register has an enable signal Write decoding circuit: 0000 if wr_en is 0 1 bit asserted according to w_addr if wr_en is 1 Read circuit: A mux for each read port 45

46 VHDL Implementation code A 2-D data type is needed here 46

47 VHDL Implementation code 47

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51 FIFO Buffer Elastic storage between two subsystems 51

52 FIFO Buffer Circular queue implementation Use two pointers and a generic storage Write pointer: point to the empty slot before the head of the queue Read pointer: point to the tail of the queue 52

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54 FIFO Buffer 54

55 FIFO controller Read and write pointers: 2 counters Status circuit: Difficult Design 1: Augmented binary counter Design 2: with status FFs LSFR as counter 55

56 Augmented binary counter: increase the counter by 1 bits Use LSBs for as register address Use MSB to distinguish full or empty 56

57 FIFO controller with Augmented counter 57

58 FIFO controller with Augmented counter 58

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60 2 extra status FFs Full_erg/empty_reg memorize the current staus Initialized as 0 and 1 Modified according to wr and rd signals: 00: no change 11: advance read pointer/write pointer; full/empty no change 10: advance write pointer; de-assert empty; assert full if needed (when write pointer=read pointer) 01: advance read pointer; de-assert full; asserted empty if needed (when write pointer=read pointer) 60

61 2 extra status FFs 61

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67 Other design Non-binary counter for the pointer Exact location does not matter as long as the write pointer and read pointer follow the same pattern Other counters can be used for the second scheme E.g, use LFSR 67

68 4. Pipelined circuit Two performance criteria: o Delay: required time to complete one task o Throughput: number of tasks completed per unit time. E.g., ATM machine o Original: 3 minutes to process a transaction delay: 3 min; throughput: 20 trans per hour o Option 1: faster machine 1.5 min to process delay: 1.5 min; throughput: 40 trans per hour o Option 2: two machines delay: 3 min; throughput: 40 trans per hour Pipelined circuit: increase throughput 68

69 Pipeline: overlap certain operation E.g., pipelined laundry: 69

70 Pipeline Non-pipelined: Delay: 60 min Throughput 1/60 load per min Pipelined: Delay: 60 min Throughput k/(40+k*20) load per min about 1/20 when k is large Throughput 3 times better than non-pipelined 70

71 Pipelined combinational circuit Basic idea is to divide the combinational logic into a set of stages, with buffers (registers or latches) inserted between each stage 71

72 Pipelined combinational circuit Given a pipeline with stage delays of T1, T2, T3 and T4, clock cycle time is bounded by : ADD the setup and clock-to-q delays of the pipeline registers In non-pipelined version, delay to process one item is For the pipelined version, its actually longer 72

73 Pipelined combinational circuit The win is actually w.r.t. the throughput metric For pipelined version, it takes 3*Tc time to fill the pipeline and the time to process k items is 3*Tc + ktc yielding : TP = k/(3*tc + ktc) which approaches 1/Tc for large k 73

74 Adding pipeline to a comb circuit Not all circuits are amenable to pipelines. The following criteria required for pipelining: o Data is always available for the pipelined circuit s inputs o System throughput is an important performance characteristic o Combinational circuit can be divided into stages with similar propagation delays o Propagation delay of a stage is much larger than the T setup and T cq of the register 74

75 Procedure Derive the block diagram of the original combinational circuit and arrange the circuit as a cascading chain Identify the major components and estimate the relative propagation delays of these components Divide the chain into stages of similar propagation delays Identify the signals that cross the boundary of the chain Insert registers for these signals in the boundary. 75

76 Pipelined comb multiplier 76

77 Pipelined comb multiplier The two major components are the adder and bit-product generation circuit Arrange this components in cascade as shown on the next slide, with the bitproduct labeled as BP The bit-product circuit is simply an AND operation and therefore has a small delay We combine it with the adder to define a stage 77

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79 Pipelined comb multiplier There are two types of pipeline registers One type to accommodate the computation flow and to store the intermediate results (partial products pp1,... pp4) Second type to preserve the info needed in each stage, i.e., a1, a2, a3, b1, b2, and b3 Since there are different multiplications occurring in each stage, the operands for any given multiplication must move along with the partial products 79

80 Pipelined comb multiplier 80

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89 Congratulation! Your first pipeline. 89

90 Any Questions?? 90