The Trigger System of the MEG Experiment

Transcription

1 The Trigger System of the MEG Experiment On behalf of D. Nicolò F. Morsani S. Galeotti M. Grassi Marco Grassi INFN - Pisa Lecce - 23 Sep

2 COBRA magnet Background Rate Evaluation Drift Chambers Target Timing Counters Simulation Simulation with GEANT 3.21 Proposal geometry Contribution correlated: irrelevant µ eυ υ γ accidental: main Xe Calorimeter µ eυ υ γ and e + e γγ µ eυ υ Lecce - 23 Sep

3 Event selection Kinematical variables - γ energy - γ direction - γ time - e + time - approx. e + direction - e + direction - e + energy Detectors Liquid Xe calorimeter entrance face : for energy, direction and time other faces : relevant only for the energy Timing Counters Counters along Z for time Counters along Z and ϕ for the direction Tracking chambers Information delayed with respect to LXe and TC Large number of channels Use YES YES NO Trigger Rate evaluation obtained with simple and intuitive reconstruction algorithms Other general algorithms have shown better performances Lecce - 23 Sep

4 Photon Energy LXe calorimeter charge = energy N QSUM = w Q w = i i i i Q i = PMT coverage density i-th PMT charge annihilation in flight total Background = 2 10 f γ 4 radiative decay Signal ε = 96 % λ ass = 100 cm λ Ryl = 30 cm 45 MeV threshold Lecce - 23 Sep

5 Photon Direction Maximum-charge PMT γimpact point on the inner calorimeter face highly efficient on the signal ε ( φ < 3.5 ) 99% ϕ Lecce - 23 Sep

6 e + - γ direction matching Z-ϕ hit counters = e + direction 2 Timing Counters Suppression factor for the θ coordinate f θ = 2 ϕ -bands matching Suppression factor for the ϕ coordinate f ϕ = 5 e + hit point on TC from µ eγ events Photon φ -range (±3σ) Timing counter coverage Lecce - 23 Sep

7 γ -e + time coincidence Signal leading-edge time = emission time some ns accuracy Safe choice: T = 10 ns coincidence window Lecce - 23 Sep

8 Trigger Rates Summary µ eυ υ γ Accidental background and rejection obtained by applying cuts on the following variables e + e γγ µ eυ υ photon energy photon direction hit on the positron counter time correlation T = 10 positron-photon direction match 8 R µ = 10 s Ω = 0.1 4π 1 E γ σ φ > 45 MeV ε 97% f γ ~ 2 10 o o = 1.2 ε ( φ < 3.5 ) > 99% R e 2 ns ε 100% = 5 10 s f θ = 2 ; f = 5 R ϕ = R f R + µ γ e 4 Ω T 4π fϑ f ϕ s The rate depends on R µ R e + R µ 2 Lecce - 23 Sep

9 The trigger implementation Digital approach Flash analog-to-digital converters (FADC) Field programmable gate array (FPGA) Good reasons Flexibility Complexity Common noise rejection Different reconstruction algorithms Easily and quickly re-configurable Lecce - 23 Sep

10 Hardware: system structure LXe inner face (312 PMT) LXe lateral faces (208 PMT) (120x2 PMT) (40x2 PMT) Type1 Type1 Type1 Type1 Type1 Type1 20 boards 20 x boards 10 x 48 Type2 Type2 Type2 2 boards 1 board 2 x 48 4 x 48 Type2 1 board or 6 boards Timing counters Type1 (160 PMT) 16 Type1 or Type1 (80 PMT) Type x 48 Type2 2 or 1 boards 4 x 48 2 VME 6U 1 VME 9U Lecce - 23 Sep

11 Hardware: board Type 1 FADC PMT x 10 FPGA VME 6U A-to-D Conversion Clock Sync Trigger Start 4 Sync 4 48 Control CPLD VME FADC with differential inputs bandwidth limited Trigger LXe calorimeter timing counters Acquisition Type 2 boards LVDS Trans 48 LVDS Trans 48 tracking chambers I/O 16 PMT signals 2 LVDS transmitters 4 in control signals Lecce - 23 Sep

12 Hardware: board Type 2 Type 1 Clock Sync Trigger Start Trigger Sync Start to next Type 2 10 x LVDS Rec Sync Out LVDS Trans LVDS Trans 10 x FPGA 48 Control CPLD VME VME 9U Matched with the Type 1 boards I/O 10 LVDS receivers 2 LVDS transmitters 4 in control signals 3 out signals Lecce - 23 Sep

13 Trigger types Standard acquisition trigger use of all variables of the photons and the positrons with baseline algorithms Debugging triggers release of 1 or 2 selection criteria at the time for a fraction of normal triggers Calibration triggers connection of auxiliary external devices (calorimeters) through further Type1 board selection of µ eννγ events for timing Different, more performing, triggers hardware is dimensioned to support other algorithms (Principal Component Analysis) Readout of the trigger system and detector status for each trigger the trigger configuration and status is read out for a fraction of the triggers the entire 100 MHz waveform buffers are read out for a fraction of the triggers the rates of each analog channel (LXe and TC) are readout Lecce - 23 Sep

14 Trigger system simulation PMT signals Fit to a real PMT pulse of the large prototype + Random noise + Sinusoidal noise Simulation with abnormal noise figures Lecce - 23 Sep

15 Pedestal and noise subtraction: 1 Excellent algorithm performance to suppress DC Pedestal Low frequency (<400KHz) noise Lecce - 23 Sep

16 Pedestal and noise subtraction: 2 First critical frequency First optimal frequency Lecce - 23 Sep

17 Pedestal and noise subtraction: 3 High frequency noise (>15 MHz) is not amplified. But FADC inputs must be bandwidth limited (< 40MHz) The critical frequency can be tuned in the range 1-4 MHz, after having measured the real noise level Lecce - 23 Sep

18 Other algorithms The charge sum algorithm The reconstructed-generated times are within the 10 ns tolerance even in presence of unacceptable noise and The maximum charge PMT search do not have difficulties Lecce - 23 Sep

19 Prototype board: Type0 Modified Type1 : Present status Check of the connectivity with the Type2 Study the FADC coupling Verify the chosen algorithms Selected components Main FPGA XCV812E-8-FG900 and XCV18V04 config. ROM Interface and control CPLD XC95288XL-FG256 ADC AD9218 (dual 10 bits 100 MHz) Clock distribution CY7B993V (DLL multi-phase clock buffer) LVDS serializer DS90CR483 / 484 (48 bits MHz Gbits/s) LVDS connectors 3M Mini-D-Ribbon Analog input by 3M coaxial connectors Control and debug signals in LVDS standard FPGA design completed FPGA design and simulation completed (runs at 100 MHz) Behavioural model imported in CADENCE Lecce - 23 Sep

20 16 x 10 Analog MT 16 FADC receivers Clock Sync Trigger Start Sync Trigger Start Spare in/out 4 3 Prototype board : Type 0 Sync Out LVDS Trans LVDS Rec FPGA Control CPLD 48 VME VME 6U A-to-D Conversion Trigger I/O 16 PMT signals 2 LVDS transmitters 4 in/2 out control signals Complete system test 2 boards Trigger Start Type0 Type0 Lecce - 23 Sep

21 Board design Implemented with CADENCE routing 10 layers (4 GND/Power 6 signals DC/DC converters A32 mode Block transfer Board DELIVERED Footprints checked OK DC/DC mounted: voltage OK (noise 15 mv peak to peak ) Board completion Component mounting: done Test: September Lecce - 23 Sep

22 Final system Trigger location: platform or counting area Spy buffers to check the data flow JTAG programming/debugging through the VME Further developments Virtex or VirtexII Main FPGA XCV812E-8-FG900 and XCV18V04 config. ROM Connectors Analog input by 3M coaxial connectors Ancillary boards: distribution of control signals Analog section moved to the fan-out boards: 20 chan/board Final prototypes (Type1 and Type2) first half 2004 Cost 23k If tests are ok start of the mass production Estimatedproduction and test 1 year Lecce - 23 Sep

23 Jan Jan 2002 Trigger Prototype Board 2 nd Prototype Full System Lecce - 23 Sep Design Manufactoring Assembly Test Milestone