ENGR-4300 Spring 2008 Test 3. Name SOLUTION. Section 1(MR 8:00) 2(TF 2:00) 3(MR 6:00) (circle one) Question I (20 points) Question II (20 points)

Size: px

Start display at page:

Download "ENGR-4300 Spring 2008 Test 3. Name SOLUTION. Section 1(MR 8:00) 2(TF 2:00) 3(MR 6:00) (circle one) Question I (20 points) Question II (20 points)"

Philippa James
5 years ago
Views:

1 NGR- Test Spring 8 NGR- Spring 8 Test Name SOLUTION Section MR 8: TF : MR 6: circle one Question I points Question II points Question III points Question IV 5 points Question V 5 points Total points: On all questions: SHOW LL WORK. GIN WITH FORMULS, THN SUSTITUT VLUS ND UNITS. No credit will be given for numbers that appear without justification. of

2 NGR- Test Spring 8 Question I stable Multivibrator points The 555 timer circuit shown is found to have an output on pin plotted below. R k, R k,.7µf. pt alculate the period of the output signal. T.69R xr T.69k.7µ.s V 9Vdc R R u V 8 X TRIGGR RST OUTPUT ONTROL THRSHOLD DISHRG GND 555D Rload. pt alculate the duty cycle of the output. Duty cyclet/trr/rr / 5.%. pt If an LD were properly driven by pin above, would your eye be able to detect the flashing? Frequency /T /. 5Hz YS, slow enough to detect flashing with eye. pt TRU or FLS: If R is increased, both the frequency and duty cycle will increase. FLS frequency and duty cycle will both decrease 5. pt dd traces to the plot sketching the voltages on pin and of the circuit above and be sure to label each. V 8V 6V V V V s.s.s.6s.8s.s V Time of

3 NGR- Test Spring 8 V 8V 6V V V V s.s.s.6s.8s.s VR: V: Time Vpin swings between V and 6V / & / of 9V Vpin is either grounded V or 9V actual voltage is ~7V of

4 NGR- Test Spring 8 Question II ombinational Logic ircuits points. 8pt For the following circuit, complete the truth table. That is, find the four outputs for all possible input conditions. Note that it is not necessary to fill out the entire table of values at all possible locations in the table, but this is the best way to solve this problem. It will also help us to understand where you may have gone wrong if your answers for the three outputs are not correct. Note that the circuit is very well labeled so you can easily identify which location goes with each letter. I D H G J F K L D F G H I J K L NOT FROM TL: I J and K L of

5 NGR- Test Spring 8 5 of Question II ombinational Logic ircuits continued. pt Write the oolean expressions for I, J, K, and L in terms of,, and, their inverses overbars on variables, and logic operators ND, OR, and NOT. L K J I. pt From columns I & J or K & L in the table, what property is being demonstrated or describe in words what can be observed about these logical expressions? DeMorgan s Principal: Inverting the inputs to an OR gate and inverting its output yields the same results as an ND gate Inverting the inputs to an ND gate and inverting its output yields the same results as an OR gate. pt For,,, D, and, what is the value of the expression: D D? D D.

6 NGR- Test Spring 8 Question III Sequential Logic ircuits points OFFTIM.5mS DSTM ONTIM.5mS LK DLY STRTVL OPPVL V U 7 V U7 7 J Q LK Q K LR U 77 OFFTIM.S DSTM ONTIM.mSLK DLY STRTVL OPPVL V U Q Q Q 5 QD 6 LR 79 U6 7 U 7 V In the circuit pictured above, clock DSTM provides a clock signal to a counter and a flip flop. The flip flop is clocked one half cycle after the counter to allow for the propagation of the signals through the gates. DSTM provides an initial reset pulse to both chips. This is required by PSpice to ensure that all sequential devices start in a known state.. pt The timing diagram below shows the reset pulses and the clock signals. Sketch the following signals in the space provided: the output from the timer U:Q, U:Q, U:Q, and U:QD; the output from the combinational logic U7:Y and U6:Y; and the output from the flip flop U:Q. DSTM: :LRbar DSTM: U:Y Q Q Q QD J K Q s.ms.ms.ms.ms 5.ms 6.ms Time 6 of

7 NGR- Test Spring 8 Question III Sequential Logic ircuits continued. pt From your knowledge of working with the 79 counter in the studio, which output bit represents the bit in a binary number formed from the four bits generated by the counter? Q. pt ssume that Q and J K. ased on the truth table of the J-K flip-flop above, how will the output Q behave when this device is clocked while pin is false low? Pin is the low-active clear so the flip-flop will remain cleared as long as is low. The output Q will remain low.. pt -bit 79 counter s current state is. It receives a string of clock pulses starting with a low to high transition. What are Q, Q, Q and QD after the th clock pulse s rising edge? learly indicate the state of each signal. QD Q Q Q Only counts on falling edge of clock. 6 pulses 7 > 7 of

8 NGR- Test Spring 8 DSTM: U:Y DSTM: U:Y U:Q U:Q U:Q U:QD U:J U:K U:Q s.ms.ms.ms.ms 5.ms 6.ms Time 8 of

9 NGR- Test Spring 8 Question IV Switching ircuits 5 points k V 5Vdc V k Q V VQ Q Q R5 k Q Vout Va k Vb k Vc k. pt Replacing the transistors in the above circuit with diodes and switches, redraw the above circuit when inputs Va V, Vb V, and Vc V, replacing the open or closed switches with open or short circuits. k 5Vdc V k VQ R8 k Vout Va k Vb k Vc k. pt Find the values of the voltages VQ and Vout for these inputs. VQ ~.5V [actual VQ 5 -.7/.7.85] Vout V.5 pt off for VQ 5V 9 of

10 NGR- Test Spring 8 Question IV Switching ircuits continued. pt Replacing the transistors in the above circuit with diodes and switches, redraw the above circuit when inputs Va V, Vb V, and Vc V, replacing the open or closed switches with open or short circuits. k 5Vdc V k VQ R k Vout Va k Vb k Vc k. pt Fill in the table below: Va Vb Vc VQ Vout V V V ~.5V V V V V V 5V V V V V 5V V V V V 5V V V V V 5V V V V V 5V V V V V 5V V V V V 5V 5. pt What logic function does this circuit perform assume V & >V? -Input OR GT of

11 NGR- Test Spring 8 Question V omparators and Schmitt Triggers 5 points. pt Given the circuit below, find the erence voltage for the Schmitt Trigger if the desired switching voltages are 7V and -5V when R k and R k. ssume the op-amp output voltages will be equal to the supply voltages. v v v v v high low high R R R V v k k k k k k out V 9 v 9 v 9 v V v v v 7V 5V 6 v 7V V R V u7-7 9Vdc V- OS OUT 6 OS 5 V 9Vdc R v. pt On the axes below sketch the input-output curve for the circuit in. e sure to scale both axes. Vout Vin pt Find the width of the hysteresis band include units for the circuit above. and v high v low 7-5 V of

12 NGR- Test Spring 8 Question V omparators and Schmitt Triggers continued. pt Given the comparator circuit on the right, assume the op-amps are powered by 5V and ground to provide a binary logic value on outputs D. ssuming the standard low V is a binary and high 5V is a binary, what is the expected binary output D when Vin V? V is below all the op-amp erence voltages so all outputs will be low V D Vdc Vin k k - - OUT OUT OUT D k - 5 pt What is the expected binary output D when Vin 5V? k - OUT 5V is above all the op-amp erence voltages V, V, V, & V for,,, & D so all outputs will be high 5V D 6. 6pt What range of Vin would produce an output D? V <Vin < V for & outputs HIGH 5V and & D outputs LOW V 7. pt Will this circuit produce a normal digital output for an increasing Vin from to 5 V, i.e. a sequence of,,,,? xplain why or why not. NO, the binary output will be,,,, for increasing Vin. Once Vin exceeds the erence input for a given comparator, the output will stay at. This is called a temperature gauge binary output. of

13 NGR- Test Spring 8 Vout 9V -5V 7V Vin -9V of

ENGR-4300 Fall 2008 Test 3. Name. Section 1(MR 8:00) 2(TF 2:00) (circle one) Question I (20 points) Question II (15 points) Question III (20 points)

ENGR-4300 Fall 2008 Test 3. Name. Section 1(MR 8:00) 2(TF 2:00) (circle one) Question I (20 points) Question II (15 points) Question III (20 points) ENGR-43 Fall 8 Test 3 Name Section (MR 8:) (TF :) (circle one) Question I ( points) Question II (5 points) Question III ( points) Question I ( points) Question (5 points) Total ( points): On all questions: