Synchronizing Receiver Node Hardware Operations and Node M&C and hardware Interaction: Version 1.0

Transcription

1 RRI Internal Technical Report Library ref no. TR: AA Synchronizing Receiver de Hardware Operations and de M&C and hardware Interaction: Version 1.0 Authors: D. Anish Roshi 1 Affiliation: 1 Raman Research Institute, Bangalore, India Date: June 5, 2007, (v1.01) Class: MWA: Receiver de Abstract This report describes the synchronization of state machines in the receiver node. The basic functions of the de M&C, its interaction with the Receiver de hardware and the needed synchronization s for the M&C are discussed. Method to generate the bit at the des with the proper delay is also described. 1 Introduction We consider that the MWA will be synchronized using a centrally generated clock and synchronization. Fig. 1 shows the schematic of the clock and synchronization distribution for the array. In this report, we consider the generation of synchronization s at the receiver node based on this scheme. The sampling clock is assumed to be 660 MHz (CLK), which is generated at the des from the reference clock (REF CLK). The synchronization scheme does not depend on the actual value of the clock. The basic integration cycle needed for calibration is 8 sec (Briggs 2007a). So we consider that the period of the primary synchronization to be CLK cycles, which is about 8.13 sec. Following Briggs (2007a) we refer to this as (Start Counting Ticks w). 2 and s at the Receiver node Fig. 2 shows the and propagation delays due to their distribution. One of the requirements of the clock and synchronization (CLK/SYNCH) circuit at the de is to compensate the differential delay of due to τ i. This compensation will align the synchronization at the des. Since the differential delay can change with time, the delays should be programmable from the LM&C (local Monitor and control). The accuracy of this delay compensation will be +/ half the reference clock (REF CLK) period distributed from the central station. The s are generated at the Receiver de and are distributed to the 8 Tiles that are connected to the de. The propagation delay due to this distribution (τ β ij; i is the de number and j is the Tile number) as well as the cable delay suffered by the need to be compensated to demodulate the in the ADFB (Analog-to-Digital converter Filter Bank) board. This delay compensation can be in the generation board (see Section 4). The accuracy to which this delay needs to be adjusted is set as 50 nsec. 1

2 Basic Reference oscillator 10 MHz Reference clock synthesizer Phase Modulator To correlator To Central M&C generator (8sec period) Clock distributor To RTM module 1 To RTM module 60 Optical fiber Optical fiber Figure 1: Clock and Synchronization distribution Central clock /REF_CLK central τ1 Clk/Synch generator τ2 /REF_CLK de1 τα11 τβ11 τα18 τβ18 Tile1 Tile8 Synch to the correlator de2 τα21 τβ21 Tile1 τα28 τβ28 Tile8 Figure 2: Delay suffered by, and from the Tile 2

3 (Captured & delayed) adjust the width as required by LM&C M (to LM&C; period 8 sec) clk/synch from central station REF_CLK/ (8sec period) Clk cleaning & synch capturing at receiver node CLK CLK (660 MHz) REF_CLK Programing delay from LM&C Delay the captured synch Lsynch Generate Lsynch (160 msec period) REF_CLK Lsynch Divide by 10 and adjust the width for LM&C Synch for the LM&C as interrupt; period 1.6 sec REF_CLK Clock for walsh and synch for Wsynch (period 160 msec) Wclk (about 20 MHz) Figure 3: Clock recovery and capturing blocks at the Receiver de 3 Local Synchronization s needed at the Receiver de and their requirements The period is considered to be 10 msec (Briggs 2007b). 16 states are required for the two polarizations of the 8 Tiles connected to a de. Thus the cycle period is 160 msec. The hardware operations in a FPGA in the ADFB will be synchronized with a with the cycle period. We refer to this synchronization in the ADFB as Lsynch (Local synchronization ) The Lsynch generated at different FPGAs in ADFB boards has to be synchronized, which is done using the delay compensated SNTC (see Fig. 3). The current thinking is that the Data Aggregation and Formatting (AgFo) board will also use. The synchronization needed for the generation, Wsynch, will have a periodicity of cycle (see Section 4). The LM&C will be provided with two synchronization s M and (see Section 6). M has the same periodicity of but the pulse width is adjusted as required by the single board computer. is generated at 1.6 sec, which the LM&C will use to read the hardware status registers (see Section 6). 4 generation at the Receiver de The states are generated with a clock (Wclk) which is derived from the reference clock. As mentioned above, the send from the Receiver de suffers a delay τ β ij, before it reaches the multiplier in the Tile electronics. The from the telescope after the phase flip introduced by the modulation suffers a delay of τ α ij before it reaches the ADC. The demodulation is done at the output of the ADC and this hardware process needs to know the total 3

4 τ1 delay compensated de 1 Central at de 1 for tile 1 τα11+τβ11 mode of tile 1 for tile 8 τα18+τβ18 mode of tile 8 τ2 delay compensated de 2 Central at de 2 for tile 1 τα21+τβ21 mode of tile 1 for tile 8 τα28+τβ28 mode of tile 8 Figure 4: Timing diagram showing the generation of synchronization and pattern at the Receiver de delay. To align the demodulation process with the phase transition in the telescope, the states are advanced by τ α ij + τ β ij (see Fig. 4). We consider that the accuracy of the delay compensation of states be about 50 nsec. This delay compensation is achieved with Wclk and hence its frequency should be about 20 MHz. A block diagram for generating is shown in Fig. 5. The sequence is re-synchronized at the end of cycle using Wsynch. 5 Do we need delay compensation at the receiver node? τ α ij is not the same for the 8 Tiles in a de. If MWA uses cables of standard lengths 150, 100 and 50 meters, then the maximum delay between the Tiles in a de is 0.5 microsec, which is ten times smaller than the maximum expected geometric delay. Therefore it is not necessary to compensate for the delay between the Tiles in a de. 6 Synchronizing M&C and the Receiver de The LM&C will be provided with two synchronisation s (M and ; see Fig. 3). M has a periodicity of 8 sec. LM&C can use MSTNC to determine the boundary of the basic integration cycle., which has a period of about 1.6 sec, can be used to read the status registers in the hardware. Fig. 6 and 7 give, respectively, the state and timing diagram for the de M&C operation. 4

5 16 Pattern 16 states (32 Byte mem) Address 100 Hz Offset1 delay logic1 Wclk delay logic16 Offset16 Synch Clock circuit Wclk (about 20 MHz) (from CLK/SYNCH ckt in the de) 1 16 To Tiles Wsynch (about 160 msec period) (from CLK/SYNCH ckt in the de) Interface to LM&C (to load walsh/offset values) 1Bit flag indicating loss of synchronization Figure 5: Block diagram of pattern generation at Receiver de start Intialize Hardware Start hardware state m/c Wait for M Wait for I1 Update info on interrupt M I2 Update M info on interrupt Take action Take action Yes Need any update of hardware config Check Yes M and period Get info on integration cycle number from M interrupt Read temperature and voltage values Check any bad thing happening at the de Yes Read hardware status/pwr register Check any flags are set Send power values to M&C Yes Send bad flag to central M&C with priority Take action Figure 6: State diagram for the Receiver de M&C 5

6 1.6sec period These are interrupts for the de M&C Do the listed task during each period after start of observations. Read hardware status/power reg Check any flag is set; send bad flag to central M&C if falg is set send power to the central M&C M 8sec period These are interrupts for the de M&C Do the listed task during each M period. Read temperature and voltage values Check anything bad happening in the node; alert central M&C and take appropriate action if things are bad Check the period of Ssynch and STNC; if not good altert central M&C and take action If any config update needed do that; discard read hardware reg and send bad flag to the central M&C Update local info on the integration cycle and send that number to the central M&C Acknowledgment Figure 7: Timing diagram of the M&C operations I acknowledge the many useful discussions I had with Annino, Frank, Mark and Prabu which helped to bring the work reported here to the present state. Reference Briggs, F., 2007a, January 7, MWA Knowledge Tree Briggs, F., 2007b, February 25, MWA Knowledge Tree Revision History V1.0 June 5, 2007 V1.01 July 25, 2007 is needed at ADFB for synchronization. So it has been decided to provide only from the node clock and synch circuit. The 160 msec period Lsynch will be generated inside the ADFB FPGAs. 6