Xilinx Implementation of Pulse Width Modulation Generation using FPGA

Transcription

1 Volume-7, Issue-1, January-February 2017 International Journal of Engineering and Management Research Page Number: Xilinx Implementation of Pulse Width Modulation Generation using FPGA Rahul Patel 1, Prof. Vijay Prakash Singh 2 1 (M.Tech Student) Department of Electronics and Communication, SSSUTMS University, Sehore, INDIA 2 Department of Electronics & Communication Engineering, SSSUTMS University, Sehore, INDIA ABSTRACT Multi level inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower EMI generation, better output waveform and higher efficiency for a given quality of output waveform. In this paper a XILINX FPGA based multilevel PWM controller design is simulated and compilation portion is tested through VHDL in real time process using hardware-co simulation. The effective controller maintains the voltage to frequency ratio constant. The simulation with experimental results demonstrates quality of voltage and current waveforms with less harmonic content at the output of the cascaded inverter. In this paper we have implemented multilevel inverter using FPGA for the hardware implementation of proposed methodology. Keyword-- Cascaded Multilevel Inverter, FPGA, Pulse Width Modulation, XILINX. I. INTRODUCTION Multilevel inverters have been attracting increasing attention in the past few years as power Inverters of choice in many applications. They have significant advantages over the conventional one because of the capability to reduce the undesirable harmonics in order to improve the performance and efficiency. Various topologies to realize these inverters have been introduced and studied recently. Waveform synthesis methods for these inverters include staircase modulation, sine-triangle carrier modulation, space vector modulation, and other predictive methods. Normally the topological structure of multilevel inverter suggested must cope with the following points: 1) It should have less switching devices as far as possible, 2) It should be capable of enduring very high input voltage such as HVDC transmission for high power applications, and 3) Each switching device should have lower switching frequency owing to multilevel approach. PWM generation is considered the more important in the inverter design and several multicarrier techniques have been developed to reduce the distortion in multilevel inverters, based on the classical (SPWM) with triangular carriers. Some methods use carrier disposition and others use phase shifting of multiple carrier signals. [1] Xilinx field programmable gate arrays (FPGA's) are standard integrated circuits that can be programmed by a user to perform a variety of complex logic functions. The high level of integration available with these devices (currently up to 500,000 gates) means that they can be used to implement complex electronic systems. Furthermore, there are many advantages due to the rapid design process and reprogrammable functions. XILINX FPGA enables to produce prototype logic designs right in a short period. It is possible to create, implement, and verify a new design. This is a sharp contrast to conventional gate array design processes, which can take months to produce working silicon. The FPGA architecture consists of three types of configurable elements - a perimeter of input/output blocks (IOBs), a core array of configurable logic block (CLBs), and resources for interconnection. The IOBs provide a programmable interface between the internal array of logic blocks (CLBs) and the device's external package pins. CLBs perform user-specified logic functions, and the interconnect resources carry signals among the blocks. A configuration program stored in internal static memory cells determines the logic functions and the interconnections. The configuration data is loaded into the device during power-up reprogramming functions. [1] II. PROPOSED METHODOLOGY This details a pulse width modulation (PWM) generator component for use in CPLDs and FPGAs, written in VHDL. The component outputs PWM signals based on the duty cycle set by user logic. The center of each pulse occurs at the PWM frequency, and the pulse width varies around the center. If set to multiple phases, the component generates one PWM signal for each phase, evenly spaced. For example, when set to three phases, it generates three PWM outputs 120 out-of-phase with one another. The component was designed with Quartos II, version 12.1 and tested with ModelSim Altera 10.1b. Resource requirements depend on the implementation. Fig. 1 illustrates a typical example of the PWM generator integrated into a system. 411 Copyright Vandana Publications. All Rights Reserved.

2 Figure 1: Example Implementation A. Theory of Operation The system clock divided by the PWM frequency equals the number of system clock pulses in one PWM period. Counters define this PWM period for each phase. There is one counter for each PWM phase, with their values offset by the phase. Each counter increments on each system clock and clears once it reaches the end of its period. The duty cycle determines the points during the period when the PWM signal s rising and falling edges occur. Figure 2 illustrates the basic concept used to determine these positions. The signal s falling edge happens at ½ duty cycle, and its rising edge happens at the end of the period minus ½ duty cycle. Once the counter reaches each of these positions, the PWM signal is toggled as appropriate. Since a half duty cycle can never exceed a half period, the falling edge always occurs before the rising edge. Table 1: Generic Parameters Generic Data Description Type sys_clk Integer System clock frequency in Hz. pwm_freq Integer Frequency of PWM in Hz. bits_resolution Integer The number of bits of resolution setting the duty cycle. Phases Integer The number of output PWMs and phases. Design properties of any project play s an important role for project implementation. In the design properties the main things are use the change the target device project information. For details, see Changing Design Properties. Figure 3 shows all the parameter with specification of parts. Figure 3: Design Properties B. RTL View of Proposed Work Figure 2: Waveform of a Pulse in Phase with the PWM Period The PWM generator is configured using four GENERIC parameters, set in the ENTITY. Table 1 lists the parameters. The PWM generator does not require a specific input clock, so long as the user sets the sys_clk parameter to the clock frequency provided. The parameter pwm_freq corresponds to the PWM frequency. The bits_resolution determines the resolution of the pulse width. For example, a value of 8 provides 8 bits of resolution. Therefore, the pulse width s resolution is 28 or 256, so in this case, the finest possible pulse width adjustment is the period (i.e. 1/pwm_freq) divided by 256. The parameter phases sets the number of outputs and their relation to one another. The number of PWM outputs is phases, and these outputs are 360 /phase s out-of-phase with one another. Figure 4: RTL Design View After the HDL synthesis phase of the synthesis process, you can display a schematic representation of your synthesized source file. This schematic shows a representation of the pre-optimized design in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates, that are independent of the 412 Copyright Vandana Publications. All Rights Reserved.

3 targeted Xilinx device. Viewing this schematic may help you discover design issues early in the design process. III. SIMULATION AND RESULTS The output and the result of proposed method is show in the ModelSim. ModelSim is a multi-language HDL simulation environment by Mentor Graphics, for simulation of hardware description languages such as VHDL, Verilog and System C, and includes a built-in C debugger. ModelSim can be used independently, or in conjunction with Altera Quartus or Xilinx ISE. Simulation is performed using the graphical user interface (GUI), or automatically using scripts. For any type of switching generation the first basic phenomena is generation of sin wave so first generate the sine wave on the ModelSim. Further implement the different switching technique for PWM and other for hybrid implementation. Figure 5 shows the VHDL coded ModelSim output of sine wave. In the VHDL inbuilt i-sim simulator but that is not sufficient to show the sin wave in the simulator that s why for the representation of sin wave use the ModelSim simulator. of the cascaded inverter. Fig 6 shows the sinusoidal wave and 1800 phase shift sinusoidal wave (inverse sinusoidal wave) as a reference signals. Figure 6: Sinusoidal wave as a reference signal The three carrier signals (such as sawtooth waves) are generated using an up-counter design. The first sawtooth carrier signal is generated from 20-bit up counter and these signals phase are shifted to 1200 for second sawtooth carrier signals and 2400 for third sawtooth carrier signals. Fig 7 shows each sawtooth wave starts from different amplitude with 1200 phase shift. This sawtooth wave amplitude is V, -800 V, and +900 V to V. Figure 5: Sine Wave implementation The Xilinx Block set is a powerful graphical modeling tool which allows digital complex systems to be designed using a block diagram methodology. The system generator allows the modeling of digitized systems, which can be transformed into ModelSim atmosphere and targeted at a Xilinx FPGA board. Automatic generation of the bit stream is supported with the synthesis and implementation tools run within the ModelSim as well as Xilinx environment. The design is verified and tested both in ISE/Xilinx impact and ModelSim. The system is investigated by resistive and inductive (RL-load) loads. The simulation results are investigated and the waveform of output voltage and load currents obtained contains fewer harmonic. The desired reference speed RMS value is converted to digital fixed point value for digital-design. The discrete reference value set the amplitude and the frequency according to voltage and frequency ratio. The amplitude and frequency with 14-bit ROM device are generated in two reference sinusoidal signals. These maintain the voltage to frequency ratio constant by controlling the output voltage Figure 7: each saw tooth wave starts from different amplitude The Very High speed integrated circuits Hardware Description Language (VHDL) can be used to model a digital system at many levels of abstraction, ranging from the algorithmic level to gate level with high degree of complexity. Figure 8 shows the decimal value, bit waveforms of ADC reference speed value, amplitude and frequency. It also shows sinusoidal wave, 1800 phase shift sinusoidal wave (inverse sinusoidal) for reference signals, up-counter, 1200 phase shift up counter and 2400 phase shift up-counter for carrier sawtooth signals. The 12- channel gate control signals are generated from the comparison of two reference sinusoidal signals and three carrier saw tooth-signals. The VHDL program generated from the system is generated using Simulink platform. Fig. 413 Copyright Vandana Publications. All Rights Reserved.

4 8 shows, 12-gate switching pulses and clock signals to drive the single-phase cascaded multilevel inverter for 7-level output voltage. Figure 8: Final output of proposed System on Model Sim IV. CONCLUSION This controller design is simulated and compilation portion is tested through VHDL in real time process using hardware-co simulation. The effective controller maintains the voltage to frequency ratio constant. The simulation with experimental results demonstrates quality of voltage and current waveforms with less harmonic content at the output of the cascaded inverter. These inverter topologies with digital-control circuit can be used for speed control of induction motor and other medium scale industrial applications. At last but not least done the design and implementation of different switching techniques and hardwired digital circuits. The proposed work done is implementation on a novel discrete time control technique for hybrid inverter system by using pulse width modulation is on VHDL-front end. Platform. Because of growing interest in miniaturization and production of systems, digital control schemes based on VLSI technology and microprocessor for PWM inverters are becoming increasingly popular today for motor drives PV systems and UPS. In future try to make more different type multilevel inverter (MLI). A part from PWM focus on other switching generator architecture which was downloaded onto FPGA can be used to control Gate signal of Power Switches of Inverter. By this way we can be able to control ON and OFF time of Inverter. Hence we can use this architecture for controlling Inverter which produces AC from DC source. Hence we can implement PWM Inverter from this FPGA based PWM Generator. FPGA enables easy, fast and flexible implementation of the controller circuit in hardware. It can adjust effectively the modulation index range for varying speed control of induction motor drive. REFERENCES [1] Saad MeHuIef, N. A. Rahim, Xilinx FPGA Based Three-Phase PWM Inverter And Its Application For Utility Connected PV System, Proceedings of IEEE TENCON [2] S. Mekhilef, A. Masaoud, Xilinx FPGA Based Multilevel PWM Single Phase Inverter, Electronic Journal of University Malaya (EJUM), Vol.1, No 2 December 2006 pp [3] Karuppanan P, AyasKanta SWAIN, KamalaKanta Makapatra, FPGA Based Single-Phase Cascaded Multilevel Voltage Source Inverter Fed ASD Applications, Journal of Electrical Engineering, [4] Jagdish Kumar, Biswarup Das, and Pramod Agarwal, Harmonic reduction technique for a cascade multilevel inverter International Journal of Recent Trends in Engineering, vol.1, no. 3, May [5] Jin Wang and Damoun Ahmadi, A precise and practical harmonic elimination method for multilevel inverters IEEE Transactions on Industry Applications, vol. 46, no. 2, pp , March/April [6] Swamit S. Tannu Dr. R. R. Sawant Dr. Y. S. Rao, Discrete Time Control Technique for Induction Heating System, IEEE, International Conference on Communication, Information & Computing Technology (ICCICT), Oct [7] M. Mythili, N. Kayalvizhi, Harmonic Minimization in Multilevel Inverters Using Selective Harmonic Elimination PWM Technique, 2013 International Conference on Renewable Energy and Sustainable Energy [ICRESE 13], IEEE [8] Ahmed Belkheiri1, Said Aoughellanet1, Mohammed Belkheiri, Abdelhamid Rabhi, FPGA based Control of a PWM Inverter by the Third Harmonic Injection Technique for Maximizing DC Bus Utilization IEEE, May [9] M.F.M Sabri, M.H. Husin, I. N. Othman, Development of 5-bit, 4-Inputs PWM Generator on FPGA through VHDL Programming International Conference on Advances Science and Contemporary Engineering 2012(ICASCE 2012). [10] Ahmed Belkheiri1, Mohammed Belkheiri, Said Aoughellanet and A. Rabhi, FPGA implementation of configurable three-phase SPWM module, Conference Paper August [11] ToleSutikno, MochammadFacta, An Efficient Strategy to Generate High Resolution Three-Phase Pulse Width Modulation Signal Based on Field Programmable Gate Array, International Journal of Computer and Electrical Engineering, Vol. 2, No. 3, June, [12] Afarulrazi Abu Bakar, MdZarafi Ahmad and Farah Salwani Abdullah, Design of FPGA Based SPWM Single Phase Inverter, Malaysian Technical Universities Conference on Engineering and Technology, Malaysia. June 20-22, [13] Afarulrazi Abu Bakar, MdZarafi Ahmad and Farah Salwani Abdullah, Design of FPGA Based SPWM Single Phase Inverte, Malaysian Technical Universities Conference on Engineering and Technology June 20-22, 2009, [14] Kariyappa B. S1 Dr. M. UttaraKumari FPGA Based Speed Control of AC Servo motor Using Sinusoidal PWM,IJCSNS International Journal of Computer Science and Network Security, VOL.8 No.10, October [15] M. N. Md Isa, M.I. Ahmad, Sohiful A.Z. Murad and M. K. Md Arshad, FPGA Based SPWM Bridge Inverter, 414 Copyright Vandana Publications. All Rights Reserved.

5 American Journal of Applied Sciences 4 (8): , 2007 ISSN [16] Eftichios Koutroulis, Apostolos Dollas, Kostas Kalaitzakis, High-frequency pulse width modulation implementation using FPGA and CPLD ICs, Journal of Systems Architecture 52 (2006) [17] Rahim N.A. and Islam Z., Field Programmable Gate Array-Based Pulse-Width Modulation for Single Phase Active Power Filter ; American Journal of Applied Sciences, Vol.6 (2009): pp [18] Koutroulis E., Dollas A. and Kalaitzakis K., Highfrequency pulse width modulation implementation using FPGA and CPLD ICs, Journal of Systems Architecture, Vol.52 (2006): pp [19] Rahim, N.A. and Islam Z., A single-phase series active power filter design, Proceeding of the International Conference on Electrical, Electronic and Computer Engineering, IEEE Xplore Press,Sept. 2004, pp: [20] Dong Kim, Eui-Cheol Nho, Heung-Geun Kim, and Jong Sun Ko, A Generalized UndelandSnubber for Flying Capacitor Multilevel Inverter and Converter. IEEE transactions on industrial electronics, vol. 51, no. 6, December Copyright Vandana Publications. All Rights Reserved.