A silicon-on-glass single-pole-double- throw (SPDT) switching circuit integrated with a siliconcore

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1 HOME SEARCH PACS & MSC JOURNALS ABOUT CONTACT US A silicon-on-glass single-pole-double- throw (SPDT) switching circuit integrated with a siliconcore metal-coated transmission line This article has been downloaded from IOPscience. Please scroll down to see the full text article J. Micromech. Microeng ( The Table of Contents and more related content is available Download details: IP Address: The article was downloaded on 15/08/2008 at 06:23 Please note that terms and conditions apply.

2 IOP PUBLISHING JOURNAL OF MICROMECHANICS AND MICROENGINEERING J. Micromech. Microeng. 18 (2008) (9pp) doi: / /18/9/ A silicon-on-glass single-pole-doublethrow (SPDT) switching circuit integrated with a silicon-core metal-coated transmission line MTang 1,2,AQLiu 1 and J Oberhammer 3 1 School of Electrical and Electronic Engineering, Nanyang Technological University, ngapore Institute of Microelectronics, 11 Science Park Road, Science Park II, ngapore Microsystem Technology Lab, School of Electrical Engineering, KTH Royal Institute of Technology, SE Stockholm, Sweden eaqliu@ntu.edu.sg Received 15 May 2008, in final form 2 July 2008 Published 14 August 2008 Online at stacks.iop.org/jmm/18/ Abstract This paper presents a novel low-loss single-pole-double-throw (SPDT) switching circuit which integrates a silicon-core metal-coated coplanar waveguide (CPW) and two laterally moving switches in parallel. The circuit structure consists of single-crystal silicon as the core material and a thin layer of metal coated on the core surface to propagate the RF signal. The influences of the material property and the process variation on the RF performance of the silicon-core metal-coated CPW is analyzed in detail, including the silicon-core resistivity, the spreading metal on the substrate and the recess etching depth. Based on this analysis, the low-loss SPDT switching circuit is designed and fabricated using high-resistivity silicon (HR) as the core material and Pyrex 7740 glass as the substrate. The pull-in voltage of the laterally moving switch is V. The insertion loss of the laterally moving switch is less than 1 db up to 40 GHz. Both the return loss and the isolation are higher than 22 db up to 40 GHz. The SPDT switching circuit has an insertion loss of less than 1 db up to 22 GHz. The return loss is 17 db and the isolation is 25 db at 25 GHz. A silicon-on-glass (SOG)-based substrate-transfer micromachining process is developed for the SPDT switching circuit fabrication, which has the advantages of single mask, high design flexibility and low signal propagation losses. (Some figures in this article are in colour only in the electronic version) 1. Introduction With the advent of wireless and portable communications, the demand for low-cost, miniaturized RF and microwave devices and components is steadily increasing. RF MEMS switches exhibit a high potential in these areas since they can significantly reduce the size, weight, loss and power dissipation of RF components in the system [1, 2]. It is common to use metals and dielectric thin films as the moving structures (bridges or armatures) in RF MEMS switches. The fabrication processes are surface micromachining processes [2]. While demonstrating excellent RF performance, the mechanical properties of these switches (such as Young s modulus and residual stress of the thin-film structures) usually depend on the tuning of individual fabrication equipment, making the switches less reproducible. Additionally, the deformation of the structures due to fabrication-related stress gradients is difficult to control, which causes the disparity in the performance of the thin-film switches and the degradation of the fabrication yield [3 6]. ngle-crystal silicon (SCS) has been used as the moving structure in some MEMS switches [7 20]. nce SCS has nearly no biaxial stress and vertical stress gradient, and has superior thermal characteristics, the deformation of the SCS moving structures can be reduced and the reliability of the switch can be improved. Some groups also developed vertically moving SCS switches with robust and /08/ $ IOP Publishing Ltd Printed in the UK

3 Metal core Metal Substrate, ε r (a) G r S W G r Substrate, ε r G r S G r t w r Figure 1. Schematic cross-sectional view of (a) the conventional thin-film CPW and (b) the silicon-core metal-coated CPW. high-reliable performance [7 9]. However, the fabrication processes of these switches are relatively complicated. The transmission line, the passivation layer, the moving structures and the contacts are patterned and processed in different deposition and photolithographical process steps. x masks are needed in the fabrication processes. Others developed laterally moving SCS switches and transmission lines with a single-mask process [10 16]. A silicon-core metal-coated parallel-plate transmission line was first reported in [10], which was fabricated on a silicon wafer using the singlecrystal reactive etching and metallization (SCREAM) process. A step impedance filter and a continuous microactuated phase shifter were realized using this transmission line [11, 12]. The majority of the laterally moving SCS switches reported to date are not suitable for high-frequency applications [13 16]. Some thermally actuated switches can work up to 50 GHz [17, 18]. Compared to thermally actuated switches, electrostatically actuated switches are more favorable for RF systems due to their lower actuation power consumption and faster switching speed. An electrostatically actuated switch fabricated using a silicon-on-insulator (SOI) wafer with an insertion loss of 1 db and an isolation of 22 db up to 25 GHz and a SPDT switching circuit with an insertion loss of 1 db and an isolation of 20 db up to 6 GHz have also been demonstrated in our previous work [19, 20]. In this paper, the influences of the material property and process variation on the signal propagation of the siliconcore metal-coated CPW are investigated in detail. These include the effects of the silicon-core resistivity, the spreading metal on the substrate and the recess etching depth on the characterization impedance and the attenuation. Based on this study, a novel SPDT switching circuit integrating two laterally moving switches is designed and fabricated using high-resistivity silicon (HR) as the core material and Pyrex 7740 glass as the substrate for low insertion loss and high isolation up to 22 GHz. A single-mask substrate transfer process is developed to fabricate the silicon-core metalcoated CPW and the laterally moving switches. Finally, the experimental results of the silicon-core metal-coated CPW and the SPDT switching circuit are presented. (b) h r T H Table 1. Dielectric properties of the selected medium materials. Material ε r tan δ σ d (S m 1 ) Pyrex at 1 MHz HR LR Air The silicon-core metal-coated CPW This section studies the silicon-core metal-coated CPW in detail, which is designed for laterally moving switches and circuits. Figures 1(a) and (b) show a cross-sectional view of a conventional thin-film CPW and a silicon-core metal-coated CPW. Each conductor of the silicon-core metal-coated CPW consists of µm thick single-crystal silicon coated with a thin layer of metal on the top and on the sidewalls. The RF signal propagates along the metal. The recesses in the substrate under waveguides play three roles avoid metal connection and insulate conductors from each other, reduce the coupling effect of the spreading metal on recesses and allow the release of moving structures. Like the conventional thin-film CPW, the silicon-core metal-coated CPW has advantages of coplanar configuration and balanced wave propagation. The silicon-core metal-coated CPW is designed in two steps. First, the geometrical dimensions are adjusted for the required characteristic impedance, Z 0, based on the conventional equations [21]. To accommodate 150 µm pitch ground signal ground coplanar probes, the distance between the two ground lines, S +2W, is chosen to be 200 µm, where S is the width of the signal line and W is the space between the signal line and the ground line. The ground line width, G r, is in the range of µm. Then, the three-dimensional (3D) electromagnetic field simulator Ansoft s HFSS [22] is used to simulate this transmission line configuration. The values of other parameters are set in the simulation model based on the process restrictions, including the depth h r and the undercut width w r of the recess, the conductivity σ and the metal thicknesses t t on the top and t s on the sidewalls. Therefore, the S/W/G r values are adjusted further for the required characteristic impedance. Table 1 lists the material properties used in the simulation model. The silicon-core metal-coated CPW can be modeled as a lumped-element RLGC circuit, where R, L, G, and C are series resistance, series inductance, shunt conductance and shunt capacitance per unit length, respectively [21]. The characteristic impedance, Z 0, attenuation, α, and RLGC parameters can be extracted from the simulated or measured S-parameters [23]. Therefore, based on the extracted Z 0, α and RLGC parameters, we can easily find out the influence of any element change of the silicon-core metal-coated CPW. The influence of the core material on the characteristic impedance and the attenuation is shown in figure 2. The characteristic impedance, Z 0, is larger when HR is used as the core material, compared to the low-resistivity silicon (LR). At the same time, the attenuation decreases and the difference in the attenuation grows faster with the frequency. This is because when the core resistivity decreases, the unit 2

4 Characteristic impedance, Z 0 (Ω) HR-core LR-core Attenuation, α (db/mm) Characteristic impedance, Z 0 (Ω) h r = 12 µm, w r = 20 µm h r = 6 µm, w r = 10 µm h r = 2 µm, w r = 4 µm Attenuation, α (db/mm) Figure 2. mulation results of silicon-core metal-coated CPWs with different conductor core materials simulated with HFSS (ρ HR = 2000 cm, ρ LR = 1 cm, h r = 12 µmandw r = 20 µm, 1 µm thick Au in the glass recesses) Figure 4. mulation results of HR-core metal-coated CPWs with various undercut dimensions (ρ HR = 2000 cm). Characteristic impedance, Z 0 (Ω) With Au in glass recesses Without Au in glass recesses Attenuation, α (db/mm) Ground gnal Cantilever Ground beam Contact bump Anchor l 1 (a) l l 2 l 3 Figure 3. mulation results of a LR-core metal-coated CPW with/without gold on the recess surface between two conductors simulated with HFSS (h r = 6 µm, w r = 10 µm, ρ LR = 1 cm). y x w 1 Cantilever beam g 0 d 0 w 2 shunt capacitance, C, and shunt conductance, G, increase. Figure 3 shows that the metal on the recess between conductors significantly reduces the characteristic impedance and increases the attenuation of the silicon-core metal-coated CPW due to the increase of the unit conductance, G, and the capacitance, C. Figure 4 shows that when the recess is etched deeper, that is, h r /w r increases from 2/4 µm to12/20 µm, the characteristic impedance increases from 34 to 49.8, and the attenuation significantly decreases. This is because when the recesses are deeper, the distance between the spreading metal and conductors is larger. Therefore, the parasitic conductance, G, and capacitance, C, are smaller, and the dielectric loss is smaller as well. Therefore, etching recesses deeper or removing the metal on the glass recesses can reduce the coupling effect of the spreading metal and improve the RF performance of the silicon-core metal-coated CPW effectively. In all the simulation models, S/W/G r = 110/45/300 µm and T = 45 µm. The substrate is Pyrex V (b) Fixed electrode Contact bump Figure 5. Schematic drawing (not to scale) of (a) the SPST switch, and (b) top view of the switch geometry. The conductors are coated with 1 µm thick Au on the top and with 0.4 µm thick Au on the sidewalls. 3. The single-pole double-throw (SPDT) switching circuit The SPDT switching circuit consists of the CPW T-junction and two laterally moving single-pole single-throw (SPST) switches. Figure 5(a) shows the schematic of the SPST switch. The design details of the SPST switch have been presented in our previous work [19]. The laterally moving 3

5 Port 2 (Output1) Port 3 (Output2) G r S G r S Switch1 A 1 A 2 A 4 A 3 A 1 Switch2 A 4 A 2 A 3 G r S G r Port 1 (Input) (a) (b) G r Figure 6. Schematic drawing of a SPDT switching circuit (G r : ground; S: signal; A i A i : bond wire). Table 2. Design and fabrication dimensions of the SPST switch before metal coating. Nominal Measured dimension Parameter dimension (µm) after fabrication (µm) l l l w w g d T (c) (d ) (e) ( f ) switch consists of one single-side clamped cantilever beam and a fixed electrode. The narrow, flexible part of the cantilever beam is 2.5 µm wide and 260 µm long, as shown in figure 5(b). The wider part of the cantilever beam forms a stiffer, larger mass, which is 5 µm wide and 210 µm long. The fixed electrode is part of one ground line of the silicon-core metal-coated CPW, which here is in very close approximation to the cantilever beam. The detailed dimensions of the SPST switch are shown in table 2. In operation, the cantilever beam is electrostatically actuated by applying a bias voltage between the cantilever beam and the fixed electrode, so that the free end of the cantilever beam touches the contact bump at the output port to close the electrical path between the input port and the output port. The gap between the cantilever beam and the fixed electrode is 4 µm, a little larger than the gap between the free end of the cantilever beam and the contact bump, 3.5 µm, to prevent electrical short. Figure 6 shows a schematic drawing of the proposed SPDT switching circuit. A SPST switch is located on each of the output lines of a tee junction. The two laterally moving switches are parallel to each other. The silicon-core metalcoated CPW is utilized as the transmission line. The two cantilever beams share one common ground line between them, as well as the common fixed electrode. The signal can therefore be routed to different output ports with one switch at the open state and the other at the close state. Bond wires are applied to electrically connect the different ground conductors O 2 / N Cr/Au Figure 7. Fabrication process flow. to suppress the excitation of the parasitic, coupled slot-line mode in laterally asymmetrical geometries, especially in a high-frequency range [24]. 4. Fabrication process A substrate transfer process is developed for the fabrication of the SPDT switching circuit on a 500 µm thick 8 glass (Pyrex 7740) substrate [25]. The brief process flow is shown in figure 7. The fabrication process begins with the deposition and patterning of a 2 µm thick plasma-enhanced chemical vapour deposition (PECVD) silicon dioxide (O 2 ). Then, µm thick high-aspect-ratio silicon structures are etched in a silicon wafer via a deep reactive ion etch (DRIE) process using O 2 as the hard mask. After the removal of the PECVD O 2 using the reactive ion etching (RIE) process, a 2000 Å thick thermal O 2 is grown to cover every part of the silicon structures (figure 7(a)). After that, the silicon wafer faces down and is bonded to the glass wafer using an anodic bonding technique (figure 7(b)). Next, the silicon wafer is thinned from the backside in two steps. First, the wafer is thinned rapidly by grinding and polishing until the deepest trenches are exposed (figure 7(c)). Second, a 35% aqueous solution of potassium hydroxide (KOH) at 40 C is used to etch 4

6 Au 0.4 µm 1 µm 10.2 µm 5.7 µm Figure 8. SEM microphoto of the cross-sectional view of a silicon structure (distance to the opposing sidewall = 45 µm). the silicon until all silicon structures are exposed to the air (figure 7(d)). The thermal O 2 can protect the sidewalls of the exposed silicon structures from the erosion of the KOH solution. After the removal of the exposed thermal O 2 in the buffered oxide etchant (BOE), the wafer stack is dipped in the aqueous solution of hydrofluoric acid (HF) for 30 min to etch the glass and release the high-aspect-ratio suspended structures (figure 7(e)). The silicon structures serve as the hard mask for glass etching. Therefore, glass etching is a self-aligned process and needs no additional mask. At last, a thin layer of chromium/gold (Cr/Au) is directly coated on the silicon structures using E-beam evaporation (figure 7( f )). The scanning electron microscope (SEM) microphoto of the cross-sectional view of a silicon wire is shown in figure 8. It shows that the straight silicon structure is approximately 50 µm high. A recess is formed in the glass due to glass self-aligned etching. The vertical etching depth of the glass is 5.7 µm and the lateral etching width is 10.2 µm. 1.0 µm thick gold with 1000 Å chromium as the adhesion layer is coated on the top surface and the sidewalls of the silicon structure uniformly. Due to the step coverage of evaporation, the gold coated on the sidewalls (0.4 µm) is thinner than the gold coated on the top surface (1.0 µm). On the sidewalls, the metal is tightly coated and is uniformly covering the height of the entire structures. Figure 9 shows that the surface roughness of the sidewalls of the cantilever beam is only 75 Å, which is much smaller than the gold skin depth up to 100 GHz. Therefore, only a small per cent of the total current can see this roughness and the power loss due to this roughness is negligible [26]. 5. Experimental results and discussions The RF characteristics of the silicon-core metal-coated CPW, the laterally moving switch and the SPDT switching circuit have been measured using an HP 8510C network analyzer with tungsten-tip 150 µm pitch Cascade Microtech ground signal ground coplanar probes. The system is calibrated using a standard short-open-load-thru (SOLT) calibration technique with an impedance standard substrate (ISS). Figure 9. AFM micrograph showing the surface roughness of the sidewall of the cantilever beam after metal coating (roughness = 75 Å) The silicon-core metal-coated CPW Figure 10 compares the measurement results with the simulated and fitted results of a 1 mm long HR-core metalcoated CPW on glass. The S/W/G are 110/45/300 µm. The transmission line is 52 µm thick. The glass recess parameters, h r and w r, are about 6 µm and 10 µm, respectively. The measured RLGC parameters, the characteristic impedance, Z 0, and the attenuation, α, are extracted from the measured S- parameters. The fitted RLGC parameters are fitted from the extracted RLGC parameters. Then, the fitted characteristic impedance, Z 0, and the fitted attenuation, α, are calculated from the fitted RLGC parameters. The 3D simulation model was built based on the real device parameters using HFSS version 10. The skin depth-based mesh refinement with three layers of elements was set for all metal structures to include the metal thickness effect. The convergence resolution of maximum delta S was 1. Figure 10 shows that the simulated and fitted results are in good agreement with the measurement results. The characteristic impedance of the glasssubstrate, HR-core metal-coated CPW is about 47 when the frequency is above 10 GHz. The attenuation increases with frequency, which is 0.4 db mm 1 at 25 GHz. This is much lower compared to the SCS parallel-plate transmission line on the low-resistivity silicon [10], whose attenuation is about 1.1 db mm 1 at 25 GHz. The extracted unit resistance and conductance are shown in figure 10(b). At 20 GHz, the measured conductance, G, is S mm 1, resulting in a dielectric loss, α d, of 34 db mm 1. A measured resistance, R,of3.76 mm 1 contributes to a conductor loss, α c, of db mm 1. The conductor loss is nine times higher than the dielectric loss. Therefore, the large unit resistance, R, is the dominant factor of the attenuation of the silicon-core metal-coated CPW. The surface current is mainly concentrated at the sidewalls of the apertures, instead of the whole conductor surfaces. Therefore, the unit resistance, R, mainly depends on the thickness of the metal coating on the sidewalls. The metal coated on the sidewalls is thinner than the one on top of the conductors, which results 5

7 Characteristic impedance, Z 0 (Ω) Measured mulated Fitted Attenuation, α (db/mm) Characteristic impedance (Ω) LR-core, measured LR-core, fitted HR-core, measured HR-core, fitted Attenuation (db/mm) Measured Fitted (a) Figure 11. Measured attenuation of LR-core and HR-core metal-coated CPWs on a Pyrex 7740 substrate (S/W/G r = 110/45/300 µm, T 52 µm, h r 6 µmandw r 10 µm, 1 µm Au coating). Resistance, R (Ω/mm) Conductance, G (S/mm) (b) Figure 10. Comparison of the measured, simulated and fitted performance of a 1 mm long HR-core metal-coated CPW on a Pyrex 7740 substrate (T 52 µm, h r 6 µm, w r 10 µmand 1 µm thick Au coating). in larger unit resistance and higher conductor loss. The metal spreading on the recesses between conductors during E-beam evaporation causes larger shunt conductance, which results in larger dielectric loss. The influence of the resistivity of the silicon core on the attenuation is illustrated in figure 11. For the HR silicon core, the attenuation is lower compared to the LR silicon core in a high-frequency range. Based on the simulation and the experiment study, four basic guidelines for the low-loss silicon-core metal-coated CPW design are developed: (i) coating thick metal with good step coverage; (ii) removing the metal between waveguides or etching the glass recesses deeply; (iii) utilizing a low-loss substrate, such as glass; and (iv) utilizing HR as the core material. And also these guidelines are very useful for the low-loss SPDT switching circuit development The SPDT switching circuit The SEM microphoto of the fabricated SPDT switching circuit is shown in figure 12. The size of the SPDT switching circuit Figure 12. SEM microphoto of a SPDT switching circuit with bond wires. is 1.6 mm 1.3 mm in area. The conductors are 52 µm thick HR core coated with 1.0 µm thick gold. The substrate is 500 µm thick Pyrex The glass recesses are 5.7 µm deep. Four gold wires were bonded at the discontinuities of the ground plane to electrically balance the potential of the ground plane. Table 2 lists the designed and fabricated dimensions of the SPST switch before metal coating. Figure 13 compares the measured and calculated displacement results of the free end of the cantilever beam with the applied bias voltage. When the bias voltage increases to V, the cantilever beam moves 3.05 µm away to touch the contact bump. That is, the measured pull-in voltage of the laterally moving switch is V, which is in close agreement with the calculated value of 12.0 V. During RF characterization, the applied bias voltage is 30 V, larger than the pull-in voltage, so that the contact force can be larger than the burst-in force of the Au Au contact. The measured dc contact resistance at 30 V is 1 2. Figure 14 shows the SEM microphoto of the contact area of the switch, which reveals 6

8 Insertion loss Displacement (µm) Measurement Calculation Voltage (V) V Figure 13. Displacement of the free end of the lateral switch with the applied bias voltage. S-parameters (db) Return loss Isolation Measurement mulation Figure 15. Comparison of measured and simulated RF performance of a SPST switch. Table 3. Comparison of the SPST switch performance between the current work and our previous work [19]. Contact Point Attributes Reference [19] Current work Core LR HR Substrate HR Pyrex 7740 Recess h r = 2 µm h r = 5.7 µm w r = 4 µm w r = 10 µm Metal 1.5 µm Al 1kÅCr/1.0 µmau Frequency range 50 MHz 25 GHz 50 MHz 40 GHz Insertion loss at 25 GHz 1 db 0.7 db Return loss at 25 GHz 18 db 23 db Isolation at 25 GHz 22 db 27 db Figure 14. SEM microphoto of the zoomed view of the contact point on the cantilever beam after several tens of switching cycles. that the contact is a small point at the top of the cantilever beam sidewall, instead of being distributed along the whole depth. The contact point is approximately 200 nm 250 nm in area. The mechanical switching lifetime of this laterally moving switch exceeds 10 6 switching cycles. However, the switch intends to stick as being switched with the RF signal (hot switching). The hot switching lifetime is only several tens of switching cycles when the RF signal power is 0 dbm. This is because the stiffness of the cantilever beam, 1.1 N m 1, is relatively low, resulting in low restoring force at the open state. The reliability of the switch with low actuation voltage can be enhanced through a larger stiffness ( 10 N m 1 ) and a smaller initial gap distance in the switch design [2]. For example, when L 1 = 140 µm, L 2 = 250 µm, w 1 = 5 µm, w 2 = 5 µm, T = 50 µm and g 0 = 3 um, the calculated stiffness is 11.5 N m 1 and the restoring force at the open state is 34.7 µn. The pull-in voltage increases to 28.9 V for 0.4 µm Au coating on the sidewalls. To obtain a 100 µn contact force, the applied bias voltage should be larger than 35 V. The switching lifetime of this design can be improved significantly due to larger stiffness and restoring force. During RF characterization, the bias voltage of the switch is applied via the bias tee. However, due to the three-terminal configuration, this kind of switch requires biasing network, including blocking capacitors and choke inductors, to decouple the RF signal from the dc actuation signal in the real circuit. This can be achieved in exactly the same way as for PIN diode switches [27]. The RF response of a SPST switch is shown in figure 15. The simulated insertion loss is a little smaller than the measured results since the contact resistance cannot be involved in the simulation model of HFSS. Table 3 shows that compared to our previous work [19], the insertion loss is reduced from 1 db to 0.7 db at 25 GHz. The return loss is increased from 18 db to 23 db and the isolation is improved from 22 db to 27 db at 25 GHz. The working frequency is widened from 25 GHz to 40 GHz. Due to the new substratetransfer fabrication process, this switch uses high-resistivity silicon as the core material and glass with deep recess etching as the substrate, resulting in lower loss and wider bandwidth. The measured S-parameters of the SPDT switching circuit with 7

9 Acknowledgments The authors would like to thank all the staff in the Semiconductor Process Technology Lab of the Institute of Microelectronics and the Photonics Lab I of Nanyang Technology University for their assistance and help. References Figure 16. Comparison of measured and simulated RF performance of a SPDT switching circuit. bond wires are shown in figure 16. The bias voltage of 30 V is applied from the output port to close the corresponding switch. The insertion loss is less than 1 db up to 22 GHz. The return loss is higher than 17 db and isolation is higher than 25 db up to 25 GHz. The RF performance of this SPDT switching circuit is significantly improved compared to our previous work [20]. The bandwidth of the SPDT switching circuit is increased from 6 GHz to 20 GHz. 6. Conclusions In this paper, a SPDT switching circuit integrating a siliconcore metal-coated CPW and two laterally moving switches have been designed, fabricated and characterized. For the silicon-core metal-coated CPW, the influences of the silicon core resistivity, the spreading metal on substrate recesses and the recess etching depth on the characteristic impedance and the attenuation are analyzed in detail. The attenuation of the silicon-core metal-coated CPW is 0.4 db mm 1 up to 25 GHz. The laterally moving SPST switch on Pyrex 7740 glass has an insertion loss of less than 1 db up to 40 GHz. Both the return loss and the isolation are higher than 22 db up to 40 GHz. The pull-in voltage is V. The contact point is approximately 200 nm 250 nm in area. The contact resistance is less than 2. The SPDT switching circuit has an insertion loss of less than 1 db up to 22 GHz. The return loss and isolation are higher than 17 db and 25 db up to 25 GHz, respectively. Based on the simulation and the measurement results, four guidelines are developed in order to achieve low-loss silicon-core metalcoated circuits: (i) depositing metal with sufficient thickness and improving the step coverage of the metal deposition; (ii) removing the spreading metal between conductors or etching recesses deeply; (iii) utilizing a low-loss substrate, such as glass; and (iv) utilizing high-resistivity silicon as the core material. [1] Yao J J 2000 RF MEMS from a device perspective J. Micromech. Microeng. 10 R9 R38 [2] Rebeiz G B 2003 RF MEMS Theory, Design, and Technology (Hoboken, NJ: Wiley) [3] Guo F M, Zhu Z Q, Long Y F, Wang W M, Zhu S Z, Lai Z S, Li N, Yang G Q and Lu W 2003 Study on low voltage actuated MEMS rf capacitive switches Sensors Actuators A [4] Huang J-M, Liu A Q, Lu C and Ahn J 2003 Mechanical characterization of micromachined capacitive switches: design consideration and experimental verification Sensors Actuators A [5] Chen Z, Yu M B and Guo L H 2001 Design and fabrication of RF MEMS capacitive switch on silicon substrate with advanced IC interconnect technology 6th Int. Conf. on Solid-State and Integrated-Circuit Technology pp [6] Yu A B, Liu A Q, Zhang Q X, Alphones A, Zhu L and Shacklock A P 2005 Improvement of isolation for MEMS capacitive switch via membrane planarization Sensors Actuators A [7] Sakata M, Komura Y, Seki T, Kobayashi K, Sano K and Horiike S 1999 Micromachined relay which utilizes single crystal silicon electrostatic actuator Proc. IEEE MEMS 99 Conf. (Orlando, USA) pp 21 4 [8] Kim J, Park J, Baek C and Kim Y 2004 The OG-based single-crystalline silicon (SCS) RF MEMS switch with uniform characteristics J. Microelectromech. Syst [9] Lee S, Kim J, Kim Y and Kwon Y 2008 A single-pole nine-throw antenna switch using radio-frequency microelectromechanical systems technology for broadband multi-mode and multi-band front ends J. Micromech. Microeng [10] Ayon A A, Kolias N J and MacDonald N C 1995 Tunable, micromachined parallel-plate transmission lines Proc. IEEE MEMS 95 Conf. pp [11] Kudrle T D, Neves H P and MacDonald N C 1998 Microfabricated single crystal silicon transmission lines Proc. RAWCON 98 pp [12] Kudrle T D, Neves H P and MacDonald N C 1999 A micromachined millimeter wave phase shifter Proc. 12th Int. Conf. Solid-State Sensors, Actuators and Microsystems (Transducers 99) pp [13] Schile I and Hillerich B 1999 Comparison of lateral and vertical switches for applications as microrelays J. Micromech. Microeng [14] Li Z, Zhang D, Li T, Wang W and Wu G 2000 Bulk micromachined relay with lateral contact J. Micromech. Microeng [15] Borwick R L III, Stupar P A and DeNatale J 2003 A hybrid approach to low-voltage MEMS switches Proc. 12th Int. Conf. Solid-State Sensors, Actuators and Microsystems (Transducers 03) pp [16] Receveur R A M, Marxer C R, Woering R, Larik V C M H and Rooij N D 2005 Laterally moving bistable MEMS DC switch for biomedical applications J. Microelectromech. Syst

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