Implementation of phase disposition modulation method for the three-level diode-clamped matrix converter

Transcription

1 IET Power Electronics Research Article Implementation of phase disposition modulation method for the three-level diode-clamped matrix converter ISSN Received on 21st November 2014 Revised on 18th April 2015 Accepted on 4th May 2015 doi: /iet-pel Hanbing Dan, Tao Peng, Mei Su, Yao Sun, Guanguan Zhang, Wenjing Xiong School of Information Science and Engineering, Central South University No. 932, Lushan South Road, Changsha, Hunan , People s Republic of China pandtao@csu.edu.cn Abstract: To improve the input and output waveform quality in terms of total harmonic distortion (THD) for the three-level diode-clamped matrix converter topology, the phase disposition carrier-based modulation method is a good option. However, it is difficult to implement because of the loss of zero-current commutations. Aiming at addressing the problem above, a hybrid switching sequence for the phase disposition method is presented to realise the safe commutation, and a prediction-based method is used to alternate the switching sequences. The current direction information of the switches in cascaded rectifier for commutations is obtained by a current reconstruction method. As demonstrated by experimental results, the phase disposition method contributes to lower input and output waveforms THD values compared with the phase opposition disposition method. 1 Introduction Multilevel converters [1 3] can generate output voltages with low total harmonic distortion (THD) values and reduce voltage stress, which are suitable for high-power high-voltage applications, such as energy conversion, compressor, high-voltage direct-current transmission, railway traction and manufacturing [4 10]. Lots of multilevel matrix converter (MC) topologies [11 20] are recently proposed as new types of multilevel converters, which inherit the merits of both multilevel converters and the conventional MCs [21 24], such as four-quadrant operation, sinusoidal input and output current, lower common mode voltage and larger power density. Generally, the topologies of multilevel MC mainly include multimodular MCs [11 13], capacitor-clamped (flying capacitor) MCs [14, 15], diode-clamped (neutral-clamped) MCs [16 19] and direct three-level MC [20]. The multimodular MC inherits the topological structure of cascaded H-bridge converter. Although a high output voltage can be obtained by increasing the number of basic modules connected in series, bulky and expensive transformers are required accordingly. For the capacitor-clamped MC, to balance the capacitor voltage is a tough task, and a larger number of capacitors make it difficult to commercialise. The multilevel diode-clamped MC derives from indirect MC. The three-level indirect MC was briefly mentioned at the end of [16], which was composed of a bidirectional current source rectifiers (CSR) and a three-level diode-clamped inverter (TLDCI). Moreover, its pulse-width modulation (PWM) control was presented in [17]. However, the input current quality may degrade to some extent since the current through the neutral point is not taken into account. Meng et al. [18] proposed an indirect three-level sparse MC topology with reduced number of switches. Moreover, its input currents are improved by keeping the current through the neutral point being zero. Raju et al. [20] proposed a new direct three-level MC, which increased three additional bi-directional switches connecting output terminals to the input filter capacitor neutral. Compared with conventional MC, it had lower output waveforms THD values and switching stress. Although multilevel MC was realised based on the topologies presented in [16 18, 20], it is not suitable for high-voltage applications because of the limited voltage rating of power semiconductors. Thus, a multilevel diode-clamped MC topology was proposed in [19], which includes N 1 CSR modules connected in series and an N-level diode-clamped inverter. Owing to this structure, it is suitable for high-voltage applications. Usually carrier-based modulation strategies [25] are adopted in the multilevel converters because of its simplicity of implementation. Most multicarrier-based PWM schemes for diode-clamped inverters derive from the carrier disposition strategy [26]. The carrier-based modulation strategies for TLDCI mainly consist of phase disposition (PD) and phase opposition disposition (POD) methods [27]. For simplicity of commutations in three-level diode-clamped matrix converter (TLDCMC), the POD method was adopted in [19]. However, the output waveform quality is not very good. In theory, the PD method leads to better output waveform quality compared with POD [25, 27, 28]. However, the associated commutations become very complicated for TLDCMC with the PD method because it is difficult to determine the current directions accurately. In this paper, we propose a hybrid switching sequence which easily detects the DC-link current directions. Thus, the commutation problem is solved. To begin with, the multicarrier-based modulation method for the TLDCMC is first reviewed in Section 2. Then, a hybrid switching sequence is proposed for the PD method to guarantee safe commutations in Section 3. To realise the PD method, the overall modulation implementation is analysed in detail in Section 4, which includes the current construction, switching sequence selection, four-step current-based commutation for the cascaded rectifier [29, 30] and the commutation for the TLDCI. Finally, the experimental waveforms of both PD method and POD method are given in Section 5. 2 Review of the multicarrier-based modulation method for TLDCMC The TLDCMC topology proposed in [19] is shown in Fig. 1. It consists of two CSR modules and a TLDCI. In the cascaded-rectifier stage, the space vector pulse-width modulation (SVPWM) is used to synthesise the desired input current vector. In the TLDCI stage, the multicarrier modulation is adopted to produce the desired output voltages. The multicarrier-based modulation method for the TLDCMC is reviewed in this section. & The Institution of Engineering and Technology

2 Fig. 1 Topology of the TLDCMC 2.1 Cascaded-rectifier stage The cascaded rectifier consists of two identical CSR modules, which adopt the same SVPWM method. The DC-link voltage of the cascaded-rectifier stage is twice as large as that of a single CSR module. For SVPWM as shown in Fig. 2, there are six active current vectors I 1 I 6 and three zero current vectors I 0 for the cascade-rectifier stage. Each current vector corresponds to a switching state of the cascaded rectifier. For example, the current vector I 1 (ab) represents the connection of input phase a1 to DC-link terminal p and input phase b1 to neutral point o in rectifier 1, and it also represents the connection of input phase a2 to neutral point o and input phase b2 to point n in rectifier 2. According to the vector synthesis principle, the duty ratios of the adjacent active vectors can be expressed as follows d a = m I sin (p/6 [u sc (N cur 1)p/3]) d b = m I sin (p/6 + [u sc (N cur 1)p/3]) d 0 = 1 d a d b where d α, d β and d 0 are the duty ratios of the active and zero vectors, respectively. m I represents the modulation index of the two identical CSR modules, θ sc represents the angular position of the current vector and N cur (N cur =1,2,, 6) denotes the current vector sector. The cascaded rectifier is controlled to supply maximum average DC-link voltage so that the modulation on the inversion stage controls the overall voltage transfer ratio. Hence, the zero current vectors are eliminated and the rectifier modulation index is unity. The adjusted cascaded-rectifier stage duty ratios are determined by (1) the following equation d a = d a = sin (p/6 (u sc (N cur 1)p/3)) d a + d b cos [u sc (N cur 1)p/3] d b = d b = sin (p/6 + (u sc (N cur 1)p/3)) d a + d b cos [u sc (N cur 1)p/3] And the average DC-link voltage in each switching period is no longer constant. When input power factor is unity, it can be recalculated as follows u pn = 2d a V l la + 2d b V l lb 3 2Ns V = inrms N p cos [u sc (N cur 1)p/3] where V inrms is the root-mean-square (RMS) of the input phase voltage referred to the transformer primary side, N p /N s is the primary-to-secondary turn ratio of the transformer and u pn is the average DC-link voltage of the cascaded rectifier. Similar to the conventional indirect MC, the DC-link voltage is fluctuated with six times the input frequency. 2.2 TLDCI stage Assume that the expected output voltages are expressed as u A = 2UAoRMS cos (w A ) u B = 2UBoRMS cos (w B ) u C = 2UCoRMS cos (w C ) (2) (3) (4) where U iorms and f i i {A, B, C} are the RMS and phase angle of the desired output phase voltage, respectively. The modulating signal is given by u io = u i + u NO, i [ { A, B, C} (5) where u io and u NO are the modulating signal and the zero-sequence signal, respectively. To maximise the utilisation of DC-link voltage, the zero-sequence signal u NO can be selected as Fig. 2 Diagram of current space vector in cascaded rectifier u NO = min (u A, u B, u C ) + max (u A, u B, u C ) 2 (6) 2108 & The Institution of Engineering and Technology 2015

3 The modulating signals can be normalised as u io = 2 u io u pn, i [ { A, B, C} (7) where u io denotes the normalised value and 1 u io 1. 3 Proposed hybrid switching sequence In the cascaded-rectifier stage, the symmetrical and asymmetrical switching sequences are commonly used in the current SVPWM. However, the asymmetrical switching sequence is not suitable for PD method applied in TLDCI stage. Supposing all reference signals remain unchanged in each modulation period, and the input reference current vector is located in sector 1 as shown in Fig. 2, then the asymmetrical switching sequence is: I 1 (ab) I 2 (ac), which is defined as type-a sequence. The symmetrical switching sequence is: I 1 (ab) I 2 (ac) I 1 (ab), which is defined as type-b sequence. If the type-a sequence is applied, the corresponding schematic diagram of type-a sequence for TLDCMC is shown in Fig. 3. Fig. 3 includes two modulation periods. In the first period, the output reference voltages satisfy u AO. 0. u BO. u CO ; whereas in the next period, the output reference voltages satisfy u AO. u BO. 0. u CO. In Fig. 3, the switches commutation in a rectifier occurs four times. In addition, the four-step current-based commutation is adopted here because of non-zero DC-link current. At t = t 1 and t = t 2, according to the switching states, the direction information of i P, i N could be easily determined by reconstruction method; whereas at t = T s, it is difficult to determine the direction of i P, i N since a simultaneous commutation occurs in both the cascaded rectifier and the TLDCI. As well known, the bidirectional switches commutations in the cascaded rectifier may fail if the associated current directions cannot be determined correctly. To avoid the simultaneous commutation phenomenon mentioned above, the type-b sequence as shown in Fig. 4a can be considered. Similarly, there are four commutations during two sequential modulation periods. However, the simultaneous commutation will not take place in this case. Till now, we only consider the case where the input reference current vector lies in the same sector during two sequential modulation periods. In fact, there exist other special cases as shown in Fig. 4b, where the input reference current vector changes from sector 1 to sector 2. The simultaneous commutation will occur again at t = T s even when the type-b sequence is employed. In summary, compared with the type-a sequence in Fig. 3, the type-b sequence in Fig. 4 can greatly reduce the probability of simultaneous commutations. However, it cannot avoid simultaneous commutations completely in some special cases. To deal with the limitation of the type-b sequence in special case above, the hybrid switching sequence shown in Fig. 5 can be considered. Assume that the total number of sampling period in each input current sector is n. In Fig. 5, the type-b sequence is used in intervals [0, (n 1)T s ] and [nt s,(n+1)t s ], and the type-a sequence is inserted in interval [(n 1)T s, nt s ]. Obviously, the simultaneous commutation is avoided at t = nt s because of the type-a sequence inserted at the end of sector 1. Fig. 3 Schematic diagram of the type-a sequence in the case that N cur =1 in [0, 2T s ] Fig. 5 Schematic diagram of the hybrid switching sequence in the case that N cur is 1 in [(n 2) T s,nt s ], and 2 in [nt s, (n + 1)T s ] Fig. 4 Schematic diagram of the type-b sequence for the TLDCI in the case that an cur = 1 in [0, 2T s ] bn cur is 1 in [0, T s ], and 2 in [T s,2t s ] & The Institution of Engineering and Technology

4 Table 2 Switching functions of the output A-phase in TLDCI Switching combinations Switching functions Q 1 Q 2 Q 3 Q 4 f AP f AN Fig. 6 For safe commutation, type-b sequence is adopted when N cur keeps unchanged and type-a sequence is adopted when N cur change In addition, γ 1 =(((n 1)π)/3n), γ 2 =(π/3n) A-phase for example, the output voltage is equal to the voltage u P, u O and u N, on the conditions of sets {Q 1, Q 2 }, sets {Q 2, Q 3 }, sets {Q 3, Q 4 }, respectively. Moreover, the switching functions are defined as f Ar (r = P, N). The switching functions of the output A-phase in TLDCI are shown in Table 2, and other two output phases can be deduced in the same way. Table 1 Sector To conduct a safe commutation, all the simultaneous commutations should be avoided. According to the analysis above, the hybrid switching sequence is a proper way to guarantee safe commutations. To formulate the hybrid switching sequence, the overall diagram for the proposed switching sequence is shown in Fig. 6. The total number of sampling period in each input current sector is n. The type-a sequence is employed in shaded regions which are the transition regions from one sector to the next, and the type-b sequence is used in unshaded regions. The total switching sequence arrangements are given in Table 1. 4 Overall implementation process of the PD method for TLDCMC The overall implementation diagram of the TLDCMC is shown in Fig. 7. The SVPWM method is adopted in the cascaded rectifier and the PD method is employed in the TLDCI. In addition, safe commutations are implemented by the proposed switching sequence. More implementation details will be discussed in this part. For the convenience of description, switching functions for the TLDCI are discussed here. As shown in Fig. 1, voltage levels can be obtained by three different switch combinations. Taking output Fig. 7 Arrangement of input current vector for cascaded rectifier Arrangement of input current vector for cascaded rectifier 1-b I 1 (ab) I 2 (ac) I 1 (ab) 1-a I 1 (ab) I 2 (ac) 2-b I 2 (ac) I 3 (bc) I 2 (ac) 2-a I 2 (ac) I 3 (bc) 3-b I 3 (bc) I 4 (ba) I 3 (bc) 3-a I 3 (bc) I 4 (ba) 4-b I 4 (ba) I 5 (ca) I 4 (ba) 4-a I 4 (ba) I 5 (ca) 5-b I 5 (ca) I 6 (cb) I 5 (ca) 5-a I 5 (ca) I 6 (cb) 6-b I 6 (cb) I 1 (ab) I 6 (cb) 6-a I 6 (cb) I 1 (ab) Overall implementation diagram of the PD method for TLDCMC 4.1 Current reconstruction method for DC-link currents It is noted that the four-step current-based commutation is required for the cascaded rectifier. Thus, the direction of the instantaneous DC-link current must be known, and it must remain unchanged in the process of four-step current-based commutation. However, detecting the DC-link current by current sensors is not precise enough because of the high-frequency pulsation within the DC-link current. According to the analysis, it can be found that the DC-link currents depend on switch states and load currents, which can be reconstructed by { i P = f AP i A + f BP i B + f CP i C (8) i N = f AN i A + f BN i B + f CN i C where i i (i {A, B, C}) is the output phase current. 4.2 Switching sequence selection The switching sequence selection depends on the position information of the desired input current space vector. Moreover, the key is to find out the moment the desired input current space vector sector changes. A prediction-based method is proposed to find the moment above. The current angular position of the desired input current vector is set by θ sc (t)=θ(t)+f in, θ(t) is the input voltage A-phase angle obtained by phase locked loop (PLL), and f in is the desired input power factor angle. Thus, the current sector number N cur is determined by θ sc in the current sampling period, and the next sector number N next can be determined by predicting θ sc (t + T s ) in the next sampling period. It could be written as θ sc (t + T s )=θ sc (t)+ω in T s, where ω in is the frequency obtained by PLL. When N cur = N next, the type-b sequence is adopted; when N next = rem((n cur + 1)/6), the type-a sequence is adopted, and rem( ) is the remainder operator; otherwise, the system will be shut down. 4.3 Four-step current-based commutation for cascaded rectifier In the cascaded-rectifier stage, when N cur = N next = 1 in a modulation period, the arrangement of input current vector for cascaded rectifier is I 1 (ab) I 2 (ac) I 1 (ab). For rectifier 1 in this period, the switch S 1 is kept being ON, the switch S 5 and S 6 are successively turned ON and OFF in the specific order indicated by the switching sequence. Fig. 8a shows the simplified circuit at the moment that the switch commutates from S 5 to S 6 in rectifier 1. To avoid a line-to-line short circuit or a load open circuit, the four-step current-based commutation in Fig. 8b is adopted. The commutation relies on the current direction information of i P, and i P is obtained by (8). Assume that the current direction information of DC-link current is wrong because of the error in load current measurement. This may result in the overvoltage because of the absence of a path for 2110 & The Institution of Engineering and Technology 2015

5 Fig. 8 Schematic diagram of the four-step current-based commutation a Simplified circuit b Commutation process Fig. 10 Experimental setup for the TLDCMC Table 3 Component parameters of the experimental setup Parameters Value Fig. 9 Switching process of the output A-phase states input phase voltage (V inrms ) 220 V input voltage frequency( f in ) 50 Hz transformer turn ratio (N p /N s ) 220/60 switching frequency ( f s ) 5 khz input filter inductor (L s ) 0.6 mh input filter capacitor (C f1, C f2 ) 22 uf damping resistor (R s ) 9 Ω resistor of load (R) 11Ω inductor of load (L o ) 6mH hall current sensor LT308-S7 load current. Thus, the accurate current direction information is important for the commutation, which will guarantee the effectiveness of the PD method. The delay between each switching event is determined by the device characteristics. The commutation of the cascaded rectifier in Table 1 can also be completed in the same method. 4.4 Switches commutation for TLDCI A transient state should be inserted to avoid the overvoltage of the switching devices during the commutation in the TLDCI. Taking output A-phase for example, when 0 < t < t 1 as shown in Fig. 5, the switching state of output A-phase changes from 0110 to If switches Q 1 is turned on and switches Q 3 is turned off at the same time, Q 1, Q 2 and Q 3 may be on state at the same time because of the shutdown delay, then short circuit will occur in the rectifier 1. Therefore a transient switching state 0100 should be inserted, and the switching process of the output A-phase states is shown in Fig. 9. Other two phases can be deduced as above. 5 Experimental results The implementation process is verified on a low-voltage experimental prototype as shown in Fig. 10. The setup is fed by 220 V/50 Hz (RMS), and corresponding component parameters are listed in Table 3. A 10 kva three-phase three-winding transformer with the turn ratio of 220:60 is used in the experiment. The measured magnetic inductance of the transformer is H, and the leakage inductance referred to the primary side is mh. In the cascaded rectifier, the four quadrant power switches are realised by the insulated gate bipolar transistor (IGBT) module FF300R12KT3_E. In the TLDCI, one phase leg is realised by connecting the IGBT module F3300R12ME4_B23 and F3300R12ME4_B23 in series. Sensor circuits are equipped to provide the information of the input voltage and the output current. A floating-point digital signal processor (DSP) (TMS320F28335) is used to calculate the duty ratios of the switches in TLDCMC and judge the direction of the instantaneous DC-link current. In addition, a field programmable gate array (EP2C8J144C8N) is Table 4 THD values of the input and output experimental waveforms under PD method and POD method Cases Output line-to-line voltage THD, % Output current THD, % Input current THD, % Desired output voltage Modulation method U orms =45V,f o = 30 Hz POD PD U orms =45V,f o = 60 Hz POD PD U orms =93V,f o = 30 Hz POD PD U orms =93V,f o = 60 Hz POD PD & The Institution of Engineering and Technology

6 Fig. 11 Experimental waveforms of TLDCMC, CH1: the DC-link voltage U pn, CH2: the output line-to-line voltage u AB, CH3: the input current i a, CH4: the output current i A POD method au orms =45V,f o =30Hz bu orms =45V,f o =60Hz cu orms =93V,f o =30Hz du orms =93V,f o =60Hz PD method eu orms =45V,f o =30Hz fu orms =45V,f o =60Hz gu orms =93V,f o =30Hz hu orms =93V,f o =60Hz 2112 & The Institution of Engineering and Technology 2015

7 Fig. 12 Experimental waveforms of TLDCMC with the desired output voltage U orms =93V,f o =30Hz POD method a Voltage and current of the secondary transformer winding b Voltage and current of the primary transformer winding PD method c Voltage and current of the secondary transformer winding d Voltage and current of the primary transformer winding used for implementing the switching sequences and the commutation process in cascaded rectifier and TLDCI. Figs. 11a d show the experimental waveforms of different desired output voltage under the POD method. As seen, the output line-to-line voltage is characterised by three levels. The distorted input current is mainly caused by the distorted no-load current in the transformer, dead time, device drop, LC resonance of the input filter and so on. Figs. 11e h show the experimental waveforms under the PD method in the same conditions as Figs. 11a d. As seen, the output line-to-line voltage waveforms under the PD method are different from the waveforms under the POD method. The THD values of the input and output waveforms under PD method and POD method have been compared in Table 4. Under the same conditions, the THD values of the input and output waveforms under the PD method are lower compared with the POD method. Figs. 12a d show the voltage and current waveforms of the primary and secondary transformer windings under the PD method and POD method. The current on the secondary side of the transformer are distorted with high-frequency component, but the total input current on the primary side of the transformer is seen to be sinusoid with low distortions. Additionally, the voltage and current of the primary transformer winding are in the same phase, the unity power factor is obtained. 6 Conclusions To realise the safe commutations for the PD method, the four-step current-based commutation is adopted, and a hybrid switching sequence is proposed. The overall implementation process for the PD method has been described in detail. The experiment results have verified the feasibility of the proposed switching sequence. In addition, compared with the POD method, the PD method contributes to lower THD values in the input and output waveforms. 7 Acknowledgments This work was supported by the National High-tech R & D Program of China (863 Program) under Grant 2012AA051603, and the Fundamental Research Funds for the Central Universities of Central South University under Grant 2014zzts210 and 2015zzts References 1 Lai, J.S., Peng, F.Z.: Multilevel converters. a new breed of power converters, IEEE Trans. Ind. Appl., 1996, 32, (3), pp Tolbert, L.M., Peng, F.Z., Habetler, T.G.: Multilevel converters for large electric drive, IEEE Trans. Ind. Appl., 1999, 35, (1), pp Krishna, K.G., Shailendra, J.: Comprehensive review of a recently proposed multilevel inverter, IET Power Electron., 2014, 7, (3), pp Rodriguez, J., Lai, J.S., Peng, F.Z.: Multilevel inverters: a survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., 2002, 49, (4), pp Klug, R.D., Klaassen, N.: High power medium voltage drives innovations, portfolio, trends. Proc. of European Conf. on Power Electronics and Applications, Dresden, Germany, 2005, pp Rodriguez, J., Bernet, S., Wu, B., et al.: Multilevel voltage-source-converter topologies for industrial medium-voltage drives, IEEE Trans. Ind. Electron., 2007, 54, (6), pp Franquelo, L.G., Rodriguez, J., Leon, J.I., et al.: The age of multilevel converters arrives, IEEE Trans. Ind. Electron., 2008, 2, (2), pp Rodriguez, J., Franquelo, L.G., Kouro, S., et al.: Multilevel converters: an enabling technology for high-power applications, Proc. IEEE, 2009, 97, (11), pp Bose, K.: Power electronics and motor drives recent progress and perspective, IEEE Trans. Ind. Electron., 2009, 56, (2), pp Kouro, S., Malinowski, M., Gopakumar, K., et al.: Recent advances and industrial applications of multilevel converters, IEEE Trans. Ind. Electron., 2010, 57, (8), pp & The Institution of Engineering and Technology

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