A PWM Dual- Output DC/DC Boost Converter in a 0.13μm CMOS Technology for Cellular- Phone Backlight Application

Transcription

1 S.K. Hoon, N. Culp, J. Chen, F. Maloberti: "A PWM Dual-Output DC/DC Boost Converter in a 0.13μm CMOS Technology for Cellular-Phone Backlight Application"; Proc. of the 31st European Solid- State Circuits Conf., ESSCIRC 2005, Grenoble, September 2005, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 A PWM Dual-Output DC/DC Boost Converter in a 0.13µm CMOS Technology for Cellular- Phone Backlight Application Siew Kuok Hoon (1), Norm Culp (1), Jun Chen (2), Franco Maloberti (3) (1) Wireless Analog Technology Center, Texas Instruments, Dallas. (2) Advanced Analogic Tech, Dallas. (3) Department of Electronics, University of Pavia, Italy. siewkh@ti.com, xieyin668@yahoo.com, franco.maloberti@unipv.it Abstract: This integrated single inductor dual-output boost DC/DC converter provides two independently regulated outputs with maximum efficiency at 83%. The converter operates in PWM and discontinuous mode at 500kHz using a 6.8uH inductor. Each output is time-multiplexed and regulated via current mode control. A drain-extended 0.13um technology allows backlight application up to 11V operation. The chip occupies 1.56 mm Introduction Color screen displays and keypad lightings are widely used in wireless cell-phones [1,2]. White light emitting diodes (LEDs) power the color screen backlight. To ensure brightness uniformity over the screen, two or three white LEDs are connected in series. Brightness control is achieved by adjusting the LEDs current. Since the white LED forward-biased voltage is about 3.5V, three LEDs in series would require about 11V. An inductor-based boost DC/DC converter is typically used for converting the Li-Ion battery voltage (about 3.6V) to a higher voltage (up to 11V) to serve as power source for the LEDs. Charge pump is not a powerefficient solution for high power application and wide range of input and output voltages. Boost DC/DC converters are more convenient. However, driving multiple sets of white LEDs for color screen display, keypad and other functions would require multiple external inductors, which incur high cost and board area. Dual output DC/DC boost converters using only single inductor have been proposed [3,4,5,6] to serve as power source for both digital processors and audio circuits working at around 3V, which significantly reduced system cost. However, the converter in [3] operates at variable switching frequency and also suffers from cross regulation. The time-multiplexing control method in [4] which is adapted from [5], operates with each switching cycle in discontinuous mode, so as to prevent cross-regulation. However, it will lead to a very high peak inductor current. Both approaches are unsuitable for system-onchip (SOC) [7] due to the noise-coupling and reliability issue. The pseudo continuous conduction method in [6] ingeniously reduce the peak inductor current and crossregulation issues but at the expense of an extra power switch. In a wireless SoC chip, which consists of multimodules densely packed and integrated together, when it involves significant consumption of silicon area in a design, the trade-offs needs to be studied carefully. Thus, the key features of the dual output single inductor power converter for wireless application include high efficiency, small area, and minimum cross-regulation and fixed frequency PWM operation. Another important feature includes the ability to have independent control of output voltages and currents so as to control different light intensity and also to allow selectively enabling backlight sources. There are two methods reported in [5] that may be suitable for the backlight driver application. Essentially, both methods are based on the concept of delivering inductor energy in a time-multiplexed manner. Both approaches operate at the condition of boundary continuous and discontinuous mode. To prevent cross-regulation, the boundary needs to be constantly adjusted to accommodate any load/line changes, which may involve complex control scheme. However, there are no system or circuit implementation details reported in [5] and how the issue of crossregulation is dealt with. In the following section, the two methods will be discussed in detail. Based upon one of the switching scheme in [5], a multi-loop controller (based on current mode control) with complete circuit implementation will be proposed. The challenges also include how to implement a high-voltage driver in a thinoxide process (1.5V max rating) and how to modify the switching scheme in order to reduce the effect of crossregulation. 2. Switching Scheme Choices The two switching schemes for dual output converter design are described as follows: /05/$ IEEE 81 Paper 1.E.2

3 1.1 Method 1 The method enables the sharing of inductor driving the loads in a time multiplexing (1-2A, 1-2B) fashion, as shown in Fig. 1, Method 1. It operates at the boundary condition as shown in shaded region of phase 1 and 2B, with the end phase of 2B touching the start phase of 1. During phase 1, the inductor is charged, and during phase 2, all the inductor energy is delivered to load A. In the second half cycle, the sequence repeats again with load B. To avoid cross-regulation, the technique of having each switching cycle operates in discontinuous mode is proposed in [3], which is not to have the end phase 2A and 2B touching the start phase of Method 2 The inductor is charged in phase 1 with the amount of energy that is enough to bias loads A and B sequentially. Again, it is operating at boundary condition with the end of phase 2B touching the start phase of 1. To avoid cross-regulation, this paper proposed having each combined switching cycle (1-2A-2B) to be in discontinuous mode as shown in Fig.1, Method 2. It is noted that the solid lines give the current profile with power levels equal to Method 1. The dashed lines show that, for example, power to B can be set at the maximum of Method 1 but the power to A can be much greater than the maximum permitted by the Method 1. In comparison, Method 2 provides more room for handling power while using the same value of inductor. Moreover there is room for further increasing delivered power to both loads. Another benefit of Method 2 is that the power n-mos is only switched once instead of twice. The benefits of the Method 2 enable an efficiency ranging from 76% to 83% and delivering power up to 0.62 W. Thus, Method 2 is preferable. It is essential that in between each complete switching cycle of power n- MOS, the inductor current must goes to zero which is operation in discontinuous mode. This key point has not been stated in [5], which is critical in avoiding crossregulation. 3. Circuit Implementation Fig. 2 shows the block diagram of the control implementation. The main feedback control scheme is based on the peak-current mode control. Slopecompensation is added to prevent sub-harmonic oscillation. The currents in loads A and B are measured by R FA and R FB and generate the feedback signals V FA and V FB. These feedback voltages are subtracted from the settings and compared with a signal proportional to the current ramp charging the inductor. The comparators detect the crossing points and the logic selects the longest crossing to switch off the n-channel power MOS. Figure 2: Block diagram of the proposed system. The inputs of comparator Comp C are the A-setting and V FA. It determines the switching from load A to load B during the inductor discharge period. Thus, the inductor delivers energy to output A until V FA reaches the setting. The remaining fraction of energy is delivered to the output B. If load B needs more or less energy the error amplifier changes accordingly the duration of the charging phase of inductor accordingly. Thus, the output feedback voltages, inductor current ramp and the comparator Comp C form the control loop to adjust the longest duty cycle to provide for an adequate amount of energy in order to regulate the loads. At all times, the following relationship is maintained t 1 + t a + t b + t 3 = T; t 3 > 0 Eq. 1 Figure 1: Discontinuous mode control, Method 1 and 2. where T is the switching period of the power n-mos, t 1 is the charging time of the inductor, t a,t b are the time interval of inductor energy delivering to output A and B respectively and t 3 is the interval when inductor current goes to zero. To have a stable and minimum crossregulation system, (2) must be satisfied. During power-up, the converter charges up output A first and when it reaches steady-state condition, the charging operation will alternate between A and B outputs. The entire control circuit operates at low voltage. The power p-mos switches use drain-extension transistors and can sustain a drain-source voltage (V DS ) up to 18V [8]. In the on condition the driver of the power p-mos must be able to control the gate below the maximum permitted V GS. In the off state the source of the power p-mos is almost at the voltage of the other output. It is necessary to ensure a good isolation of the outputs. Otherwise energy leakage would result in cross- 82

4 regulation. The driver of Fig. 3 achieves the required features. The external Schottky diode prevents reverse currents either when the power n-mos is on or during the supplying of the other loads. The current source M 1 and resistance R 1 generate a proper voltage that clamps the on-control of the power p-mos. Transistor M 2 achieves a fast transition from the on to the off states by discharging the C GS of the power p-mos. Transistors with drain extension M P1, M P2 and M P3 protect the low voltage devices. Figure 5: Measured waveform with output A in steady state and output B powering up. Figure 3: Proposed high-voltage power p-mos driver 4. Results and Discussion Fig.4 shows the microphotograph of the chip with a die area of 1.56 mm 2. The technology used is 0.13um 1.5V CMOS with 18V Drain Extended process. The external inductor is 6.8uH and capacitor is 0.1uF and the switching frequency is 500kHz. The input battery voltage used during test is 3.6V. Fig.6 illustrates the line regulation performance with the battery supply (V BAT ) jump from 3.3V to 3.6V. The bottom 2 outputs exhibit little DC and transient changes due to the line changes, and vice versa from 3.6V to 3.3V change. In the SoC chip, rejection of supply noise is a key performance since there are many other modules, which can inject noises at the power supply line. VBAT Output A M PA (PMOS) Output B Controller M N (NMOS) Figure 6: Ouput and supply line waveforms subjected to line- regulation changes. Figure 4: Chip Microphotograph. M PB (PMOS) Fig.5 verifies the independency of the two outputs. Output A is in steady state while output B is powering up. The power-up transient of output B slightly affects output A but after 20us, both outputs settle to the correct settings. This verifies that the system is capable of handling the issue of cross-regulation. Fig.7 illustrates the power n-mos drain voltage (node X Fig. 2) and two steady-state output voltages A and B both at about 6V, supplying 28mA and 5mA respectively which give rise to a slight difference in output voltages. The staircase-shaped drain voltage waveform illustrates the 1-2A-2B control scheme with output A biased first and immediately followed by output B. In backlight application, the output ripple is not a main concern. This is why the design did not care much about the ripple. If needed, using a larger output capacitor can minimize the ripple. The subsequent ringing at node X is caused by the inductance and parasitic capacitance when the inductor current is zero. 83

5 5. Conclusion Integration of power management blocks with the DSP in today s cellular phone platform demands the power converters to be realized in deep sub-micron process (0.13um). The main design criteria of proposed dual output converter is to achieve high efficiency while using minimal die area. This work is targeted for the high voltage, widely used backlight application while still capable of integrated in a low-voltage process technology. References: Figure 7: Measured waveforms with voltage at node X, output A and B corresponding to different output current levels. Fig.8 illustrates the efficiency of the converter versus output voltage for different output current. The efficiency peaks at 83% when outputs are both at 4V. To achieve good efficiency, the value of R FA and R FB can be made small. Supply Voltage 3.6V Inductor capacitor die area n-mos switching freq Ouptut Voltage Output Current 6.8uH 0.1uF 1.56mm2 500kHz max 11V max 28mA (in both legs) Table 1: Performance of Boost DC/DC converter. [1] P.L. Miribel-Catala,.M. Puig-Vidal, J.S. Marti, P.Goyhenetche and X.-Q. Nguyen, An integrated digital PFM DC-DC boost converter for a power management application : a RGB backlight LED system driver, IECON 02, vol.1, pp.37-42, Nov [2] M. Paparo, Power management systems on silicon for portable equipment, 8 th IEEE Intl. Conf. Electronics, Circuits and Systems, Vol.1, pp.13-18, Sept [3] M.W.May et al., A synchronous dual-output switching dc-dc converter using multibit noiseshaped switch control, ISSCC Dig. Tech. Papers, pp , Feb [4] D. Ma, W.-H. Ki, C.-Y. Tsui and P.K.T. Mok, Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous mode, IEEE Journal of Solid-State Circuits, vol.38, pp , Jan [5] T. Li, Single inductor multiple output boost regulator, U.S.Patent , June [6] D. Ma, W.-H. Ki and C.-Y. Tsui, A pseudo- CCM/DCM SIMO switching converter with freewhelel switching, IEEE Journal of solid-state circuits, vol.38, pp , Jun [7] D. Evans, M. McConnell, P. Kawamura and L. Krug, SoC integration challenges for a power management/analog baseband IC for 3G wireless chipsets, 16 th International Symp. on Power Semiconductor Devices and ICs, pp , May [8] J.C. Mitros, C.-y. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Goodpaster, D. Mosher and T.R. Efland, High-voltage drain extended MOS transistors for 0.18um logic CMOS process, IEEE Trans. on Electron Devices, vol.48, pp , Aug 2. Figure 8: Measured efficiency with both output branches subjected to same number of LEDs and current. 84