ISSN Vol.08,Issue.10, August-2016, Pages:

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1 ISSN Vol.08,Issue.10, August-2016, Pages: Implementation of High Speed and Area Efficient Address Generator for WiMAX Deinterleaver B.ARAVIND KUMAR 1, Y. AVANIJA 2 1 PG Scholar, Dept of ECE, Ananthalakshmi Institute of Technology and Sciences, Anantapur, AP, India, aravindworldak@gmail.com. 2 Assistant Professor, Dept of ECE, Ananthalakshmi Institute of Technology and Sciences, Anantapur, AP, India. Abstract:WiMAX(Worldwide interoperability for Microwave Access) is a wireless technology used to provide wireless connection over 30 miles. WiMAX is based on RF technology called Orthogonal Frequency Division Multiplexing (OFDM), which is a very effective means of transferring data when carriers of width of 5MHz or greater can be used. WiMAX is a standard-based wireless technology that provides high throughput broadband connections over long distance. WiMAX can be used for a number of applications, including broadband connections, hotspots and high-speed connectivity for business customers. In order to increase the security strength in wireless internet, interleaving and deinterleaving is performed in transmitter and receiver respectively. The block deinterleaver is one of the deinterleaving methods which take less computation time, but the floor function present in the address generator increase the complexity of de inter leaver. The Address generator used here involves two complex mathematical steps which includes modulo and floor functions associated with it. Implementation of these complex functions is difficult, the available method of LUT based address generation uses more area and its implementation is complex. To overcome the above problem in order to generate relevant address we use complete de inter leaver address generator of three different modulation techniques like QPSK, 16 QAM, 64QAM along with their code rates. The designing process has been divided into four modules. The first three modules deal with the designs of QPSK, 16-QAMand 64-QAM address generators and the final module deals with the combination of these three modules using resources sharing it is a low complexity and efficient method because it eliminates the requirements of functions. The main aim of the work is to concentrate on performance improvement by reducing delay and efficient resource utilization by comparing with prevailing technique. Keywords: LUT, QPSK, QAM, QAM, WiMAX, OFDM. designed to provide 30 to 40 mega bits per second data rates. WiMAX is a standard-based on wireless technology that provides high throughput broadband connections over long distance. WiMAX can be used for a number of applications, including broadband connections, hotspots and high-speed connectivity for business customers. The channel inter leaver employed in the WiMAX transceiver plays a vital role in minimizing the effect of burst error. Memory utilization and frequent memory accesses time are a crucial part of inter leaver design. Basically, the interleaving technique is to reorder the encoded data such that the adjacent bits can now become nonadjacent which can help handling the burst error occurring in those channels with memory. Although the basic concept of interleaving is straight-forward, the way of data recorder can be quite complex. In addition, to reorder a sequence of data requires a large memory buffer and frequent memory access such that the deinterleaver may become a crucial part of the overall decoder circuit in both area and power. Therefore, how to design an efficient deinterleaving circuit is very important. The blocks of a WiMAX trans receiver are shown in Fig.1. The output of source is randomized before being encoded by two Forward Error Correction (FEC) coding techniques, namely, Reed Solomon (RS) and Convolutional Coding (CC). The channel inter leaver permutes the encoded bit stream to reduce the effect of burst error. When Convolutional Turbo Code (CTC) is used for FEC, being used as optional in WiMAX, hence the channel inter leaver is not required, CTC itself includes an inter leaver within it. Modulation and construction of the orthogonal multiplexing symbols are performed by the subsequent block, namely, Mapper. In the receiver end, the blocks are organized in the reverse order to obtain the restoration of the original bit sequence at the output. The randomizer eliminates a long sequence of zeros and ones so that synchronization is not lost. It works on bit by bit fashion. Encoding is used for forward error correction where additional redundancy bits are added to the output of the randomizer. I. INTRODUCTION Broadband Wireless Access (BWA) is continuously becoming a more challenging competitor to the conventional wired technologies. IEEE has developed standards for mobile BWA (IEEE e) [1], popularly referred to as mobile WiMAX (Worldwide Interoperability for Microwave Access) Inter leaver is used for protection against burst errors is a family of wireless communication standard initially which can make a sequence of consecutive bits erroneous, 2016 IJATIR. All rights reserved.

2 thus making it difficult for the error correcting codes to correct this long sequence of consecutive errors in the sequence bits. WiMAX uses Reed-Solomon Codes and its error correcting capacity is 8 bits. If there are more than 8 consecutive bits in error than RS code will not be able to correct them. It is the role of the inter leaver to break this sequence of consecutive erroneous bits and make it possible to correct errors by RS codes below 8 bits. The Mapper maps the incoming bits onto a constellation. B.ARAVIND KUMAR, Y. AVANIJA classical inter leaver designs. The implementation is based on analysis of the address generation patterns used for the WMAN standard, the performance of this implementation is measured in terms of gate count and maximum frequency of operation. B.K.Upadhyaya, I.S.Misra and S.K.Sanyal [5] proposed Address generator for Wi-max using FPGA based finite state machine, the presented circuit supports all the code rates and the modulations permitted under IEEE e standard, the novelty of their approach including higher operating frequency and better utilization of resources. The presented circuits up ports all the code rates and modulation schemes permitted under IEEE e standard. The simulation results endorse the correct operation of both address generator and inter leaver as a whole. The novelty of our approach includes higher operating frequency and better resource utilization in FPGA. Fig.1. Block Diagram of WiMAX Transceiver. II. LITERATURE SURVEY W.Konhauser [1] proposed the Broadband wireless access alternative to the cable modem and DSL technologies, the key to the success of BWA is to offer a solution at least as reliable and easy to deploy as the competitive copper technologies. This paper will present the background of technologies and standards that address broadband wireless access (BWA), followed by a primer on orthogonal frequency-division multiplexing (OFDM) and its basic advantages and trade-offs, he has proposed OFDMA solution as the suitable answer to the challenges of wired technologies. B.Li, Y.Qin,c.p low and C.L.Gwee [2] proposed the IEEE standard, commonly known as Wi-max is the latest technology that has promised to offer broadband wireless access over long distances they also specified issues associated with scheduling and quality and service. This paper provides an overview of Mobile WiMAX standards and highlights potential problems arising from applications. Their main focuses are on the PHY layer, MAC layer specifications of mobile WiMAX. They gave an overview of the MAC specification in the IEEE j andieee802.16m standards, specifically focusing on scheduling mechanisms and QOS provisioning. The new features in mobile WiMAX, including mobility support, handoff, and multicast services. They discussed technical challenges in mobile WiMAX deployment. Y.N.Chang and Y.C.Ding [3] proposed efficient design of dual mode inter leaver for IEEE802.16, according to the proposed pattern, the input data can be split and allocated into separate, the input data can be split and allocated into separate storage units they implemented block inter leaver using 0.18um cmos technology. A.A.Khater, M.M.Khairy and S.E Habib [4] proposed an architecture that is both area and delay efficient, they compared between FPGA implementations of IEEE e inter leaver architecture and R.Asghar and D.Liu [6] proposed 2D realization of Wimax Channel Inter leaver there works provides the mathematical transformation of the one dimensional Wimax inter leaver equations in the standard to two dimensional spaces. This 2D transformation leads to optimized hardware architecture for address generation of the WiMAX inter leaver. Due to presence of modulus and floor operators within the inter leaver functions use of standard algebraic rules does not work always. Thus the structural analysis along with progressive generation of the equivalent set of equations for 2D space is used to reach to the low cost solution. M.N.Khan and S.Ghauri [7] proposed Wi-max e physical layer model Mobile WiMAX is the most emerging trend in recent wireless communication technology. WiMAX is based on wireless metropolitan area networking (WMAN) standards developed by the IEEE group. Wi-MAX's main objectives are to cover remote areas where cable connection is not feasible or expensive and for better coverage especially for mobile networks where users are always moving than and WiMAX is supported by IEEE802.16e-2005 Standard in this paper they proposed WIMAX PHY layer model using Simulink of the different modulation scheme gives transmission power required for different modulation in the Wi-max system for BER of 10-5 the performance is taken in terms of BER versus SNR. B.K.Upadhyaya and S.K.Sanyal [8] proposed an improved LUT based reconfigurable multimode inter leaver. In this paper, a memory efficient Look-up Table (LUT) based address generator for the de-inter leaver used in OFDM-WiMAX trans receiver is proposed. The relationships between various address LUTs implementing different inter leaver/deinterleaver depths within a modulation scheme have been exploited to model the proposed address generator. The proposed design shows81.25% saving of memory blocks in comparison with conventional technique. Hardware structure of the address generator is developed and is converted into a VHDL model using Xilinx Integrated Software Environment (ISE).Simulation results obtained using

3 Implementation of High Speed and Area Efficient Address Generator for WiMAX Deinterleaver Model Sim XE-III verifies the functionality of the proposed design In this paper, a novel technique to model the LUT based deinterleaver address generator for WiMAX system is proposed. A special relationship between the address LUTs has been explored and utilized to propose memory efficient design. The design is transformed into a digital hardware and is implemented on two different reconfigurable platforms. III. IMPLEMENTING METHOD OF DEINTERLEAVER ADDRESS GENERATOR The implementing method is complete deinterleaver address generator which includes the modules of address generator of QPSK, 16QAM, 64QAM; here design is optimized in the sense that common logic circuits such as multiplier, adder, row counter, and column counter are shared while generating addresses for the three modulation type. random code rates and also eliminates the use of multiple multiplexer modules and as it is common to all the three modules, we can use only one divider and subtractor module instead of three, thereby further reducing the hardware. The block diagram representation has been shown in Figs 2, 3, 4, for QPSK, 16-QAM and 64-QAM and the final deinterleaver block is shown in Fig.5. Here the address will be in the range of 0 to 95 in the QPSK modulation with the interleaving depth of 96 bits, the interleaving depth can also be varied according to the code rate [8]. TABLE I: 16-QAM Addresses (First 5 Rows) A. Complete Deinterleaver Address Generator An alternate algorithm to generate the deinterleaver addresses by eliminating the floor function has been obtained. The addresses generated for different code rates and modulations are shown in Tables 1, 2, 3. These are the addresses generated by using the permutation formulae given by IEEE standard for WiMAX deinterleaver.here the value of d has been chosen as 16,though other values are also possible (e.g.12). This is done keeping in the final synthesis problems i.e. Xilinx s does not allow division by a number other than the power of two. The algorithms used to generate the above addresses, thus by passing the floor function of the permutation formulae defined by IEEE Here j (0 to d-1) gives us the row number and i (0 to d-1) gives the column number represents the deinterleaver addresses. We have modified the implemented circuitry for the above algorithm keeping in view the optimality of the final design in terms of generalization of the address generator to accept random code rates and the final hardware efficiency. The designing process has been divided into four modules. The first three modules deal with the designs of QPSK, 16- QAM and 64-QAM address generators and the final module deals with the combination of these three modules using resources sharing A divider and a subtractor (minus one) circuit has been used as a common input module for all the three types of modulations and resource sharing has been done in terms of the blocks common to all the three modulation schemes. TABLE I: QPSK address (First 5 Rows) Here the address will be in the range of 0 to 191 in the 16 QAM modulations with the interleaving depth of 192 bits, the interleaving depth can also be varied according to the code rate. TABLE III: 64-QAM Addresses (First 5 Rows) Here the address will be in the range of 0 to 595 in the 64-QAM modulations with the interleaving depth of 596 bits, the interleaving depth can also be varied according to the code rate. Architecture of the deinterleaver address generator for QPSK: Algorithm for QPSK: Initialize N cbps and d The divider and a subtractor (minus one) combination at the input of the modulation blocks makes it possible to accept for j=0 to d-1,j++ for i=0 to (N cbps /d)-1, i++ K n =d*i+j end for end for The above algorithm shows how the address is obtained for the QPSK modulation scheme. After the initialization step, for loop is used as same as how we use in C

4 programming and later the value of j and i is incremented as shown and then it is multiplied with d (the number of columns used). And that result is added with j value. The similar steps of algorithm are used for the other two modulation type and hence as a result, their address will be obtained. B.ARAVIND KUMAR, Y. AVANIJA later the value of j and i is incremented as shown and then it is multiplied with d (the number of columns used). And that result is added with j value. when j mod 2 is equal to zero then deinterleaver address will be directly written as d multiplied with i and added with j, if i mod 2 is equal to zero then the deinterleaver address is written as d multiplied with i plus incremented by 1with j, if the two conditions fails then address is written as d multiplied with i minus decremented by 1 with j. Thus the deinterleaver address generation is obtained by using 16 QAM. Fig.2. Hardware structure of address generator for QPSK. The address generator of the WiMAX deinterleaver with QPSK is as shown in Fig.2. The QPSK hardware has a row counter RWC0 to generate row numbers between 0 and d 1 column counter CLC0 with multiplexer M0 and comparator C0 generate the variable column numbers to implement permissible Ncbps. A multiplier M0 and an adder A0 perform the desired operations to implement deinterleaver address for QPSK. Architecture of the deinterleaver address generator for 16QAM: Algorithm for 16QAM Initialize N cbps and d for j=0 to d-1,j++ for i=0 to (N cbps /d)-1,i++ Fig.3. Hardware structure of address generator for 16 QAM. The address generator of the WiMAX deinterleaver with 16-QAM hardware is as shown in Fig.3. The 16 QAM hardware has a row counter RWC0 to generate row numbers between 0 and d 1 A column counter CLC0 with multiplexer M0 and comparator C0 generate the variable column numbers to implement permissible Ncbps. A multiplier M1, M2, M3 and an adder A1, A2, A3 perform the desired operations to implement deinterleaver address for 16QAM. Architecture of the deinterleaver address generator for 64QAM: if (j mod 2=0) Algorithm for 64QAM K n =d*i+j Initialize N cbps and d for j=0 to d-1,j++ if (i mod 2=0) for i=0 to (N Cbps /d)-1,i++ K n =d*(i+1) +j if (j mod 3=0) K n =d*i+j K n =d*(i-1) +j if (j mod 3=1) end if if (i mod 3=2) end if. end for. end for. K n =d*(i-2) + j The above algorithm shows how the address is obtained for the 16QAM modulation scheme. After the initialization step, for loop is used as same as how we use in C programming and K n =d*(i+1) + j

5 end if Implementation of High Speed and Area Efficient Address Generator for WiMAX Deinterleaver Architecture of the Complete Deinterleaver Address Generator: if (i mod 3 = 0) K n =d*(i+2) + j K n =d*(i-1) + j end if end if end for end for The above algorithm shows how the address is obtained for the 64 QAM modulation scheme. After the initialization step, for loop is used as same as how we use in C programming and later the value of j and i is incremented as shown and then it is multiplied with d (the number of columns used). And that result is added with j value. when j mod 3 is equal to zero then deinterleaver address will be directly written as d multiplied with i and added with j, if i mod 3 is equal to 2, j mod 3 is equal to 1 then the deinterleaver address is written as d multiplied with i minus incremented by 2 with j, if the two conditions fails then address is written as d multiplied with i minus decremented by 1 with j. Thus the deinterleaver address generation is obtained by using 64 QAM. Fig.5. Top-level view of complete deinterleaver address generator. The top-level structure of the deinterleaver address generator is shown in Fig.5. Logic circuits of Fig.2, 3, 4 are presented here as QPSK block, 16-QAM block, and 64- QAM block, respectively. Our design is optimized in the sense that common logic circuits such as multiplier, adder, row counter, and column counter are shared while generating addresses for any modulation type. In addition, the design also shares the incremented and the decremented required in 16-QAM and 64-QAM blocks. IV. RESULTS This chapter discusses about Simulation results, showing the addresses of the first row (j = 0, 1) for QPSK, Simulation result showing the addresses of the first row (j =0,1) for 16QAM, Simulation result showing the addresses of the first row (j = 0) for 64QAM and Comparison between the proposed and LUT-based technique is explained along with its Synthesis report. Fig.4. Hardware structure of address generator for 64 QAM The address generator of the WiMAX deinterleaver with 64-QAM hardware is as shown in Fig.4.. The 64QAM hardware has a row counter RWC2 to generate row numbers between 0 and d 1 A column counter CLC2 with multiplexer M0 and comparator C0 generate the variable column numbers to implement permissible Ncbps. A mux M4, M5, M6 and an adder A4, A5, A6, A7 perform the desired operations to implement deinterleaver address for 64QAM. A. Simulation Results The proposed hardware of the address generator is converted into a VHDL program using the Xilinx ISE. Simulation results are obtained for all permissible modulation types and code rates using Model Sim XE-III and a part of the same for Ncbps =96-bits, 1/2 code rate for QPSK, has been presented in Fig.6, Ncbps =192-bits, 1/2 code rate for 16QAM, has been presented in Fig.7 Ncbps =576-bits, 1/2 code rate for 64QAM, has been presented in Fig.8. All the possible combinations can be obtained from the complete deinterleaver circuit and the Simulation results showing the address of the last part of first row (j=1) for N cbps =96bits, ½ code rate, similarly we can obtain for remaining combinations. QPSK Simulation Output:

6 B.ARAVIND KUMAR, Y. AVANIJA 64-QAM Simulation Output: Fig.6. Simulation result showing the addresses of the first row (j = 0, 1) for QPSK. When clk is assigned as 1, reset as 0 and mod type as 00 is given as input we get the required addresses, here we select code rate as 000 so it generates 5 addresses in each row and the entire addresses ranges from 0 to 95 and at each time the row counter and column counter gets incremented to generate the addresses. The indicator line in the simulation results shows the value of addresses as in row 0 and the values of addresses as in row QAM Simulation Output: Fig.8. Simulation result showing the addresses of the first row (j = 0) for 64QAM. When clk is assigned as 1, reset as 0 and mod type as 10 is given as input we get the required addresses, here we select code rate as 000 so it generates 16 addresses in each row and the entire addresses ranges from 0 to 287 and at each time the row counter and column counter gets incremented to generate the addresses the simulation results show the addresses of in the first row, for the generation of address for deinterleaver one can use interleaving depth based on the code rate by using 64 QAM one can transmit more bits per symbol. If the mux signal is selected as 001 we get different inter leaver depth of 384 bits of which addresses ranges from 0 to 383 bits thus deinterleaving addresses are generated. Complete Deinterleaver Address Generator: Fig.7. Simulation result showing the addresses of the first row (j = 0, 1) for 16QAM. When clk is assigned as 1, reset as 0 and mod type as 01 is given as input we get the required addresses, here we select mux signal that is the code rate as 000 so it generates 11 addresses in each row and the entire addresses ranges from 0 to 191 and at each time the row counter and column counter gets incremented to generate the addresses. The indicator line in the simulation results shows the value of addresses as in row 1.for the generation of address for deinterleaver one can use interleaving depth based on the code rate by using 16 QAM one can transmit more bits per symbol. If the mux signal is selected as 001 we get different inter leaver depth of 288 bits of which addresses ranges from 0 to 287 bits. Fig.9. Complete Deinterleaver address generator. Simulation result showing the complete addresses of the first row (j = 0) and the first portion of second row (j = 1) for Ncbps = 96-bits, 1/2 code rate and QPSK as shown in Fig.9. When we give the inputs as clk with time period, reset=0 and mod signal as 00, it display the addresses of QPSK modulation the address will be When we give the inputs as clk with time period, reset=0 and mod signal as 01, it display the

7 Implementation of High Speed and Area Efficient Address Generator for WiMAX Deinterleaver addresses of 16QAM modulation the address will be When we give the inputs as clk with time period, reset=0 and mod signal as 10 with code rate as 000, it displays the addresses of 64QAM the address will be B. Synthesis Report Synthesis Report as shown in Figs.10 and 11. The address generation circuitry of the WiMAX channel deinterleaver supporting QPSK and 16-QAM 16 QAM modulation patterns and all possible code rates as per IEEE e, When compared with the existing method LUT based technique the implementing method improves the FPGA parameters such as slices from 10% to 2% and flipflops from 2% to 1%, luts from 9% to 2% In addition to FPGA parameters delay has been improved from ns to 3.26 ns and thereby improving the performance of overall WiMAX system. D. Summary In this chapter, the complete deinterleaver Address Generator method is explained with blocks of QPSK, 16 QAM, and 64 QAM in detail. And then, the advantages over the existing LUT based method are discussed. The Resources utilization and the time delay of existing and implementing methods are calculated and the values are also presented, along with the synthesis report. Fig.10. Synthesis report of LUT based technique. Fig.11. Synthesis report of proposed technique. C. Comparison of Results TABLE IV: Comparison between the Proposed And LUT- Based Technique V. CONCLUSIONS AND FUTURE WORK This paper proposes a novel algorithm including proof for address generation circuitry of the WiMAX channel deinterleaver supporting QPSK and 16-QAM, 64QAM modulation patterns and all possible code rates as per IEEE e. The mobile WiMAX is going to be a great assurance for the upcoming wireless broadband systems in terms of performance, and it will replace the existing last mile or wired networks. When compared with the existing method LUT based technique the implementing method improves the FPGA parameters such as slices from 10% to 2% and flip-flops from 2% to 1%, luts from 9% to 2% In addition to FPGA parameters delay has been improved from ns to 3.26 ns and thereby improving the performance of overall WiMAX system. Future Work: In future this algorithm can be expanded to WIFI system by considering the protocols of both Wi-max and Wi-fi system and reduces the problem by shuffling source symbols across several code words there by creating a more uniform distribution of errors. VI. REFERENCES [1] W.Konhauser, Broadband wireless access solutions, Progressive challenges and potential value of next generation Wireless Communication, vol. 37, pp , May [2] B.Li,Y.Qin, C.P. Low and C.L.GWEE A survey on mobile WIMAX IEEE commun.mag.,vol.45no.12 pp Dec [3] Y. N. Chang and Y. C. Ding, A low-cost dual mode de-inters leaver design, in Proc Int. Conf. Consum. Electron. 2007, pp [4] A. A. Khater, M. M. Khairy, and S. E.-D. Habib, Efficient FPGA implementation for the IEEE e inters leaver, in Proc. Int. Conf. Micro electron, Marrakech, Morocco, 2009, pp [5] B. K. Upadhyaya, I. S. Misra, and S. K. Sanyal, Novel design of address generator for WiMAX multimode inter

8 B.ARAVIND KUMAR, Y. AVANIJA leaver using FPGA based finite state machine, in Proc. 13th Int. Conf. Comput. Inf. Technol., Dhaka, Bangladesh, 2010, pp [6] R. Asghar and D. Liu, 2D realization of WiMAX channel inters leaver for efficient hardware implementation, in Proc. World Acad. Sci. Eng.Technol., Hong Kong, 2009, vol. 51, pp [7] M. N. Khan and S. Ghauri, The WiMAX e physical layer model in Proc.IET Int. Wireless Mobile multimedia, pp [8] B. K. Upadhyaya and S. K. Sanyal, An improved LUT based reconfigurable multimode inter leaver for WLAN application, Int. J. Recent Trends Eng. Tech., ACEEE, vol. 6, no. 2, pp , [9] Local and Metropolitans Networks- Part 16: Air Interface for Fixed Broadband Wireless Access Systems, IEEE Std [10] Sanjose, XILINX Spartan-3 FPGA Family: Complete Data Sheet.USA [11] IEEE Standard for Local and Metropolitan Area Networks, Air Interface for Fixed Broadband Wireless Access Systems, IEEE ,2005. [12] J.G. Andrews, A. Ghosh, and R.Muhamed, Fundamental of WiMAX Broadband Wireless Networking. Author s Profile: Arvind Kumar, Pursuing His Master of Technology In VLSI Stream In Department of Electronics and Communication Engineering From Ananthalakshmi Institute of Technology And Sciences, Near S.K.University, Itukalapalli, Anantapur, Andhra Pradesh aravindworldak@gmail.com. Y.Avanija, Presently Working as Assistant Professor in Department for Electronics and Communication Engineering in Ananthalakshmi Institute of Technology and Sciences, Near S.K.University, Itukalapalli, Anantapur, Andhra Pradesh