ETM35E-10. Application Manual. Real Time Clock Module RX-8035SA/LC. Preliminary

Transcription

1 Application Manual Real Time Clock Module RX-835SA/LC Preliminary

2 NOTICE This material is subject to change without notice. Any part of this material may not be reproduced or duplicated in any form or any means without the written permission of Seiko Epson. The information about applied circuitry, software, usage, etc. written in this material is intended for reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any patent or copyright of a third party. This material does not authorize the licensing for any patent or intellectual copyrights. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes. You are also requested that you would not make the products available to any third party who may use the products for such prohied purposes. These products are intended for general use in electronic equipment. When using them in specific applications that require extremely high reliability, such as the applications stated below, you must obtain permission from Seiko Epson in advance. / Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and related (automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life / Submarine transmitters / Power stations and related / Fire work equipment and security equipment / traffic control equipment / and others requiring equivalent reliability. All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective.

3 RX-835SA/LC Contents. Overview..... Features Block Diagram Pin Descriptions Pin Layout Pin Functions Absolute Maximum Ratings Recommended Operating Conditions Frequency Characteristics Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics() AC Electrical Characteristics(2) Usege Overview of Functions Automatic battery switch-over circuit Register table Time stamp functions EDFG Time stamp registers. (BANK=,address -6h) EDCH,EDCH2 Indication of event input terminal EDFG of event detection function Event detection timing chart Clock Precision Adjustment Function Periodic Interrupt Function Alarm Interrupt Function The various detection Functions Overview of I2C-BUS External Connection Example External Dimensions / Marking Layout External Dimensions Marking Layout Reference Data Application notes... 39

4 I 2 C-Bus Interface Real-time Clock Module RX-835SA/LC. Overview The RX-835 is an I 2 C bus interface Real-time clock module which includes a kHz quartz oscillator that has been adjusted for high precision 5 ppm at +25C. This module provides time-stamp function and automatic battery switch-over circuit with low currents current consumption. And provides six types of interrupts, dual alarm function, oscillation stop detection, and power supply voltage monitoring. Since the internal oscillation circuit is driven by regulated voltage, kHz precision is stable and free of voltage fluctuation effects. The RX-835 is most suitable for power reduction, resource expansion of CPU, elimination of parts, improvement of tamper performance of a system in all electrical equipment... Features Built-in kHz crystal unit : Frequency adjusted for high accuracy ( 5 6 at 25C ). Available automatic battery backup switch-over function. When internal power supply was switched from VDD to battery, I 2 C-interface is inhied, and Time data are protected automatically. Available time-stamp function and interrupt out to CPU by trigger input from two event input ports. Time-stamp function is available in supply from VDD or VBAT. Includes time (H/M/S) and calendar (YR/MO/WEEK/DATE/DAY) counter functions (BCD code) Selectable 2-hour mode or 24-hour clock mode. Auto calculation of leap years until 299. ( 2 is not leap year. ) Dual alarm functions (Alarm_Wk: Day of week, Hour, Min. Alarm_Mo: Month, Day, Hour, Min) Oscillation stop detection function (used to determine reliability of internal data) Battery voltage monitoring function. Periodic interrupt function (Rate : Monthly, Hourly, every minute, every second,.5sec, OFF.) Built-in clock precision control logic kHz output. C-MOS Supports I 2 C-Bus's high speed mode (4 khz) Wide clock voltage range:. V to 5.5 V Low current consumption: 35nA 3. V (Typ.) 835SA 2. Block Diagram C VBAT SW2 VOUT SW VDD MAIN R BATT ERY VOLTAGE MONITOR VOLTAGE DETECTOR / RES C3 Primary Battery CRYSTAL & OSCLLATOR REAL TIME CLOCK, ALARM, TIMER, & TIME-STAMP REGISTERS LEVEL SHIFTER SCL SDA CLKOUT / INTRA / INTRB CPU EVIN EVIN2 DEBOUNCE & EDGE DETECT GND Page -

5 3. Pin Descriptions 3.. Pin Layout RX835SA. N.C. 4. EVIN2 2. SCL 3. INTRB 3. CLKOUT 2. SDA 4. VBAT. GND 5. N.C.. INTRA 6. VDD 9. RES 7. VOUT 8. EVIN SOP - 4 pin RX835LC. VOUT 2. EVIN 2. VDD. RES 3. N.C.. INTRA 4. VBAT 9. GND 5. CLKOUT 8. SDA 6. SCL 7. INTRB VSOJ2pin 3.2. Pin Functions Signal I / O name EVIN EVIN2 RES SCL I I O I Function Event input terminal for timestamp request. Built in de-bounce circuit. There is no built in resistor. A High level signal is a detection event. Event input terminal 2 for timestamp request. Built in de-bounce circuit and pull-down resistor. A High level signal is a detection event. While monitoring VDD input voltage, if the voltage is equal or lower than VD2B, this output level is L. When RES becomes L, SW is open, and SW2 turns on. As a result, power is supplied from VBAT pin. When VDD is equal to VB2D or more, SW is closed, and SW2 is opened. After tdelay passed, RES changes to Hi-Z status. It means system supply is stable. (SW and SW2: Please see Block diagram.) Serial-clock input for I 2 C communications. Up to 5.5 V can be used for this input, regardless of the power supply voltage. When VDD is lower than VD2B, I 2 C interface is inactive. SDA I/O Serial data inputs and outputs (N-ch open drain) for I 2 C communications. Be sure to connect a suitable pull-up resistor relative to the signal line capacitance. CLKOUT INTRA INTRB O O O kHz CMOS output between GND to VDD. It is always active. Outputs Alarm_Mo and event detection interrupts. N-ch open drain type. Outputs Alarm_Wk and periodic interrupts. N-ch open drain type. VDD - VBAT - VOUT O Input for main positive power supply. Be sure to connect a bypass capacitor rated at least. μf between VDD and GND. Connect a battery or capacitor for backup power supply. Normally, power is supplied from VDD to the IC. If VDD level is equal or less than VD2B, power is supplied from this pin. Output of internal power source for outside devices. And the secondary battery can be connected. Be sure to connect a bypass capacitor rated at least. μf between VOUT and GND. GND - For ground. N.C. - Do not connect. Keep open. Note: Be sure to connect a bypass capacitor rated at least. μf between VDD, VOUT and GND. Page - 2

6 4. Absolute Maximum Ratings GND = V Item Symbol Condition Rating Unit VDD VDD Supply voltage.3 to +6.5 V VBAT VBAT Input voltage VI SCL, SDA, EVIN,EVIN2 GND.3 to +6.5 V Output voltage VO SDA, INTRA, INTRB GND.3 to +6.5 V VO2 CLKOUT, VOUT GND.3 to VDD+.3 V Output current IOUT VOUT 2 ma Operating Temperature TOPR -4 to +85 C Storage temperature TSTG 55 to +25 C 5. Recommended Operating Conditions GND = V Item Symbol Condition Min. Typ. Max. Unit Operating supply voltage VACCESS VDD VD2B 5.5 V Clock supply voltage VCLK VBAT. 5.5 V Pull-up Voltage VPUP SCL, SDA, INTRA, INTRB 5.5 V 6. Frequency Characteristics Item Symbol Condition Rating Unit GND = V Frequency tolerance Frequency/voltage characteristics Frequency/temperature characteristics Detection voltage of oscillation stop. Oscillation start time Aging f / f f / V Top Ta = +25C VDD = 3. V Ta = +25C VDD = 2 V to 5 V Ta = 2C to +7C, VDD = 3. V; +25 C reference AA ; 5 5 (*) AC ; 5(*) B ; 5 23(*2) Max. 6 6 / V + / 2 6 VXSTP XSTP =. Max. V tsta fa Ta = +25 C VDD = 2.V Ta = +25 C VDD=3. V; first year. Max. s 5 Max. 6 / year (*)Equivalent to 3 seconds of monthly deviation. (*2)Equivalent to minute of monthly deviation. Page - 3

7 7. Electrical Characteristics 7.. DC Electrical Characteristics * Unless otherwise specified, GND=V, VDD=3V, Ta=4Cto+85C Symbol Item Pin name Condition Min. Typ. Max. Unit.8x VIH H Input Voltage 5.5 VDD VDD =.5V to 5.5V SCL, SDA.2x VIL L Input Voltage -.3 VDD V.8x VIH2 H Input Voltage2 5.5 EVIN, VDD=. to 5.5V VDD EVIN2 VIL2 L Input Voltage V IOH H Output Current CLKOUT VOH=VDD-.5V -.5 ma IOL CLKOUT.5 / INTRA IOL2 L Output Current / INTRB VOL=.4V 2. ma / RES IOL3 SDA 3. IIL Input Leakage Current SCL VI=5.5V or GND A IOZ Output Off-state / INTRA, / INTRB, Current / RES, SDA VO=5.5V or GND A RDN Pull down resistor EVIN2 built in k VD2B Detector Threshold Voltage. ( falling VDD Ta=+25C V edge of VDD ) VB2D Detector released Voltage. (rising edge of VDD ) VDD Ta=+25C V Detector Threshold and Released Detector VD2B and VB2D Voltage Topt of VDD Temperature Ta=-4 to +85C ± 6 / C coefficient VDET VDDOUT VDDOUT 2 VBAT Voltage Monitoring Voltage VOUT output voltage VOUT output voltage 2 VBAT V VOUT VOUT Ta=+25C, VDD=3.V (Iout=mA) Ta=+25C,VDD=2.V VBAT=3.V (Iout=A) VDD -.2 VBAT -.8 VDD -.3 VBAT -.3 V V IBAT RX-835SA RX-835LC VBAT VDD=V, VBAT=3V SCL=SDA=V EVIN=EVIN2=GND CLKOUT = OPEN na IBATL Leakage Current of VBAT pin VBAT VDD=3.V VBAT=V or 5.5V SCL=SDA=V CLKOUT = OPEN EVIN=EVIN2=GND INTRA=INTRB = Hi-Z -... IDD VDD current VDD A A Page - 4

8 7.2. AC Electrical Characteristics() Unless otherwise specified: GND=V, VDD=.7V to 5.5V, Ta=4C to +85C Input conditions: VIH=.8 VDD, VIL=.2 VDD, VOH=.8 VDD, VOL=.2 VDD, CL=5pF Item Symbol Condition Min. Typ. Max. Unit SCL clock frequency fscl 4 khz SCL clock low time tlow.3 s SCL clock high time thigh.6 s Start condition hold time thd;sta.6 s Stop condition setup time tsu;sto.6 s Start condition setup time tsu;sta.6 s Recovery time from stop condition to start condition trcv 62 s Data setup time tsu:dat 2 ns Data hold time thddat ns SDA L stable time after falling of SCL tpl;dat.9 s SDA off stable time after falling of SCL tpz;dat.9 s Rising time of SCL and SDA (input) tr 3 ns Falling time of SCL and SDA (input) tf 3 ns Spike width that can be removed with input filter tsp 5 ns note: RX-835 supports 4kHz high-speed mode and khz standard mode. S Sr P SCL t LOW t HIGH t HD;STA t SP SDA(IN) t HD;STA t HD;DAT t SU;STA t SU;DAT t SU;STO SDA(OUT) t PZ;DAT t PL;DAT t RCV S Start condition Sr Repeated Start condition P Stop condition Caution: I 2 C communication must be completed from START to STOP within 5ms. If such communication requires over ms, the I 2 C bus interface is reset by the internal bus timeout function. Page - 5

9 7.3. AC Electrical Characteristics(2) Unless otherwise specified: GND=V, VDD=.7V to 5.5V, Ta=4C to +85C Input conditions: VIH=.8 VDD, VIL=.2 VDD, VOH=.8 VDD, VOL=.2 VDD, CL=5pF Symbol Item Condition Min. Typ. Max. Unit t DELAY Output Delay Time of *) Voltage Detector. VDD VB2D 5 9 ms t PD_HL Release Delay Time of Voltage Detector. VB2D VDD 5 s t DB Debounce time of EVIN, *) EVIN2. DBSL= Debounce time selects by DBSL. DBSL= ms t ED Event detection time tdb +3.8 tdb tdb +.8 ms VDD VB2D VD2B tdelay tpd_hl / RES VOH VOL EVIN VIH tdb ted / INTB VOL Page - 6

10 8. Usege 8.. Overview of Functions ) Clock and calendar functions This function is used to set and read out month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 299. ( 2 is not leap year. ) 2) Clock precision adjustment function The clock precision can be adjusted forward or back in units of This function can be used to implement a higher precision clock function, Note: Only the clock precision can be adjusted. The adjustments have no effect on the kHz output from the CLKOUT pin. 3) Periodic interrupt function In addition to the alarm function, Periodic interrupts can be output via the INTRA pin. Select among five Periodic frequency settings: 2 Hz, Hz, /6 Hz, hourly, or monthly. Select among two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or Hz) or a waveform (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts. A polling function is also provided to enable monitoring of pin states via registers. 4) Alarm functions This module is equipped with two alarm functions (Alarm Week and Alarm Month) that output interrupt signals to the host at preset times. The Alarm Week function can be used for day, hour, and minute-based alarm settings, and it outputs interrupt signals via the INTRB pin. Multiple day settings can be selected (such as Monday, Wednesday, Friday, Saturday, and Sunday). The Alarm Month function can be used for month, day, hour, and minute-based settings, and it outputs interrupt signals via the INTRA pin. A polling function is also provided to enable checking of each alarm mode by the host. 5) Data reliability monitoring function. When oscillation has stopped, XSTP is set to one by oscillation stop detector. When the battery voltage (VBAT terminal) drops than VDET voltage threshold value =.25 V (Typ.), VDET is set to one. VDET detection is performed once per second in consideration of the module's low current consumption. When initial power-on occur in this module, PON is set to one. Power-on-reset occurs in VDD rise to VB2D from V and VBAT is V basically. 6) Interface with CPU Data is read and written via the I 2 C bus interface using two signal lines: SCL (clock) and SDA (data). Since neither SCL nor SDA includes a protective diode on the VDD side, a data interface between hosts with differing supply voltages can still be implemented by adding pull-up resistors to the circuit board. The SCL's maximum clock frequency is 4 khz (when VDD VB2D ), which supports the I 2 C bus's high-speed mode(4khz) and standard mode(khz). 7) kHz clock output The kHz clock (with precision equal to that of the built-in quartz oscillator) can be output via the FOUT pin. Note: The precision of this kHz clock output via the FOUT pin cannot be adjusted (even when using the clock precision adjustment function). Clock output is driven by VDD supply. Therefore, when VDD voltage is V, clock output is V too. Page - 7

11 8.2 Automatic battery switch-over circuit. The RX-835 has two power supply terminal (VDD and VBAT) and one power output (VOUT). In case of VDD voltage is less than VD2B, power is supplied from VBAT to keep real time clock function. Also I 2 C interfaceis disabled to protect internal resistor value. When VDD voltage rises to higher than VB2D, an internal power source is switched from VBAT to VDD Example of RX-835 setup procedure in completed product. : Attach battery for RX : Power supply from VDD. 3: Sets the current date and time to RX-835 from CPU. 4: Test the shipment inspection of a system. 5: Do not remove battery of RX : A power supply of a system is turned off. 7: A system is shipped for a customer. Note Either is good even if battery is set in RX-835 first or even if VDD is given first Timing chart of VDD, VBAT and VOUT. VB2C VC2B VDD VBAT VOUT Status I II III II III II Explanation of chart. Status Explanations I When power supplies from VDD only initially. VOUT voltage follows about /2 VDD voltage gradually before tern on internal circuits. II When VDD voltage is above VB2D, VOUT outputs VDD voltage. III When VDD is less than VD2B, VOUT is equal with VBAT. Page - 8

12 8.2.3 Examples of battery connections. Case of primary battery connection. Case of secondary battery connection. And charge voltage = system supply voltage. Case of secondary battery connection. when the main power supply voltage is different from the charge voltage. VDD System power supply. VDD System power supply. VDD System supply 3V 5V VBAT VBAT VBAT VOUT C R VOUT C R VOUT C R GND Ex, CR225 GND Secondary battery or Capacitor. GND Secondary battery or Capacitor Note of battery switch-over circuit. In case the RX-835 with a rechargeable battery or a capacitor that charged from VOUT, the internal resistance of battery (R) should be less than load resistance (Rcpu) as shown following figure. Following figure shows just a timing to turn off VDD, before turn off SW. Current flow to Rcpu will be from a battery or capacitor via VOUT till SW off. If R is quite smaller than Rcpu, the input of voltage of voltage detector of VDD is higher than VD2B. At this case SW is still on until a battery or a capacitor voltage meets VD2B then consume capacity of a battery or a capacitance. Therefore R is limited by following formula. R> Rcpu (VBAT (VD2B)) / (VB2D) And also sometimes R is limited by the specification of back up device. Please refer to specification of a battery or a capacitor. R C2 VOUT RX835 Series CPU supply Vbat VBAT SW2 SW VDD VOLTAGE C3 DETECTOR VC2B CPU Rcpu Page - 9

13 8.3. Register table BANK= Address Data Function D7 D6 D5 D4 D3 D2 D D h Seconds - S4 S2 S S8 S4 S2 S h Minutes - M4 M2 M M8 M4 M2 M 2h Hours 2 /24 - H2 H H8 H4 H2 H P/ A 3h Day of week W4 W2 W 4h Day of month - - D2 D D8 D4 D2 D 5h Months MO MO8 MO4 MO2 MO 6h Years Y8 Y4 Y2 Y Y8 Y4 Y2 Y 7h Digital Offset TEST F6 F5 F4 F3 F2 F F 8h Alarm_Wk ; Minute * WkM4 WkM2 WkM WkM8 WkM4 WkM2 WkM 9h * * WkH2 WkH WkH8 WkH4 WkH2 WkH Alarm_Wk ; Hour WkP/ A Ah Alarm_Wk; Day of week. * WkW6 WkW5 WkW4 WkW3 WkW2 WkW WkW Bh Alarm_Mo ; Minute * MoM4 MoM2 MoM MoM8 MoM4 MoM2 MoM Ch * * MoH2 MoH MoH8 MoH4 MoH2 MoH Alarm_Mo ; Hour MoP/ A Dh RAM * * * * * * * * Eh Control WkALE MoALE DBSL EDEN TEST CT2 CT CT Fh Control 2 BANK VDET XSTP PON EDFG CTFG WkAFG MoAFG TSFG BANK= Address Function Data D7 D6 D5 D4 D3 D2 D D h Time-stamp Sec. EDCH TS4 TS2 TS TS8 TS4 TS2 TS h Time-stamp Min EDCH2 TM4 TM2 TM TM8 TM4 TM2 TM 2h Time-stamp Hour - - TH2 TH TH8 TH4 TH2 TH TP/ A 3h Time-stamp Day of Week TW4 TW2 TW 4h Time-stamp Day of Month - - TD2 TD TD8 TD4 TD2 TD 5h Time-stamp Month TMO TMO8 TMO4 TMO2 TMO 6h Time-stamp Year TY8 TY4 TY2 TY TY8 TY4 TY2 TY 7h Digital Offset Same as BANK 8h Reserved h Ah Bh Alarm_Mo ; Day DYE * MoD2 MoD MoD8 MoD4 MoD2 MoD Ch Alarm_Mo ; Month MOE * * MoMO MoMO8 MoMO4 MoMO2 MoMO Dh RAM Same as BANK Eh Control Same as BANK Fh Control 2 Same as BANK. The PON is a power-on reset flag. The PON is set to "" when a reset occurs, such as during the initial power-up or when recovering from a supply voltage drop. At the same time, all s in the Alarm_Wk, Alarm_Mo, RAM, Digital Offset, Control and Control 2 registers except for the PON, Vdet XSTP s are reset to "". And output of INTRA and INTRB are inhied and Hi-Z. Note: When PON =, all other register values are undefined, so be sure to perform a reset before using the module. Also, be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the time data is incorrect. 2. The TEST s are used only testing in the factory. Clear all TEST s to "" always surely. 3. All s marked with " " are read-only s. The read value of these s are always "". Writing is null and void. 4. All s marked with " " are read-write s. As for these s, set to and clear are possible. 5. By the write-access, it is null and void to set to PON, VDET,XSTP,. Page -

14 BANK= Address Register map after power-on-reset. Function Data D7 D6 D5 D4 D3 D2 D D h seconds h minutes 2h houts 3h Day of week 4h Day of month 5h Month 6h Years 7h Digital offset 8h Alarm_Wk ; Minute 9h Alarm_Wk ; Hour Ah Alarm_Wk ; Day of Week Bh Alarm_Mo ; Minute Ch Alarm_Mo ; Hour Dh RAM Eh Control Fh Control 2 BANK= Address Function Data D7 D6 D5 D4 D3 D2 D D h Time-stamp Sec. h Time-stamp Min 2h Time-stamp Hour 3h Time-stamp Day of Week 4h Time-stamp Day of Month 5h Time-stamp Month 6h Time-stamp Year 7h Digital offset Same as BANK 8h Reserved 9h Ah Bh Alarm_Mo ; Day Ch Alarm_Mo ; Month Dh RAM Same as BANK Eh Control Same as BANK Fh Control 2 Same as BANK. All s marked with " " are read-only s. The read value of these s are always "". Writing is null and void. 2. All s marked with " " are read-write s. As for these s, set to and clear are possible. 3. All s marked with " " are undefined s after power-on-reset. 4. By the write-access, it is null and void to set to PON, VDET, XSTP, MoAFG, WkAFG. Page -

15 Time counter (Reg to 2) Address Function Seconds S4 S2 S S8 S4 S2 S Minutes M4 M2 M M8 M4 M2 M 2 Hours H2 P, /A H H8 H4 H2 H The time counter counts seconds, minutes, and hours. The data format is BCD format (except during 2-hour mode). For example, when the "seconds" register value is " " it indicates 59 seconds. Note with caution that writing non-existent time data may interfere with normal operation of the time counter. ) Second counter Address Function Seconds S4 S2 S S8 S4 S2 S This second counter counts from "" to "," "2," and up to 59 seconds, after which it starts again from seconds. When a value is written to the second counter, the internal counter is also reset to zero in less than one second. 2) Minute counter Addres Function Minutes M4 M2 M M8 M4 M2 M This minute counter counts from "" to "," "2," and up to 59 minutes, after which it starts again from minutes. 3) Hour counter Addres Function Hours 2 /24 H2 P, /A H H8 H4 H2 H /2,24 This is used to select between 2-hour clock operation and 24-hour clock operation. /2,24 Data Description 2-hour clock Default Write / Read 24-hour clock Be sure to select between 2-hour and 24-hour clock operation before writing the time data. The hour counter counts hours, and its clock mode differs according to the value of its /2,24. During 24-hour clock operation, 5 functions as H2 (two-digit hour display). During 2-hour clock operation, 5 functions as an AM/PM indicator (""indicates AM and "" indicates PM). /2,24 Description Address 2 (Hours register) data [h] during 24-hour and 2-hour clock operation modes 24-hour clock 2-hour clock 24-hour clock 2-hour clock 2-hour clock 24-hour clock 2 ( AM 2 ) 2 32 ( PM 2 ) ( AM ) 3 2 ( PM ) 2 2 ( AM 2 ) 4 22 ( PM 2 ) 3 3 ( AM 3 ) 5 23 ( PM 3 ) 4 4 ( AM 4 ) 6 24 ( PM 4 ) 5 5 ( AM 5 ) 7 25 ( PM 5 ) 6 6 ( AM 6 ) 8 26 ( PM 6 ) 7 7 ( AM 7 ) 9 27 ( PM 7 ) 8 8 ( AM 8 ) 2 28 ( PM 8 ) 9 9 ( AM 9 ) 2 29 ( PM 9 ) ( AM ) 22 3 ( PM ) ( AM ) 23 3 ( PM ) Page - 2

16 Day counter (Reg 3) Address Function Day of Week W4 W2 W The day counter is a divide-by-7 counter that counts from to and up 6 before starting again from. The correspondence between days and count values is shown below. Days W4 W2 W Day Remark Sunday h Monday h Tuesday 2 h Write / Read Wednesday 3 h Thursday 4 h Friday 5 h Saturday 6 h Write prohi Do not enter a setting for this. Weekday layout is one of example Calendar counter (Reg 4 to 6) Address Function Day of Month D2 D D8 D4 D2 D 5 Months MO MO8 MO4 MO2 MO 6 Years Y8 Y4 Y2 Y Y8 Y4 Y2 Y The auto calendar function updates all dates, months, and years from January, 2 to December 3, 299. The data format is BCD format. For example, a date register value of " " indicates the 3st. Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter. ) Date counter Address Function Days D2 D D8 D4 D2 D The updating of dates by the date counter varies according to the month setting. A leap year is set whenever the year value is a multiple of four (such as 4, 8, 2, 88, 92, or 96). Days Month Date update pattern Write / Read 2) Month counter, 3, 5, 7, 8,, or 2, 2, 3 to 3, 3, 4, 6, 9, or, 2, 3 to 3,, 2 February in leap year, 2, 3 to 28, 29, February in normal year, 2, 3 to 28,, 2 Address Function Months MO MO8 MO4 MO2 MO The month counter counts from (January), 2 (February), and up to 2 (December), then starts again at (January). 3) Year counter Address Function Years Y8 Y4 Y2 Y Y8 Y4 Y2 Y The year counter counts from,, 2 and up to 99, then starts again at. In any year that is a multiple of four (4, 8, 2, 88, 92, 96, etc.), the dates in February are counted from, 2, 3 and up to 29 before starting again at. Page - 3

17 Clock precision adjustment register (Reg 7) Address Function Digital Offset TEST F6 F5 F4 F3 F2 F F (Default) () () () () () () () () The binary encoded settings in the seven s from F6 to F are used to set the precision of the clock generated from the kHz internal oscillator up to 89 6 in the forward (ahead) or reverse (behind) direction, in units of (Only the clock precision can be adjusted. The kHz output from the FOUT pin is not affected.) When not using this function, be sure to set "" for s F6 to F. Always, clear TEST s to "" surely. For details, see "9.4. Clock Precision Adjustment Function" Alarm_Wk register (Reg 8 to A) Address Function Alarm_Wk ; Minute WkM4 WkM2 WkM WkM8 WkM4 WkM2 WkM 9 Alarm_Wk ; Hour WkH2 WkP, /A WkH WkH8 WkH4 WkH2 WkH A Alarm_Wk ; Day WkW6 WkW5 WkW4 WkW3 WkW2 WkW WkW The Alarm_Wk function is used, along with the WkALE and WkAFG s, to set alarms for specified day, hour, and minute values. When the Alarm_Wk setting matches the current time, INTRB pin is set to "L"and the WkALE is set to "". Note: If the current date/time is used as the Alarm_Wk setting, the alarm will not occur until the counter counts up to the current date/time (i.e., an alarm will occur next time, not immediately). During 24-hour clock operation, the "Alarm_Wk ; Hours" register's 5 (WkH2, WkP, /A) functions as WkH2 (two-digit hour display), and during 2-hour clock operation it functions as an AM/PM indicator. When the Alarm_Wk function's day values (WkW6 to WkW) are all ""Alarm_Wk does not occur Alarm_Month register (Reg B and C) Address Function B Alarm_Mo ; Minute MoM4 MoM2 MoM MoM8 MoM4 MoM2 MoM C Alarm_Mo ; Hour MoH2 MoP, /A MoH MoH8 MoH4 MoH2 MoH The Alarm Month function is used, along with the MoALE and MoAFG s, to set alarms for specified hour and minute values. When the Alarm_Month setting matches the current time, INTRA pin is set to "L"and the MoALE is set to "". Note: If the current time is used as the Alarm_Mo setting, the alarm will not occur until the counter counts up to the current time (i.e., an alarm will occur next time, not immediately). During 24-hour clock operation, the "Alarm_Mo ; Hours" register's 5 (MoH2, MoP, /A) functions as MoH2 (two-digit hour display), and during 2-hour clock operation it functions as an AM/PM indicator RAM register (Reg D) Address Function D User RAM * * * * * * * * These s, set to and clear are possible. Page - 4

18 Control register (Reg E) Address Function E Control WkALE MoALE DBSL EDEN TEST CT2 CT CT (Default) () () () () () () () () ) The default value is the value that is read (or is set internally) after the PON has been set to "," such as after powering up from V or recovering from a supply voltage drop. ) WkALE This is used to set up the Alarm Wk function (to generate alarms matching day, hour, or minute settings). WkALE Data Description Alarm_Wk, match comparison operation invalid Default Write / Read Alarm_Wk, match comparison operation valid (INTRB = "L" when match occurs) For details, see " Alarm Wk Function". 2) MoALE This is used to set up the Alarm Mo function (to generate alarms matching hour or minute settings). MoALE Data Description Alarm_Mo, match comparison operation invalid Default Write / Read Alarm_Mo, match comparison operation valid (INTRA = "L" when match occurs) For details, see " Alarm Mo Function". 3) DBSL This is used to select de-bounce time in EVIN input. DBSL Data Description Write / Read De-bounce time are set up to 996ms. (Typ.) Default De-bounce time are set up to 35ms. (Typ.) 4) EDEN This enables Event Detection and Timestamp function. EDEN Data Description Write / Read Event detection are stops, and BANK- data are cleared. Address,,2,4,5,6 of Bank and EDFG of address F too. Enables event detection and timestamp. Default 5) TEST This is used by the manufacturer for testing. Always, clear this to "" surely. Be careful to avoid writing a "" to this when writing to other s. TEST Data Description Write / Read Normal operation mode Default Setting prohied (Factory test mode) 6) CT2, CT, and CT s These s are used to set up the operation of the periodic interrupt function that uses the INTRB pin. CT2 CT CT INTRB pin's output setting Waveform mode Cycle/Fall timing INTRB = Hi-Z (= OFF) Default INTRB = Fixed low Pulse mode ) 2 Hz (5% duty) Pulse mode ) Hz (5% duty) Level mode 2) Once per second (Synchronous with per-second count-up) Level mode 2) Once per minute (Occurs when seconds reach ":") Level mode 2) Once per hour (Occurs when minutes and seconds reach ":") Level mode 2) Once per month (Occurs at :: on first day of month) For details, see "9.5.. Periodic Interrupt". Page - 5

19 8.3.. Control register 2 (Reg F) Address Function BANK F Control 2 VDET XSTP PON EDFG CTFG WkAFG MoAFG TSFG (Default) () () () () () () () () )The default value is the value that is read (or is set internally) after the PON has been set to "," such as after powering up from V or recovering from a supply voltage drop. 2)" " are read-only s. The read value of these s are always "". Writing is null and void. ) BANK This uses switch to Bank or Bank. 2) TSFG This indicate reliability of the timestamp data. When timestamp event occurs, if XSTP and VDET was "" both, then TSFG is set to "". Or if one of XSTP or VDET are set, then TSFG are cleared to "". BANK TSFG Data Description Write (BANK) Read (TSFG) Access is possible to a register of BANK. Time and calendar. Default Access is possible to a register of BANK. Time stamp data. Time stamp data are invalidly. When clears EDEN, TSFG clears too. Time stamp data are validly. 3) VDET VDET shows that the inside voltage was less than VDET VDET Data Description Clears the VDET to zero, restarts the VBAT drop detection operation and sets up for next VBAT drop detection operation Write Can not write. Default Default Default VBAT drop was not detected Read VBAT drop was detected (result is that value is held until cleared to zero) For details, see "9.7. Detection Functions". 4) XSTP XSTP must be cleared to zero before it is used. When it was detected a vibration stop, XSTP is set to "". "" shows that there is not a stop of an oscillation. If detect oscillation stop, XSTP set to "". ( Note: The logic of this is reverse of RX-825.) XSTP Data Description Write Read Starts the oscillation stop detection function. Can not write. Oscillation stop was not detected Oscillation stop was detected (result is that value is held until a "" is written) Default 4) PON This indicates the power-on reset detection function's detection results. The PON is set (= ) when the internal power-on reset function operates. PON Data Description Write Clears the PON to zero and sets up next detection operation Can not write. Power-on reset was not detected Read Power-on reset was detected. Default (result is that value is held until cleared to zero) When PON = "" all s in the Clock Precision Adjustment register and in the Control and Control 2 registers (except for the PON, VDET and XSTP s) are reset to "". This also causes output from INTRA and INTRB pin to be stopped (= Hi-Z). VDD should rise from less than.2v so that Power-On-Reset occurs. VBAT need less than.2v too. Page - 6

20 8.3.. Diagnosis of status based on detection results The status of power supplies and reliability of time and calendar can be confirmed by reading the detection results indicated by PON, XSTP and VDET. The following are status diagnosis based on various combinations of detection results. Address F h Diagnosis of status Control 2 Register Status of power supply and Status of clock and backup PON XSTP VDET oscillation circuit Supply voltage was normal. But oscillation has stopped. Supply voltage has dropped and oscillation has stopped. Normal status. Supply voltage has dropped but oscillation continues. Supply voltage has dropped to V. Power supply flickering is likely. Clock abnormality has occurred Initialization is required Clock has stopped temporarily, possibly due to mechanical clash, etc. Clock abnormality has occurred Initialization is required Clock has stopped, maybe due to drop in backup power supply. Normal status. Maybe initialization is unnecessary. But, exchange of a battery will be necessary. Initialization is required regardless of the clock status and whether or not a voltage drop has occurred. Initialization is required. VDD terminal voltage VBAT terminal voltage VLOW Threshold voltage.25 V(Typ.) kHz oscillation VDET detector Power-on reset (PON) Oscillation stop detector XST VDET Internal initialization period (s.) PON, VDET XST VDET XST Internal initialization period (s) PON,VDET XST Page - 7

21 8.4 Time stamp functions EDFG When an event signal valid was detected, EDFG is set. An event terminal detected first is recorded in EDCH, EDCH2, after EDEN was set.when it was detected at the same time by two terminals, both s are set. EDFG status Event detection does not yet occur. (Default ) Event detected. Note: "" is not written in EDFG. Only zero clear is possible Time stamp registers. (BANK=,address -6h) Adrs Function Data D7 D6 D5 D4 D3 D2 D D h Time-stamp Sec. EDCH TS4 TS2 TS TS8 TS4 TS2 TS h Time-stamp Min EDCH2 TM4 TM2 TM TM8 TM4 TM2 TM 2h Time-stamp Hour - - TH2 TH TH8 TH4 TH2 TH TP/ A 3h Time-stamp Day of Week TW4 TW2 TW 4h Time-stamp Day of Month - - TD2 TD TD8 TD4 TD2 TD 5h Time-stamp Month TMO TMO8 TMO4 TMO2 TMO 6h Time-stamp Year TY8 TY4 TY2 TY TY8 TY4 TY2 TY All time stamp register are read only. Either date and time when an event was input first of an EVIN terminal and a RVIN2 terminal are recorded. The next event is not recorded unless EDEN is set to from again. When EDEN is cleared, all time stamp registers are cleared by zero. Therefore, time stamp data must be read before clearing an EDEN surely EDCH,EDCH2 Indication of event input terminal. EDCH2 EDCH Result. Events is not detected. (Default) Event was detected in EVIN terminal. Event was detected in EVIN2 terminal. Two event was detected in EVIN and EVIN2 terminals same time. Note: When two signals were input between 7.8ms(Max.), it is judged to be the input of the same time EDFG of event detection function. EDFG result. Event input is not detected. (Default 値 ) Event input is detected. When EDEN is, event input is detected in High from Low of EVIN terminal (tdb) time later. After 7.8ms, EDFG is set to and INT terminal asserted to Low. Detected event terminal is memorized in EDCH,EDCH2. When detected EVIN; EDCH=, When detected EVIN2; EDCH2=, When during time of tdb, EVIN and EVIN2 kept high level, then both EDCH and EDCH2 are set to. This time is recorded by a time stamp register. As for the EDFG flag, only clearing to a zero is possible As for the INT output of event detection, it is assumed that When EDFG is cleared by zero, INT output is disabled. Event detection is available in both of VBAT or VDD. Page - 8

22 8.4.5 Event detection timing chart. VOUT ( VDD or VBAT ) V DET EVIN EVIN2 VIH t DB t DB t DB t DB EVIN+EVIN2 After debounce INT 7.8ms 7.8ms EDEN X EDEN EDEN EDEN EDFG X VDET,XSTP= EDFG VDET/XSTP X / / TSFG X Time X Set Time to A. A+ A+2 A+3 Time Stamp Registers X ALL= A+ ALL= A+3 EDCH/2 X / / / / Explanations [ ] [ 2 ] [ 3 ] [ 4 ] The operation procedure. Explanation number shows step number in timing chart. [ ] Set time and date. please initialize, clear to zero the VDET and XSTP, and set to EDEN. Set an input terminal of EVIN,2 in Low level before setting EDEN to. [ 2 ] It is a steady event detection operation. When event is input into EVIN2 terminal, event is detected tdb time later. After 7.8ms,,EDCH2 is set at to EDFG in Low INT. The time at that time is recorded in Time Stamp Register. [ 3 ] The condition that was input event into with event detection condition again. Nothing changes to have already become EDFG=. INT terminal is released by Hi-Z when assumed a zero clear EDFG then. [ 3 ] When EDEN is cleared by a zero, all Time Stamp Register is cleared. [ 4 ] While event is input, event detection is not performed even if EDEN is set to. Page - 9

23 VOUT ( VDD or VBAT ) V DET EVIN t DB t DB EVIN2 EVIN+EVIN2 ( After debounce. ) INT 7.8ms 7.8ms EDEN EDFG EDFG VDET/XSTP / / / VDET TSFG Real time A+3 A+4 A+5 A+6 A+7 Time Stamp Registers A+3 A+5 A+6 EDCH/2 / / / explanations [ 5 ] [ 6 ] [5] When VOUT voltage dropped in less than VDET voltage, a VDET is set to. When event is detected, at the time of VDET=, TSFG is cleared to. And so TSFG= shows that a time stamp is untrustworthy. Time-Stamp Registers is cleared to zero in hatching period. [6] When the EVIN and EVIN2 input within tdb, both EDCH,EDCH2 set to. Time-Stamp Registers is cleared to zero in hatching period. Page - 2

24 8.5 Clock Precision Adjustment Function The clock precision can be set ahead or behind. This function can be used to implement a higher-precision clock function, such as by: enabling higher clock precision throughout the year by taking seasonal clock precision adjustments into account in advance, or enabling correction of temperature-related clock precision variation in systems that include a temperature detection function. Note: Only the clock precision can be adjusted. The adjustments have no effect on the kHz output from the FOUT pin. Address Function Digital Offset TEST F6 F5 F4 F3 F2 F F (Default) () () () () () () () () ) TEST must be cleared surely. The binary encoded settings in the seven s from F6 to F are used to set the precision of the clock generated from the kHz internal oscillator up to in the forward (ahead) or reverse (behind) direction, in units of ) When not using this function, be sure to set "" for s F6 to F. 2) This function operates every twenty seconds (at seconds, 2 seconds, and 4 seconds within each minute), which changes the cycle of the periodic interrupts that occur via this timing. (See "9.5. Periodic Interrupt Function".) 3) Always, clear TEST s to "" surely. Note : TEST can be set to by write access. Be careful Adjustment clock precision ) Adjustment range and resolution Adjustment range Adjustment resolution Internal timing of adjustment 89. x 6 to +89. x x 6 Once every 2 seconds (at "", "2" and "4" seconds) 2) Adjustment amount and adjustment value Adjustment amount Adjustment data ( 6 ) Decimal / Hexadecimal F6 F5 F4 F3 F2 F F / 3F h / 3E h / 3D h / / / 2 h OFF / h OFF / h +3.5 / 7F h / 7E h / 7D h / 44 h / 43 h / 42 h OFF 63 / 4 h OFF 64 / 4 h Page - 2

25 8.5.2 Adjustment examples Example ) Setting time forward Objective) To adjust (advance) the clock precision when FOUT clock output is kHz () Determine the current amount of variance kHz ( ) / [ ] = Reference values (2) Calculate the optimum adjustment data (decimal value) relative to the current variance. Adjustment data = variance / adjustment resolution = 9.6 / (decimal values are roundeddown from 4 and up from 5) For adjusting forward from a retarded variance, this formula can be corrected using reciprocal numbers, but since this product inverts the +/- attributes, this formula can be used as it is. (3) Calculate the setting adjustment data (hexadecimal) To calculate the setting adjustment data while taking 7- binary encoding into account, subtract the adjustment data (decimal) from 28 (8h). Setting adjustment data = 28 3 = 25 (decimal) = 8h 3h = 7Dh (hexadecimal) Example 2) Setting time backward Objective) To adjust (set back) the clock precision when FOUT clock output is kHz () Determine the current amount of variance kHz ( ) / [ ] = reference values (2) Calculate the optimum adjustment data (decimal value) relative to the current variance. Adjustment data = (variance / adjustment resolution) + = (+9.6 / 3.5) + ADD since reference value is h +4 (decimal values are roundeddown from 4 and up from 5) For adjusting backward from an advanced variance, this formula can be corrected using reciprocal numbers, but since this product inverts the +/- attributes, this formula can be used as it is. (3) Calculate the setting adjustment data (hexadecimal) The value "4" can be used in hexadecimal as it is (4h). Setting adjustment data = 4 h (hexadecimal) Page - 22

26 8.6 Periodic Interrupt Function Periodic interrupt output can be obtained via the INTRB pin. Select among five periodic-cycle settings: 2 Hz (once per.5 seconds), Hz (once per second), /6 Hz (once per minute), /36 Hz (once per hour), or monthly (on the st of each month). Select among two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or Hz) or a waveform (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts. A polling function is also provided to enable monitoring of pin states via registers. Address Function E Control WkALE MoALE DBSL EDEN TEST CT2 CT CT (Default) () () () () () () () () BANK F Control 2 TSFG VDET XSTP PON EDFG CTFG WkAFG MoAFG (Default) () () () () () () () () ) The default value is the value that is read (or is set internally) after the PON has been set to "," such as after powering up from V or recovering from a supply voltage drop. 2) " " are read-only s. The read value of these s are always "". Writing is null and void. *)Pulse mode : outputs 2Hz or Hz. CTFG /INTB about 46s Update timing of seconds. Writes seconds new value from CPU. In a pulse mode, update of seconds is behind with about 46s from a falling edge of INTRB. Therefore, during this 46s, please consider it because the time and calendar is old. When CPU writes seconds new value, INTRB outputs low level. Cause is because new value was written to seconds. *2)Level mode: A interrupt period selectable from s,min, hour and a month. Count up of a second synchronizes with an falling edge of INTRB. The timing chart example that an interrupt period set in every seconds. Clears CTFG. CTFG INTRB Clears CTFG. Update of seconds. Update of seconds. Next update of seconds. Note: When Clock Precision Adjustment Function works, a period of interrupt changes by that quantity of the adjustment once per 2 seconds or one minute. Pulse mode: ±3.784 msec changes at the maximum for a High section of an output pulse of Hz. And Duty is 5±.3784%. ±3.784 msec changes at the maximum for a Low section of an output pulse of 2Hz. And Duty is 5±.3784%. Level mode: Once per second period changes 3.784ms maximum. Page - 23

27 8.7 Alarm Interrupt Function 8.7. MoAFG, WkAFG MoAFG, WkAFG Status Alarm does not yet occur. (Default ) Alarm occurred. When MoALE or WkALE s are, these flag s are worked. When alarm occurs, after 6s these flag are set to. CPU can clear by, but can not set to these s. When MoALE,WkALE is "", value of MoAFG,WkAFG are "" always. 5s 5s MoAFG(WkAFG) /INTx Clears MoAFG (WkAFG) Alarm occur. Alarm occur. Clears MoAFG (WkAFG) Alarm_Wk register (BANK= Address 8-Ah) Alarm_Wk minutes register (BANK=, address 8h) D7 D6 D5 D4 D3 D2 D D * WkM4 WkM2 WkM WkM8 WkM4 WkM2 WkM Default Alarm_Wk Hours register (BANK=, address 9h) D7 D6 D5 D4 D3 D2 D D * * WkH2 WkH WkH WkH4 WkH WkH WkP/ A 8 2 Default Alarm_Wk Weekday register (BANK=, address Ah) D7 D6 D5 D4 D3 D2 D D * WkW6 WkW5 WkW4 WkW3 WkAW2 WkW WkW Default *) Default = When PON was set by power-on, default value loads automatically. As for the *, read and write are possible, like RAM. And the value is not related to alarm. When MoALE=, it can be used as user RAM each Alarm_Wk(3 bytes). D5 of Alarm_Mo register shows AM,PM in the 2 hours system.(am=, PM= ) and shows AH2 (2 digit of hours.) Hour counter(address 2) is update to 32(BCD) from PM. WkW to WkW6 is compare the day of week counter. (W4,W2,W) =(,,) to (,,). When AW6 from AW are all "", Alarm_Mo does not works. Page - 24

28 8.7.3 Alarm_Mo Register(BANK= and (Bh and Ch) Alarm_Mo minutes register (BANK=, Address Bh) D7 D6 D5 D4 D3 D2 D D * MoM4 MoM2 MoM MoM8 MoM4 MoM2 MoM (Default*) Alarm_Mo Hours register (BANK=,Address Ch) D7 D6 D5 D4 D 3 D2 D D * * MoH2 MoH MoH8 MoH4 MoH2 MoH MoP/ A (Default*) Alarm_Mo Day Register (BANK=,Address Bh) D7 D6 D5 D4 D3 D2 D D DYE * MoD2 MoD MoD8 MoD4 MoD2 MoD (Default*) Alarm_Mo Month Register (BANK=, AddressCh) D7 D6 D5 D4 D3 D2 D D MOE * * MoMO MoMO8 MoMO4 MoMO2 MoMO (Default*) *) Default = When PON was set by power-on, default value loads automatically. As for the *, read and write are possible, like RAM. And the value is not related to alarm. When MoALE=, it can be used as user RAM each Alarm_Mo(4 bytes). D5 of Alarm_Mo register shows AM,PM in the 2 hours system.(am=, PM= ) and shows AH2 (2 digit of hours.) Hour counter(address 2) is update to 32(BCD) from PM. DYE enables day of Alarm_Wk MOE enables Month of Alarm_Wk Usage of DYE, MOE. MOE DYE Alarm occurs. (WoALE = : Enables alarm of week.) Hours and Minutes. ( Once per day.) Default Day, Hours and Minutes.(Once per Month.) Month, Hours, and Minutes. (Once per day in selected month.) Month, Days, Hours, and Minutes. (once per year.) Page - 25

29 8.7.4 Programming example of time alarm. Ex. ) Every year January 3th 9:23. Registers of Alarm_Wk. Bit layout. D7 D6 D5 D4 D3 D2 D D 8h in Bank. Minutes 9h in Bank. Hours Bh in Bank. Days Ch in Bank. Month Ex.2 )Every month 7th PM 5:3 in 2hour system. Registers of Alarm_Wk. Bit layout. D7 D6 D5 D4 D3 D2 D D 8h in Bank. Minutes 9h in Bank. Hours Bh in Bank. Days Ch in Bank. Month x x x x x x x Ex.3)Every day 23:45. Registers of Alarm_Wk. Note: Bit layout. D7 D6 D5 D4 D3 D2 D D 8h in Bank. Minutes 9h in Bank. Hours Bh in Bank. Days x x x x x x x Ch in Bank. Month x x x x x x x The value of "x" does not affect Alarm function. 7) WkAFG ( MoAFG ) These s are valid only when the WkALE ( MoALE ) value is "".The WkAFG ( MoAFG ) set to "" when Alarm Wk ( Alarm Mo ) has occurred. The INTRB (INTRA) = "L" status that is set at this time can be set to OFF by writing a "" to this. WkAFG Data Description ( MoAFG ) Write Read INTRB (INTRA ) pin = OFF = Hi-z Can not write. Alarm_Wk ( Alarm Mo ) time setting does not match current time. This 's value is always "" when the WkALE ( MoALE ) 's setting is "") Alarm_Wk occurred. This value"" is kept until cleared to zero. Default Default Page - 26

30 8.7.5 Alarm_Mo function The Alarm_Mo function generates interrupt signals (output via the INTRA pin) that correspond to specified month, date, hours and minutes. A polling function is also provided to enable checking of each alarm mode by the host. Related registers Address Function h inbank Minutes M4 M2 M M8 M4 M2 M 2h in Bank Hours H2 P, /A H H8 H4 H2 H 4h in Bank Day of month D2 D D8 D4 D2 D 5h Bank Months MO MO8 MO4 MO2 MO Bh Bank Alarm_Mo ; Minute * MoM4 MoM2 MoM MoM8 MoM4 MoM2 MoM Ch Bank Alarm_Mo ; Hour * * MoH2 Mo P/ A MoH MoH8 MoH4 MoH2 MoH Bh Bank Alarm_Mo ; Day DYE * MoD2 MoD MoD8 MoD4 MoD2 MoD Ch Bank Alarm_Mo ; Month MOE * * MoMO MoMO8 MoMO4 MoMO2 MoMO Control WkALE MoALE DBSL EDEN TEST CT2 CT CT Eh (Default) () () () ( ) ( ) () () () Fh BANK Control 2 VDET XSTP PON EDFG CTFG WkAFG MoAFG TSFG (Default) () () () ( ) ( ) () () () ) The default value is the value that is read (or is set internally) after the PON has been set to "," such as after powering up from V or recovering from a supply voltage drop. 2) " " are read-only s. The read value of these s are always "". Writing is null and void. When the Alarm_Mo setting matches the current time, INTRA pin is set to "L"and the MoALE is set to "". Note: If the current date/time is used as the Alarm_Mo setting, the alarm will not occur until the counter counts up to the current date/time (i.e., an alarm will occur next time, not immediately). During 24-hour clock operation, the "Alarm_Mo ; Hours" register's 5 (MoH2, MoP, /A) functions as MoH2 (two-digit hour display), and during 2-hour clock operation it functions as an AM/PM indicator. ) MoALE This is used to set up the Alarm_Mo function. MoALE Data Description Alarm_Mo, match comparison operation invalid Default Write / Read Alarm_Mo, match comparison operation valid (INTRA = "L" when match occurs) When using the Alarm_Mo function, first set this MoALE value as "," then stop the function. Next, set current time and date, and reset the MoAFG. Finally, set "" to the MoALE for Alarm_Mo function as valid. The reason for first setting the MoALE value as ""is to prevent INTRA = "L" output in the event that a match between the current time and alarm setting occurs while the alarm setting is still being made. 2) MoAFG This is valid only when the MoALE value is "". When a match occurs between the Alarm_Mo setting and the current time, the MoAFG value becomes "" approximately 6 s afterward. (There is no effect when the MoALE becomes "".) The INTRA = "L" status that is set at this time can be set to OFF by writing a "" to this. MoAFG Data Description INTRA pin = OFF (Hi-z) (only when the Event detection output is Default OFF) Write Can not write. Alarm_Mo time setting does not match current time Default (This 's value is always "" when the MoALE 's setting is "") Read Alarm_Mo time setting matches current time (result is that value is held until cleared to zero) When a "" is written to the MoAFG, provisionally the MoAFG value is "" and the INTRA pin status is OFF (Hi-z). However, as long as the MoALE value is ""the Alarm_Mo function continues to operate, and Alarm_Mo occurs again the next time the same specified time arrives. You can stop Alarm_Mo from occurring by writing "" to the MoALE to set this function as invalid. Page - 27