PCF2127A. 1. General description. 2. Features. Integrated RTC, TCXO and quartz crystal DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA DRAFT

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1 Rev February 29 AFT DRAF RAFT DRA Preliminary data sheet 1. General description The is a CMOS real time clock and calendar with an integrated temperature compensated xtal oscillator (TCXO) and a khz quartz crystal optimized for very high accuracy and very low power consumption. The has 512 bytes of general purpose static RAM, a selectable I 2 C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function and many other features. 2. Features Temperature compensated crystal oscillator (TCXO) with integrated capacitors Accuracy: ±3 ppm from 2 C to +7 C Integration of a khz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes and seconds 512 bytes of general purpose static RAM Timestamp input pin Timestamp function with interrupt capability Two line bidirectional 1 MHz fast mode plus I 2 C interface 3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage pin Battery low detection Extra power fail detection with input and output pins Power-on reset override Oscillator stop detection Open-drain interrupt and system reset pin Programmable 1 second or 1 minute interrupt Programmable countdown timer with interrupt capability Programmable watchdog timer with interrupt and reset capability Programmable alarm function with interrupt capability Programmable square wave open-drain output pin Clock operating voltage: 1.2 V to 4.2 V Low supply current; typical.65 μa at V DD = 3. V and T amb =25 C

2 AFT DRAF RAFT DRA 3. Ordering information Table 1. Ordering information Type number Package Name Description Version T/1 SO2 plastic small outline package; 2 leads; body width 7.5 mm SOT Marking Table 2. Marking codes Type number T/1 Marking code _1 Preliminary data sheet Rev February 29 2 of 77

3 AFT DRAF RAFT DRA 5. Block diagram INT OSCI TCXO CLKOUT khz OSCO DIVIDER AND TIMER Control_1 Control_2 Control_3 Seconds h 1h 2h 3h BBS V DD V BAT V SS BATTERY BACK UP SWITCH-OVER CIRCUITRY OSCILLATOR MONITOR internal power supply RESET TEMP 1 Hz LOGIC CONTROL Minutes Hours Days Weekdays Months Years Second_alarm Minute_alarm 4h 5h 6h 7h 8h 9h Ah Bh RST Hour_alarm Ch SDA/CE SDO SDI SCL IFS SERIAL BUS INTERFACE INTERFACE SELECTORS ADDRESS REGISTER Day_alarm Weekday_alarm CLKOUT_ctl Watchdg_tim_ctl Watchdg_tim_val Timestp_ctl Sec_timestp Dh Eh Fh 1h 11h 12h 13h SCL SDA/CE I 2 C BUS INTERFACE Min_timestp Hour_timestp Day_timestp 14h 15h 16h TS Mon_timestp 17h SCL Year_timestp 18h PFI 1.25 V (internal) SDO SDI SDA/CE TEMP 512 BYTES STATIC RAM TEMPERATURE SENSOR Crystal_aging RAM_addr_MSB RAM_addr_LSB RAM_wrt_cmd RAM_rd_cmd 19h 1Ah 1Bh 1Ch 1Dh PFO TEST 1aaj675 Fig 1. Block diagram of _1 Preliminary data sheet Rev February 29 3 of 77

4 AFT DRAF RAFT DRA 6. Pinning information 6.1 Pinning SCL 1 2 V DD SDI 2 19 V BAT SDO 3 18 BBS SDA/CE 4 17 INT IFS TS RST PFI CLKOUT 7 14 PFO V SS 8 13 TEST aaj676 Top view. For mechanical details, see Figure 57. Fig 2. Pin configuration of (SO2) 6.2 Pin description Table 3. Pin description of Symbol Pin Description SCL 1 combined serial clock input for both I 2 C-bus and SPI-bus; may float when CE inactive SDI 2 serial data input for SPI-bus; may float when CE inactive SDO 3 serial data output for SPI-bus, push-pull SDA/CE 4 combined serial data input and output for the I 2 C interface and chip enable input (active LOW) for the SPI-bus IFS 5 interface selector input connect to ground to select the SPI-bus connect to BBS (pin 18) to select the I 2 C interface TS 6 timestamp input (active LOW) with 2 kω internal pull-up resistor CLKOUT 7 clock output (open-drain) V SS 8 ground 9 not connected; do not use as feed through TEST 13 do not connect; do not use as feed through PFO 14 power fail output (open-drain; active LOW) PFI 15 power fail input RST 16 reset output (open-drain; active LOW) INT 17 interrupt output (open-drain; active LOW) _1 Preliminary data sheet Rev February 29 4 of 77

5 AFT DRAF RAFT DRA Table 3. Pin description of continued Symbol Pin Description BBS 18 output voltage (battery backed) V BAT 19 battery supply voltage (backup) V DD 2 supply voltage 7. Device protection diagram SCL SDI V DD V BAT BBS SDO SDA/CE IFS INT RST PFI TS CLKOUT V SS 1aaj677 PFO TEST Fig 3. Device diode protection diagram of _1 Preliminary data sheet Rev February 29 5 of 77

6 AFT DRAF 8. Functional description _1 RAFT DRA The is a real time clock and calendar (RTC) with an on-chip temperature compensated crystal oscillator (TCXO) and a khz quartz crystal integrated into the same package. The address and data are transferred by a selectable 1 MHz fast mode plus I 2 C-bus or a 3 line SPI-bus with separate data input and output (see Section 8.16). The maximum speed of the SPI-bus is 6.5 Mbit/s. The contains thirty 8-bit registers, that are used for many different functions, such as clock, alarm, watchdog, timer, timestamp etc. (see Section 8.1). The has an output reset pin: the output reset is activated on Power-On Reset (POR), and whenever the oscillator is stopped (see Section 8.7). 512 bytes of general purpose static RAM are available (see Section 8.5). The has a backup battery input pin and backup battery switch-over circuit which monitors the main power supply and automatically switches to the backup battery when a power failure condition is detected (see Section 8.4.1). Accurate timekeeping is maintained even when the main power supply is interrupted. A battery low detection circuit monitors the status of the battery (see Section 8.4.3). When the battery voltage goes below a threshold value, a flag is set to indicate that the battery must be replaced soon. This ensures the integrity of the data during periods of battery backup. A power failure detection circuit monitors the voltage of the power fail input pin PFI. When the voltage of PFI goes below an internal reference (1.25 V), the power fail output pin PFO is activated (see Section 8.4.4). 8.1 Register overview The contains thirty 8-bit registers (see Table 4) with an auto-incrementing address register: the built-in address register will increment automatically after each read or write data byte up to the register 1Bh. After register 1Bh the auto-incrementing will wrap around to address h. The registers 1Ch and 1Dh must be addressed explicitly (see Figure 4). The first three registers (memory address h, 1h and 2h) are used as control registers (see Section 8.2) The memory addresses 3h through to 9h are used as counters for the clock function (seconds up to years). The date is automatically adjusted for months with fewer than 31 days, including corrections for leap years. The clock can operate in 12-hour mode with an AM/PM indication or in 24-hour mode (see Section 8.8) Addresses Ah through Eh define the alarm function. It can be selected that an interrupt is generated when an alarm event occurs (see Section 8.9) The register Fh defines the temperature measurement period and the clock out mode. The temperature measurement can be selected from every 4 minutes (default) down to every 3 seconds (see Section 8.3.1). CLKOUT frequencies of khz (default) down to 1 Hz for use as a system clock, a microcontroller clock etc. can be chosen (see Section 8.13) Preliminary data sheet Rev February 29 6 of 77

7 AFT DRAF RAFT DRA Address registers 1h and 11h are used for the watchdog and countdown timer functions. Either the watchdog timer or the countdown timer can be enabled (see Section 8.1). The timer has four selectable source clocks allowing for timer periods from less than 1 ms to greater than 4 hours. It is possible to select whether an interrupt or a pulse on the reset pin will be generated when the watchdog times out or that an interrupt will be generated at the end of every countdown Address registers 12h to 18h are used for the timestamp function. When the trigger-event happens the actual time is saved in the timestamp registers (see Section 8.11) Address register 19h is used for the correction of the crystal aging effect (see Section 8.3.2) Address registers 1Ah and 1Bh define the RAM address. Address register 1Ch (RAM_wrt_cmd) is the RAM write command; address register 1Dh (RAM_rd_cmd) is the RAM read command. Data is transferred to or from the RAM via the serial interface (see Section 8.5) The registers Seconds, Minutes, Hours, Days, Months and Years are all coded in BCD (binary coded decimal) format to simplify application use. An example BCD encoding is given in Table 13. Other registers are either bit-wise or standard binary address register h 1h 2h 3h... 19h 1Ah 1Bh 1Ch 1Dh auto-increment wrap around not reachable by auto-inc. - needs to be addressed directly not reachable by auto-inc. - needs to be addressed directly 1aaj37 Fig 4. Handling address registers When one of the RTC registers is read the content of all counters is frozen. This prevents a faulty reading of the clock and calendar during a carry condition. _1 Preliminary data sheet Rev February 29 7 of 77

8 AFT DRAF RAFT DRA Table 4. Register overview and control bits default values Bit positions labelled as - are not implemented and will return a when read; don t care. Bit T must always be written with logic. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit Control registers h Control_1 EXT_TEST T STOP TSF1 POR_OVRD 12_24 MI SI 1 1h Control_2 MSF WDTF TSF2 AF CDTF TSIE AIE CDTIE 2h Control_3 PWRMNG BTSE BF BLF BIE BLIE Time and date registers 3h Seconds OSF SECONDS ( to 59) 1 X X X X X X X 4h Minutes - MINUTES ( to 59) X X X X X X X 5h Hours - - AMPM HOURS (1 to 12) in 12 h mode X X X X X X HOURS ( to 23) in 24 h mode X X X X X X 6h Days - - DAYS (1 to 31) X X X X X X 7h Weekdays WEEKDAYS X X X 8h Months MONTHS (1 to 12) X X X X X 9h Years YEARS ( to 99) X X X X X X X X Alarm registers Ah Second_alarm AEN_S SECOND_ALARM ( to 59) 1 X X X X X X X Bh Minute_alarm AEN_M MINUTE_ALARM ( to 59) 1 X X X X X X X Ch Hour_alarm AEN_H - AMPM HOUR_ALARM (1 to 12) in 12 h mode 1 X X X X X X HOUR_ALARM ( to 23) in 24 h mode X X X X X X Dh Day_alarm AEN_D - DAY_ALARM (1 to 31) 1 X X X X X X Eh Weekday_alarm AEN_W WEEKDAY_ALARM 1 X X X _1 Preliminary data sheet Rev February 29 8 of 77

9 AFT DRAF RAFT DRA Table 4. Register overview and control bits default values continued Bit positions labelled as - are not implemented and will return a when read; don t care. Bit T must always be written with logic. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit CLKOUT control register Fh CLKOUT_ctl TCR COF Watchdog registers 1h Watchdg_tim_ctl WD_CD TI_TP TF h Watchdg_tim_val WATCHDG_TIM_VAL X X X X X X X X Timestamp registers 12h Timestp_ctl TSM TSOFF - 1_O_16_TIMESTP X X X X X 13h Sec_timestp - SECOND_TIMESTP X X X X X X X 14h Min_timestp - MINUTE_TIMESTP X X X X X X X 15h Hour_timestp - - AMPM HOUR_TIMESTP (1 to 12) in 12 h mode X X X X X X HOUR_TIMESTP ( to 23) in 24 h mode X X X X X X 16h Day_timestp - - DAY_TIMESTP (1 to 31) X X X X X X 17h Mon_timestp MONTH_TIMESTP (1 to 12) X X X X X 18h Year_timestp YEAR_TIMESTP ( to 99) X X X X X X X X Crystal aging register 19h Crystal_aging AO 1 RAM registers 1Ah RAM_addr_MSB RA8 1Bh RAM_addr_LSB RA[7:] 1Ch RAM_wrt_cmd X X X X X X X X 1Dh RAM_rd_cmd X X X X X X X X _1 8.2 Control registers has thirty 8-bit registers. The first 3 registers with the addresses h, 1h and 2h are used as control registers. Preliminary data sheet Rev February 29 9 of 77

10 AFT DRAF Register Control_1 RAFT DRA Table 5. Register Control_1 (h) bits description Bit Symbol Value Description Reference 7 EXT_TEST [1] normal mode Section external clock test mode 6 T [2] unused 5 STOP [1] RTC source clock runs Section RTC clock is stopped; RTC divider chain flip-flops are asynchronously set to logic ; CLKOUT at khz, khz or khz is still available 4 TSF1 [1] no timestamp interrupt generated Section flag set when TS input is driven to an intermediate level between power supply and ground; flag must be cleared to clear interrupt 3 POR_OVRD [1] power-on reset override facility disabled; set to logic for normal operation Section power-on reset override enabled 2 12_24 [1] 24 hour mode selected Table hour mode selected 1 MI [1] minute interrupt disabled Section minute interrupt enabled SI [1] second interrupt disabled 1 second interrupt enabled [1] Default value. [2] When writing to the register this bit has always to be set to logic Register Control_2 Table 6. Register Control_2 (1h) bits description Bit Symbol Value Description Reference 7 MSF [1] no minute or second interrupt generated Section flag set when minute or second interrupt generated; flag must be cleared to clear interrupt 6 WDTF [1] no watchdog timer interrupt or reset generated Section flag set when watchdog timer interrupt or reset generated; flag cannot be cleared by using the interface (read-only) 5 TSF2 [1] no timestamp interrupt generated Section flag set when TS input is driven to ground; flag must be cleared to clear interrupt _1 Preliminary data sheet Rev February 29 1 of 77

11 AFT DRAF RAFT DRA Table 6. Register Control_2 (1h) bits description continued Bit Symbol Value Description Reference 4 AF [1] no alarm interrupt generated Section flag set when alarm triggered; flag must be cleared to clear interrupt 3 CDTF [1] no countdown timer interrupt generated Section flag set when countdown timer interrupt generated; flag must be cleared to clear interrupt 2 TSIE [1] no interrupt generated from timestamp flag Section interrupt generated when timestamp flag set 1 AIE [1] no interrupt generated from the alarm flag Section interrupt generated when alarm flag set CDTIE [1] no interrupt generated from countdown timer flag Section interrupt generated when countdown timer flag set [1] Default value Register Control_3 Table 7. [1] Values see Table 1. [2] Default value. Register Control_3 (2h) bits description Bit Symbol Value Description Reference 7 to 5 PWRMNG [1] control of the battery switch-over, battery low Section 8.4 detection and extra power fail detection functions 4 BTSE [2] no timestamp when battery switch-over occurs (default) Section time-stamped when battery switch-over occurs 3 BF [2] no battery switch-over interrupt generated Section flag set when battery switch-over occurs; flag must be cleared to clear interrupt 2 BLF [2] battery status ok; no battery low interrupt generated Section battery status low; flag cannot be cleared using the interface 1 BIE [2] no interrupt generated from the battery flag (BF) Section interrupt generated when BF is set BLIE [2] no interrupt generated from battery low flag (BLF) Section interrupt generated when BLF is set 8.3 Temperature compensated crystal oscillator The frequency of tuning fork quartz crystals oscillators are temperature-dependent. In the the frequency drift caused by temperature variation is corrected by adjusting the load capacitance of the crystal oscillator. _1 Preliminary data sheet Rev February of 77

12 AFT DRAF RAFT DRA The load capacitance is changed by switching between two load capacitance values using a modulation signal with a programmable duty cycle. Every chip is calibrated in order to produce, at the measured temperature, the correct duty cycle which compensates for the frequency shift. The frequency accuracy can be evaluated by measuring the frequency of the square wave signal available at the output pin CLKOUT. However, the selection of f CLKOUT = 32 khz (default value) leads to inaccurate measurements. The most accurate frequency measurement occurs when f CLKOUT = 1 Hz is selected (see Table 47) Temperature measurement The has a temperature sensor circuit used to perform the temperature compensation of the frequency. The temperature is measured immediately after power-on and then periodically with a period set by the temperature conversion rate TCR[1:] in the register CLKOUT_ctl (Fh). Table 8. TCR[1:] Bit 1 Bit [1] Default value. Temperature measurement period [1] 4min 1 2 min 1 1 min seconds Crystal aging correction Temperature measurement period The has an aging offset register Crystal_aging (19h) to correct the crystal aging effects. The accuracy of the frequency of a quartz crystal depends on the aging. Crystal suppliers usually specify the first year aging (typically ±1 ppm, maximum ±3 ppm) and/or the 1 years aging (typically ±5 ppm). The aging offset register adds an offset, positive or negative, in the temperature compensation circuits which allows to correct the aging effect. The change in ppm per AO[3:] value is different at different temperatures. At 25 C, the aging offset bits allow a frequency correction of typically 1 ppm per AO[3:] value, from 7 ppm to +8 ppm. Table 9. AO[3:] Frequency correction at 25 C, typical ppm Decimal Binary _1 Preliminary data sheet Rev February of 77

13 AFT DRAF Table 9. Frequency correction at 25 C, typical continued AO[3:] ppm Decimal Binary [1] RAFT DRA [1] Default value. 8.4 Power management functions The has two power supply pins and one power output pin: V DD - the main power supply input pin V BAT - the battery backup input pin BBS - battery backed output voltage pin (equal to the internal power supply) The has three power management functions implemented: Battery switch-over function Battery low detection function Extra power fail detection function The power management functions are controlled by the control bits PWRMNG[2:] in register Control_3 (2h): Table 1. PWRMNG[2:] Power management functions control bits Function Bit 2 Bit 1 Bit [1] battery switch-over function is enabled in standard mode, battery low detection function is enabled, extra power fail detection function is enabled 1 battery switch-over function is enabled in standard mode, battery low detection function is disabled, extra power fail detection function is enabled 1 battery switch-over function is enabled in standard mode, battery low detection function is disabled, extra power fail detection function is disabled 1 1 battery switch-over function is enabled in direct switching mode, battery low detection function is enabled, extra power fail detection function is enabled _1 Preliminary data sheet Rev February of 77

14 AFT DRAF Table 1. Power management functions control bits PWRMNG[2:] Function Bit 2 Bit 1 Bit RAFT DRA 1 battery switch-over function is enabled in direct switching mode, battery low detection function is disabled, extra power fail detection function is enabled 1 1 battery switch-over function is enabled in direct switching mode, battery low detection function is disabled, extra power fail detection function is disabled 1 1 [2] battery switch-over function is disabled - only one power supply (V DD ), battery low detection function is disabled, extra power fail detection function is enabled [2] battery switch-over function is disabled - only one power supply (V DD ), battery low detection function is disabled, extra power fail detection function is disabled [1] Default value. [2] When the battery switch-over function is disabled, the works only with the power supply V DD ; V BAT must be put to ground and the battery low detection function is disabled Battery switch-over function The has a backup battery switch-over circuit which monitors the main power supply V DD and automatically switches to the backup battery when a power failure condition is detected. One of two operation modes can be selected (see Section 8.4): Standard mode: the power failure condition happens when: V DD < V BAT AND V DD <V th(sw)bat (battery switch threshold voltage) Direct switching mode: the power failure condition happens when V DD < V BAT. Direct switching from V DD to V BAT without requiring V DD to drop below V th(sw)bat When a power failure condition occurs and the power supply switches to the battery the following sequence occurs: 1. The battery switch flag BF is set to logic An interrupt is generated if the control bit BIE is enabled (see Section ). 3. If the control bit BTSE is set to logic 1, the timestamp registers store the time and date when the battery switch occurred (see Section ). 4. The battery switch flag BF is cleared via the interface; it must be cleared to clear the interrupt. The interface is disabled in battery backup operation: Interface inputs are not recognized, preventing extraneous data being written to the device Interface outputs are high-impedance _1 Preliminary data sheet Rev February of 77

15 AFT DRAF RAFT DRA The switching from the main power supply V DD to the backup battery V BAT causes the internal clock stopping just after the transistion and then recovering again. Typically after a transition from V DD = 3.3 V to V BAT = 3. V, the clock stops for about 1 ms. When the main power recovers and then the internal power switches from V BAT = 3. V to V DD = 3.3 V, the clock stops for further 1 ms Standard mode If V DD > V BAT OR V DD >V th(sw)bat the internal power supply is V DD. If V DD < V BAT AND V DD <V th(sw)bat the internal power supply is V BAT. V th(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. V DD backup battery operation V BBS V BBS V BAT internal power supply (= V BBS ) V th(sw)bat (= 2.5 V) V DD (= V) BF INT cleared via interface 1aaj311 Fig 5. Battery switch-over behavior in standard mode and with bit BIE set to logic 1 (enabled) _1 Preliminary data sheet Rev February of 77

16 AFT DRAF Direct switching mode If V DD > V BAT the internal power supply is V DD. If V DD < V BAT the internal power supply is V BAT. RAFT DRA The direct switching mode is useful in systems where V DD is higher than V BAT at all times (e.g. V DD = 5 V, V BAT = 3.5 V); the direct switching mode is not recommended if the V DD and V BAT values are similar (e.g. V DD = 3.3 V, V BAT 3. V). When the monitoring of V DD and V th(sw)bat is not performed, the power consumption is reduced compared to the standard mode. V DD backup battery operation V BBS V BBS V BAT internal power supply (= V BBS ) V th(sw)bat (= 2.5 V) V DD (= V) BF INT cleared via interface 1aaj312 Fig 6. Battery switch-over behavior in direct switching mode and with bit BIE set to logic 1 (enabled) Battery switch-over disabled: only one power supply (V DD ) When the battery switch-over function is disabled: The power supply is applied on the V DD pin The V BAT pin must be connected to ground The internal power supply, available at the output pin BBS, is equal to V DD The battery flag (BF) is always logic Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Figure 7. _1 Preliminary data sheet Rev February of 77

17 AFT DRAF RAFT DRA comparators logic switches V DD(int) V CC V th(sw)bat V DD V DD V DD(int) V th(sw)bat V BAT V CC LOGIC V BAT V BBS (internal power supply) 1aag61 V DD(int) Fig 7. Battery switch-over circuit, simplified block diagram The internal power supply (available on pin BBS) is equal to V DD or V BAT. It has to be assured that there are decoupling capacitors on the pins V DD, V BAT and BBS Battery backup supply The V BBS voltage on the output pin BBS is equal to the internal power supply and depends on the selected battery switch-over function mode: Table 11. Output pin BBS Battery switch-over function mode Conditions V BBS equals standard V DD > V BAT or V DD > V th(sw)bat V DD V DD < V BAT and V DD < V th(sw)bat V BAT direct switching V DD > V BAT V DD disabled V DD < V BAT only V DD available, V BAT must be put to ground V BAT V DD The output pin BBS can be used as a supply for battery backup devices such as SRAM (see Figure 55). For this case Figure 8 shows the typical driving capability when V BBS is driven from V DD. _1 Preliminary data sheet Rev February of 77

18 AFT DRAF RAFT DRA 1aaj327 V BBS V DD (mv) 2 V DD = 5 V 4 V DD = 3 V 6 V DD = 2 V I BBS (ma) Fig 8. Typical driving capability of V BBS : (V BBS V DD ) with respect to the output load current I BBS Battery low detection function The has a battery low detection circuit which monitors the status of the battery V BAT. When V BAT drops below the threshold value V th(bat)low (typically 2.5 V) a flag (BLF) is set to indicate that the battery is low and that it must be replaced. A low battery will not ensure data integrity during periods of backup battery operation. Monitoring of the battery voltage also occurs during battery operation. When V BAT drops below the threshold value V th(bat)low, the following sequence occurs (see Figure 9): 1. The battery low flag BLF is set to logic An interrupt is generated if the control bit BLIE is enabled (see Section ). 3. The flag BLF remains set to logic 1 until the battery is replaced. BLF cannot be cleared using the interface. It is cleared automatically by the battery low detection circuit when the battery is replaced. _1 Preliminary data sheet Rev February of 77

19 AFT DRAF RAFT DRA V DD = V BBS internal power supply (= V BBS ) V BAT V th(bat)low (= 2.5 V) V BAT BLF INT 1aaj322 Fig 9. Battery low detection behavior with bit BLIE set to logic 1 (enabled) Extra power fail detection function The has an extra power fail detection circuit which compares the voltage at the power fail input pin (PFI) to an internal reference voltage equal to 1.25 V. If V PFI < 1.25 V the power fail output PFO is driven LOW. PFO is an open-drain, active LOW output which requires an external pull-up resistor in any application. The extra power fail detection function is typically used as a low voltage detection for the main power supply V DD (see Figure 1). V DD 1.25 V (internal) R1 RPU PFI PFO R2 V SS 1aaj678 Fig 1. Typical application of the extra power fail detection function _1 Usually R1 and R2 should be chosen such that the voltage at pin PFI is higher than 1.25 V at start-up falls below 1.25 V when V DD falls below a desired threshold voltage, V th(uvp), defined by Equation 1: Preliminary data sheet Rev February of 77

20 AFT DRAF RAFT DRA R V 1 th( uvp) = R V (1) V th(uvp) value is usually set to a value that there are several milliseconds before V DD falls below the minimum operating voltage of the system, in order to allow the microcontroller to perform early backup operations. If the extra power fail detection function is not used, pin PFI must be connected to V SS and pin PFO left open Extra power fail detection when the battery switch over function is enabled When the power switches to the backup battery supply V BAT, the power fail comparator is switched off and the power fail output at pin PFO goes (or remains) LOW When the power switches back to the main V DD, the pin PFO is not driven LOW anymore and is pulled HIGH through the external pull-up resistance for a certain time (t rec = ms to ms) and then the power fail comparator is enabled again For illustration see Figure 11 and Figure 12. V DD V th(uvp) V BAT internal power supply (= V BBS ) V BBS V BBS V th(sw)bat (= 2.5 V) V DD (= V) comparator enabled comparator disabled comparator enabled PF t rec = [15.63 : 31.25] ms 1aaj319 Fig 11. PFO signal behavior when battery switch-over is enabled in standard mode and V th(uvp) >(V BAT,V th(sw)bat ) _1 Preliminary data sheet Rev February 29 2 of 77

21 AFT DRAF RAFT DRA V BAT V DD V BBS V internal power supply (= V BBS ) BBS V th(uvp) V th(sw)bat (= 2.5 V) V DD (= V) comparator enabled comparator disabled comparator enabled PF t rec 1aaj32 Fig 12. PFO signal behavior when battery switch-over is enabled in direct switching mode and V th(uvp) < V BAT Extra power fail detection when the battery switch-over function is disabled If the battery switch-over function is disabled and the power fail comparator is enabled, the power fail output at pin PFO depends only on the results of the comparison between V PFI and 1.25 V: If V PFI > 1.25 V, PFO = HIGH (through the external pull-up resistor) If V PFI < 1.25 V, PFO = LOW V DD V th(uvp) V th(sw)bat (= 2.5 V) comparator always enabled PF 1aaj321 Fig 13. PFO signal behavior when battery switch-over is disabled 8.5 General purpose 512 bytes static RAM The contains a general purpose 512 bytes static RAM. _1 Preliminary data sheet Rev February of 77

22 AFT DRAF Data is transferred to or from the RAM via the interface. RAFT DRA 9 bits, RA[8:], define the RAM address pointer in registers RAM_addr_MSB (1Ah) and RAM_addr_LSB (1Bh). The register address pointer increments after each read or write automatically up to 1Bh and then wraps around to address h (see Figure 4). To write to the RAM, the register RAM_wrt_cmd (1Ch), to read from the RAM the register RAM_rd_cmd (1Dh) must be addressed explicitly. 8.6 Oscillator stop detection function The has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag (OSF) is set to logic 1. Power-on: a. The oscillator is not running, the chip is in reset (pin RST = LOW and flag OSF = 1). b. When the oscillator starts running and is stable after power-on, the chip exits from reset (pin RST =HIGH). c. The flag OSF is still set to logic 1 and can be cleared (OSF = ) via the interface (see Section 8.7.1). Power supply failure: a. When the power supply of the chip (V DD or V BAT ) drops below a certain value, typically 1.2 V, the oscillator stops running and a reset occurs (pin RST =LOW). b. When the power supply returns to normal operation, the oscillator starts running again, the chip exits from reset (pin RST =HIGH). c. The flag OSF is still set to logic 1 and can be cleared (OSF = ) via the interface (see Section and Figure 14). _1 Preliminary data sheet Rev February of 77

23 AFT DRAF RAFT DRA V DD V DD V BBS V BAT V BBS V BBS V th(sw)bat (= 2.5 V) V low (= 1.2 V) V BBS battery discharge internal power supply V SS V BAT V SS RST (1) (2) OSF 1aaj323 Fig 14. (1) Theoretical state of the signals since there is no power. (2) The oscillator stop flag (OSF), set to logic 1, indicates that the oscillation has stopped and a reset has occurred since the flag was last cleared (OSF = ). In this case the integrity of the clock information is not guaranteed. The OSF flag is cleared using the interface. Power failure event due to battery discharge: reset occurs 8.7 Reset function The has an active low open-drain output reset pin (RST). The reset output is activated at Power-On Reset (POR) and whenever the oscillator is stopped (see Section 8.6) Power-on reset The POR is active whenever the oscillator is stopped. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance (see Figure 15). This time may be in the range of 2 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF = 1). chip in reset chip not in reset V DD oscillation RST t 1aaj325 Fig 15. Power-on reset _1 Preliminary data sheet Rev February of 77

24 AFT DRAF After power-on reset, the following mode is entered: khz CLKOUT active Power-on reset override available to be set 24 hour mode is selected Battery switch-over is enabled Battery low detection is enabled Extra power fail detection is enabled RAFT DRA The register values after power-on are shown in Table Power-on reset override The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. SCL SDA/CE OSCILLATOR RESET OVERRIDE CLEAR osc stopped = stopped, 1 = running reset = override inactive 1 = override active POR_OVRD = clear override mode 1 = override possible 1aaj324 Fig 16. Power-on reset system The setting of this mode requires that the POR_OVRD in register Control_1 (h) is set to logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 17. All timings shown are required minimums. SDA/CE power up 8 ms minimum 5 ns minimum 2 ns SCL reset override 1aaj326 Fig 17. POR override sequence, valid for both I 2 C-bus and SPI-bus Once the override mode is entered, the device is immediately released from the reset state and the set-up operation can commence. The override mode is cleared by writing a logic to POR_OVRD. POR_OVRD must be set to logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD to logic during normal operation has no effect except to prevent accidental entry into the POR override mode. _1 Preliminary data sheet Rev February of 77

25 AFT DRAF 8.8 Time and date function RAFT DRA The majority of these registers are coded in the Binary Coded Decimal (BCD) format. Table 12. Register Seconds (3h) bits description Bit Symbol Value Place value Description 7 OSF - clock integrity is guaranteed 1 [1] - clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 6to4 SECONDS to5 [2] ten s place actual seconds coded in BCD format 3to to9 [2] unit place [1] Start-up value. [2] Values shown in decimal. Table 13. Register Seconds in BCD format Seconds value in Upper-digit (ten s place) Digit (unit place) decimal Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit : : Table 14. Register Minutes (4h) bits description Bit Symbol Value Place value Description unused 6to4 MINUTES to5 [1] ten s place actual minutes coded in BCD format 3to to9 [1] unit place [1] Values shown in decimal. Table 15. Register Hours (5h) bits description Bit Symbol Value Place value Description 7 to unused 12 hour mode [1] 5 AMPM - indicates AM 1 - indicates PM 4 HOURS to 1 [2] ten s place actual hours coded in BCD format for 12 3to to9 [2] unit place hour mode _1 Preliminary data sheet Rev February of 77

26 AFT DRAF Table hour mode [1] Register Hours (5h) bits description Bit Symbol Value Place value Description RAFT DRA 5to4 HOURS to2 [2] ten s place actual hours coded in BCD format for 24 3to to9 [2] unit place hour mode [1] Hour mode is set by the bit 12_24 in register Control_1. [2] Values shown in decimal. Table 16. Register Days (6h) bits description Bit Symbol Value Place value Description 7 to unused 5to4 DAYS [1] to3 [2] ten s place actual day coded in BCD format 3to to9 [2] unit place [1] The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year. [2] Values shown in decimal. Table 17. Register Weekdays (7h) bits description Bit Symbol Value Description 7 to unused 2 to WEEKDAYS [1] to6 [2] actual weekday value, see Table 18 [1] These bits may be re-assigned by the user. [2] Values shown in decimal. Although the association of the weekdays counter to the actual weekday is arbitrary, the will assume Sunday is and Monday is 1 for the purposes of determining the increment for calendar weeks. Table 18. Day Weekday assignments Bit 2 1 Sunday Monday 1 Tuesday 1 Wednesday 1 1 Thursday 1 Friday 1 1 Saturday 1 1 Table 19. Register Months (8h) bits description Bit Symbol Value Place value Description 7 to unused 4 MONTHS to 1 [1] ten s place actual month coded in BCD format, see 3to to9 [1] unit place Table 2 _1 Preliminary data sheet Rev February of 77

27 AFT DRAF RAFT DRA [1] Values shown in decimal. Table 2. Month assignments in BCD format Month Upper-digit (ten s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit January 1 February 1 March 1 1 April 1 May 1 1 June 1 1 July August 1 September 1 1 October 1 November 1 1 December 1 1 Table 21. Register Years (9h) bits description Bit Symbol Value Place value Description 7 to 4 YEARS to 9 [1] ten s place actual year coded in BCD format 3to to9 [1] unit place [1] Values shown in decimal. Figure 18 describes the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS 1aaf91 Fig 18. Data flow for the time function _1 Preliminary data sheet Rev February of 77

28 AFT DRAF 8.9 Alarm function RAFT DRA When one or more of the alarm registers are loaded with a valid second, minute, hour, day or weekday and its corresponding alarm enable not bit (AEN_x) is logic, then that information is compared with the actual second, minute, hour, day and weekday (see Figure 19). check now signal MINUTE ALARM MINUTE TIME = MINUTE AEN example MINUTE AEN = 1 1 HOUR AEN HOUR ALARM = HOUR TIME DAY AEN set alarm flag, AF (1) DAY ALARM = DAY TIME WEEKDAY AEN WEEKDAY ALARM WEEKDAY TIME = 1aaf92 Fig 19. (1) Only when all enabled alarm settings are matching. Alarm function block diagram Generation of interrupts from the alarm function is described in Section Table 22. Register Second_alarm (Ah) bits description Bit Symbol Value Place value Description 7 AEN_S - second alarm is enabled 1 [1] - second alarm is disabled 6 to 4 SECOND_ALARM to 5 [2] ten s place second alarm information coded in BCD 3to to9 [2] unit place format [1] Default value. [2] Values shown in decimal. Table 23. [1] Default value. Register Minute_alarm (Bh) bits description Bit Symbol Value Place value Description 7 AEN_M - minute alarm is enabled 1 [1] - minute alarm is disabled 6 to 4 MINUTE_ALARM to 5 [2] ten s place minute alarm information coded in BCD 3to to9 [2] unit place format _1 Preliminary data sheet Rev February of 77

29 AFT DRAF RAFT DRA [2] Values shown in decimal. Table 24. Register Hour_alarm (Ch) bits description Bit Symbol Value Place value Description 7 AEN_H - hour alarm is enabled 1 [1] - hour alarm is disabled unused 12 hour mode 5 AMPM - indicates AM 1 - indicates PM 4 HOUR_ALARM to 1 [2] ten s place hour alarm information coded in BCD 3to to9 [2] unit place format when in 12 hour mode 24 hour mode 5 to 4 HOUR_ALARM to 2 [2] ten s place hour alarm information coded in BCD 3to to9 [2] unit place format when in 24 hour mode [1] Default value. [2] Values shown in decimal. Table 25. Register Day_alarm (Dh) bits description Bit Symbol Value Place value Description 7 AEN_D - day alarm is enabled 1 [1] - day alarm is disabled unused 5 to 4 DAY_ALARM to 3 [2] ten s place day alarm information coded in BCD 3to to9 [2] unit place format [1] Default value. [2] Values shown in decimal. Table 26. Register Weekday_alarm (Eh) bits description Bit Symbol Value Description 7 AEN_W weekday alarm is enabled 1 [1] weekday alarm is disabled 6 to unused 2 to WEEKDAY_ALARM to 6 [2] weekday alarm information [1] Default value. [2] Values shown in decimal Alarm flag When all enabled comparisons first match, the alarm flag AF is set. AF will remain set until cleared by using the interface. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. For clearing the flags see Section Alarm registers which have their bit AEN_x at logic 1 are ignored. _1 Preliminary data sheet Rev February of 77

30 AFT DRAF RAFT DRA minutes counter minute alarm 45 AF INT when AIE_M = 1 1aaj341 Fig 2. Example where only the minute alarm is used and no other interrupts are enabled. AF timing 8.1 Timer functions The has two different timer functions, a watchdog timer and a countdown timer. The timers can be selected by using the control bits WD_CD[1:] in the register Watchdg_tim_ctl (1h). The watchdog timer has four selectable source clocks. It can be used to detect a microprocessor with interrupt and reset capability which is out of control (see Section 8.1.1) The countdown timer has four selectable source clocks allowing for countdown periods from less than 1 ms to more than 4 hours (see Section 8.1.2) To control the timer functions and timer output, the registers Control_2 (1h), Watchdg_tim_ctl (1h) and Watchdg_tim_val (11h) are used. Table 27. Register Watchdg_tim_ctl (1h) bits description Bit Symbol Value Description 7 to 6 WD_CD[1:] [1] watchdog timer disabled; countdown timer disabled 1 watchdog timer disabled; countdown timer enabled if CDTIE is set to logic 1, the interrupt pin INT is activated when the countdown timed out 1 watchdog timer enabled; the interrupt pin INT is activated when timed out; countdown timer not available 1 1 watchdog timer enabled; the reset pin RST is activated when timed out; countdown timer not available 5 TI_TP [1] the interrupt pin INT is configured to generate a permanent active signal when MSF and/or CDTF is set 1 the interrupt pin INT is configured to generate a pulsed signal when MSF flag and/or CDTF flag is set (see Figure 24) _1 Preliminary data sheet Rev February 29 3 of 77

31 AFT DRAF Table 27. Register Watchdg_tim_ctl (1h) bits description continued Bit Symbol Value Description 4 to 2 - unused RAFT DRA 1 to TF[1:] timer source clock for watchdog and countdown timer 4.96 khz 1 64 Hz 1 1 Hz 1 1 [1] 1 6 Hz [1] Default value. Table 28. Register Watchdg_tim_val (11h) bits description Bit Symbol Value Description 7 to WATCHDG_TIM_VAL to FF watchdog or countdown timer period, n = to 255 n timer period = SourceClockFrequency Table 29. TF[1:] Programmable watchdog or countdown timer Timer source Units Minimum timer clock frequency period (n = 1) Watchdog timer function The watchdog timer function is controlled by the WD_CD[1:] bits of the register Watchdg_tim_ctl (1h) (see Table 27). The two bits TF[1:] in register Watchdg_tim_ctl (1h) determine one of the four source clock frequencies for the watchdog timer: 4.96 khz, 64 Hz, 1 Hz or 1 6 Hz (see Table 29). When the watchdog timer function is enabled, the 8 bit timer in register Watchdg_tim_val (11h) determines the watchdog timer period. The watchdog timer counts down from the software programmed 8 bit binary value n in register Watchdg_tim_val (11h). When the counter reaches 1 the watchdog timer flag WDTF is set to logic 1. In that case (WDTF = 1): if WD_CD[1:] = 1 an interrupt will be generated if WD_CD[1:] = 11 a reset will be generated The counter does not automatically reload. When WD_CD[1:] = 1 or WD_CD[1:] = 11 and the microcontroller unit (MCU) loads a watchdog timer value n: the flag WDTF is reset Units Maximum timer period (n = 255) 4.96 khz 244 μs ms 1 64 Hz ms s 1 1 Hz 1 s 255 s Hz 6 s 153 s Units _1 Preliminary data sheet Rev February of 77

32 AFT DRAF INT or RST is cleared the watchdog timer starts again Loading the counter with will: reset the flag WDTF clear INT or RST stop the watchdog timer RAFT DRA WDTF is read only. A read of the register Control_2 (1h) will automatically reset the flag WDTF. MCU watchdog timer value n = 1 n WDTF INT 1aag62 Fig 21. Counter reached 1, WDTF is set to logic 1, an interrupt is generated. WD_CD[1:] = 1: watchdog activates an interrupt when timed out MCU watchdog timer value n = 1 n WDTF RST t w(rst) 1aag63 Fig 22. Counter reached 1, WDTF is set to logic 1, reset pulse on the RST pin is generated for a time equal to t w(rst). WD_CD[1:] = 11: watchdog activates a reset pulse when timed out _1 Preliminary data sheet Rev February of 77

33 AFT DRAF RAFT DRA Table 3. Specification of t w(rst) WD_CD[1:] TF[1:] t w(rst) μs ms ms ms Countdown timer function The countdown timer function is controlled by the WD_CD[1:] bits in register Watchdg_tim_ctl (1h) (see Table 27). The timer counts down from the software programmed 8 bit binary value n in register Watchdg_tim_val (11h). When the counter reaches 1: the countdown timer flag CDTF is set the counter automatically reloads starts the next time period Loading the counter with effectively stops the timer. Reading the timer will return the actual value of the countdown counter. countdown value, n XX 3 timer source clock countdown counter XX WD/CD [1:] 1 CDTF INT n n duration of first timer period after enable may range from n 1 to n+1 1aaf71 Fig 23. In this example it is assumed that the countdown timer flag (CDTF) is cleared before the next countdown period expires and that INT is set to pulsed mode. General countdown timer behavior If a new value of n is written before the end of the actual timer period, this value will take immediate effect. It is not recommended to change n without first disabling the counter by setting WD_CD[1:] =. The update of n is asynchronous to the timer clock. Therefore changing it on the fly could result in a corrupted value loaded into the countdown counter. This can result in an undetermined countdown period for the first period. The countdown value n will, however, be correctly stored and correctly loaded on subsequent timer periods. _1 Preliminary data sheet Rev February of 77

34 AFT DRAF RAFT DRA When the countdown timer flag CDTF is set, an interrupt signal on INT will be generated provided that this mode is enabled. See Section for details on how the interrupt can be controlled. When starting the countdown timer for the first time, only the first period will not have a fixed duration. The amount of inaccuracy for the first timer period will depend on the chosen source clock, see Table 31. Table 31. First period delay for timer counter Timer source clock Minimum timer period Maximum timer period 4.96 khz n n Hz n n Hz (n 1) Hz n Hz 1 6 Hz (n 1) Hz n Hz At the end of every countdown, the timer sets the countdown timer flag (CDTF). CDTF may only be cleared by software. The asserted CDTF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF[1:]. CDTIE is used to control this mode selection. The interrupt output may be disabled with the CDTIE bit, see Table 6. When reading the timer, the actual countdown value is returned and not the initial value n. For accurate read back of the countdown value, the SPI-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results Pre-defined timers: second and minute interrupt has two pre-defined timers which are used to generate an interrupt either once per second or once per minute. The pulse generator for the minute or second interrupt operates from an internal 64 Hz clock. It is independent of the watchdog or countdown timers Timer flags When the watchdog timer counter reaches 1, the watchdog timer flag WDTF is set to logic 1 When the countdown timer counter reaches 1, the countdown timer flag CDTF is set to logic 1 When a minute or second interrupt occurs, the minute/second flag MSF is set to logic 1 (see Section ) The watchdog timer flag WDTF is read only and cannot be cleared with the interface. WDTF can be cleared by loading a value in register Watchdg_tim_val (11h) reading of the register Control_2 (1h) Writing a logic or logic 1 to WDTF has no effect. _1 Preliminary data sheet Rev February of 77

35 AFT DRAF RAFT DRA The flags MSF, CDTF, AF and TSFx can be cleared by using the interface. To prevent one flag being overwritten while clearing another, a logic AND is performed during the write access. Writing a logic 1 causes the flag to maintain it s value whilst writing a logic resets the flag. Four examples are given for clearing the flags. Clearing the flags is made by a write command, therefore bits labelled with - must be written with their previous values WDTF is read only and has to be written with a logic Repeatedly re-writing these bits has no influence on the functional behavior. Table 32. Flag location in Control_2 Register Bit Control_2 MSF WDTF TSF2 AF CDTF The following tables show what instruction must be sent to clear the appropriate flag. Table 33. Example to clear only CDTF (bit 3) [1] Register Bit Control_ [1] The bits labelled as - have to be rewritten with the previous values. The bit labelled as X is read only and has to be written with logic. Table 34. Example to clear only AF (bit 4) [1] Register Bit Control_ [1] The bits labelled as - have to be rewritten with the previous values. The bit labeled as X is read only and has to be written with logic. Table 35. Example to clear only MSF (bit 7) [1] Register Bit Control_ [1] The bits labelled as - have to be rewritten with the previous values. The bit labelled as X is read only and has to be written with logic. Table 36. Example to clear both CDTF and MSF [1] Register Bit Control_ [1] The bits labelled as - have to be rewritten with the previous values. The bit labeled as X is read only and has to be written with logic. _1 Preliminary data sheet Rev February of 77

36 AFT DRAF 8.11 Timestamp function RAFT DRA The has an active LOW timestamp input pin TS, internally pulled with an on-chip pull-up resistor to the internal power supply of the device. It also has a timestamp detection circuit which can detect two different events: 1. TS input on the pin is driven to an intermediate level between the power supply and ground. 2. TS input on the pin is driven to ground Timestamp flag 1. When the TS input pin is driven to an intermediate level between the power supply and ground the following sequence occurs: a. The actual date and time are stored in the timestamp registers. b. The timestamp flag TSF1 is set. c. If the TSIE bit is active, an interrupt on the INT pin is generated. The TSF1 flag can be cleared by using the interface. Clearing the flag will clear the interrupt. Once TSF1 is cleared it will only be set again when a new negative edge on TS is detected. 2. When the TS input pin is driven to ground the following sequence occurs: a. The actual date and time are stored in the timestamp registers. b. In addition to the TSF1 flag the TSF2 flag is set. c. If the TSIE bit is active, an interrupt on the INT pin is generated. The TSF1 and TSF2 flags can be cleared by using the interface; clearing both flags will clear the interrupt. Once TSF2 is cleared it will only be set again when TS is driven to ground once again Time stamp mode The timestamp function has two different modes selected by the control bit TSM (time stamp mode): If TSM = (default): in subsequent trigger events without clearing the timestamp flags, the last timestamp event is stored If TSM = 1: in subsequent trigger events without clearing the timestamp flags, the first timestamp event is stored The timestamp function also depends on the control bit BTSE (battery switch timestamp enable) in register Control_3 (2h), see Section Timestamp registers Table 37. Register Timestp_ctl (12h) bits description Bit Symbol Value Description 7 TSM [1] in subsequent events without clearing the timestamp flags, the last event is stored (default) 1 in subsequent events without clearing the timestamp flags, the first event is stored _1 Preliminary data sheet Rev February of 77