Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing Machine

Transcription

1 Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing Machine W. Bruce Puckett Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Masters of Science in Electrical and Computer Engineering Dr. Brian Woerner, Chair Dr. Peter Athanas Dr. William Tranter July 7, 2000 Blacksburg, Virginia Keywords: Turbo Codes, FPGA, Wildforce, SLAAC1V Copyright 2000, W. Bruce Puckett

2 Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing Machine W. Bruce Puckett (ABSTRACT) Turbo codes are a recently discovered class of error correction codes that achieve near-shannon limit performance. Because of their complexity and highly parallel nature, turbo coded applications are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis presents the implementation and performance of an improved turbo decoder on a configurable computing platform. The design s performance and throughput are emphasized in light of its algorithmic improvements, and its flexibility is emphasized as it is ported to a newer, more efficient architecture with more hardware resources. Because this decoder will eventually become the error correction component of a software radio, the design must maintain a high data rate, interface easily with other modules, and conserve hardware resources for future research developments.

3 Acknowledgements There were many factors that led me to choose Virginia Tech for my graduate studies. I would like to begin by thanking my advisor and teacher, Dr. Brian Woerner. I have enjoyed working with him, and I have learned a great deal from him. I truly appreciate all the opportunities he has made available to me. His relationships with his students was one of the factors that made me want to come to Tech and work for him. I also wish to extend my thanks to all the students at the Mobile and Portable Radio Research Group (MPRG). Their camaraderie and friendliness initially attracted me, and their dedication and talent never failed to impress me. They were an important factor in my decision as well. To the first six students who read my thesis, I bequeath a single zero from my six-figure salary. I also want to thank all the MPRG staff; they work behind the scenes to keep it all rolling smoothly. I want to say a special thank you to the Via family for the Bradley Fellowship. Not only was it a direct answer to prayer, but it also provided me the freedom to pursue the research topic of my choice. Their provision allowed me to travel and get a good education for free, and I cannot thank them enough. I would also like to say thanks to my other committee members, Dr. Peter Athanas and Dr. William Tranter. I m grateful not only for the expertise and insight that Dr. Athanas was able to provide during my research, but also for his helpfulness and patience as I came up to speed on a topic that I had no experience in. Dr. Tranter helped teach two of the most enjoyable classes I had at Tech, and his many stories always added extra flavor to the material at hand. iii

4 In particular, I also want to extend my thanks to Yufei Wu and Greg Durgin. Yufei s help was invaluable to this project, and I could never have finished it without her. Greg s support, insight, and friendship were priceless. Thanks, buddy. To my parents, thank you for your support and for always being there through the years. Your wisdom and prayers have helped me when the going has been tough. Finally, I have to thank my Lord, Jesus Christ. Words can only fail to express my awe and thankfulness for the blessings you have poured out on me and for your continual friendship and faithfulness. iv

5 Contents 1 Introduction HistoryofWireless HistoryofCoding TurboCodes Practical Implementation Challenges of Turbo Codes PurposeandOverviewofThesis Turbo Codes HistoricalDevelopmentofTurboCodes ClassificationofConcatenatedCodes EncodingOperation RSCEncoding Interleavers DecodingOperation StructureofIterativeDecoding DecodingAlgorithms PerformanceExamples Summary Configurable Computing Field-ProgrammableGateArrays(FPGAs) v

6 3.1.1 TheVirtexArchitecture Run-time Reconfiguration (RTR) FPGAPlatform CCMDesignMethodology Summary FPGA Implementation of Turbo Codes ImplementationGoals OverallArchitecture Hardware Implementation and VHDLModelDescription TopLevelController InterleaverModule AdderModule DecoderModule HostCode PortingtotheSLAAC1VArchitecture AlgorithmicDevelopments SimplifiedSISOModule Log-MAPAlgorithm ModularRenormalization SDRStoppingCriteria SoftwareRadioModule Summary Performance Results TestSetup PerformanceVerification WildForce Throughput Peformance vi

7 5.2.2 SLAAC1V Throughput Peformance Functional Correctness of the Improved Decoder Summary Conclusions SummaryofWork FutureWork A List of Variables 81 B List of Acronyms 84 C Finite State Machines for Wildforce Modules 88 vii

8 List of Figures 1.1 Iterativedecoding Encoder structures for (a) PCCCs and (b) SCCCs A constraint-length 3, RSC encoder with generator matrix G =[7, 5] octal Aperformancecomparisonofdifferentinterleaverdesigns Conventionalturbodecoder Trellis-based decoding algorithms BER vs. E b /N o comparison for turbo codes of different frame sizes BER vs. E b /N o comparison for turbo codes with different decoding iterations A2-sliceVirtex-ECLB[1] AsingleVirtex-Eslice[1] OverviewoftheVirtex-Earchitecture[1] Overview of the Stallion architecture SLAAC1Varchitecture[2] SLAAC1Vmemoryarchitecture[2] SLAAC1V external memory timing diagram [3] DesignmethodologyforaturbodecoderonaCCM Turbo decoder using a simplified SISO decoding structure and enhanced Log- MAPalgorithm Topleveldiagramoftheturbodecoder Finite state machine of the top level controller for the SLAAC1V CCM viii

9 4.4 Finite state machine for the SLAAC1V interleaver module FinitestatemachinefortheSLAAC1Vaddermodule Finite state machine for the SLAAC1V decoder module Improved decoding structure using a simplified SISO decoding module Illustration of the two s complement wheel for n = Proper initialization for α k (s) andβ k (s) when modular renormalization is used Trellis structure for a G =[7, 5] octal, constraint-length 3, RSC encoder Decision regions shift to follow the moving center point Throughput savings achieved by using the simplified SISO decoding structure Throughput savings achieved by using the simplified SISO decoding structure Peformance comparision of the original design, the improved design, and simulatedresults Average number of decoding iterations per frame for the original and improved designs as E b /N o isvaried Peformance comparision of the improved design and simulated results for 256- bitframes Average number of decoding iterations per 256-bit frame for the software version and the improved design as E b /N o isvaried Peformance comparision of the improved design and simulated results for 4096-bit frames Average number of decoding iterations per 4096-bit frame for the software version and the improved design as E b /N o isvaried Performance comparison for the improved design when the frame size is varied Average number of decoding iterations for different frame sizes as E b /N o is varied Demonstration of diminishing returns for the improved hardware design Hardware performance comparison for rate 1 and rate 1 turbo codes ix

10 C.1 Finite state machine of the top level controller for the Wildforce CCM C.2 Finite state machine for the Wildforce interleaver module C.3 FinitestatemachinefortheWildforceaddermodule C.4 Finite state machine for the Wildforce decoder module x

11 List of Tables 4.1 Parametersfortheimprovedturbodecoder Memorylocationsfortheimprovedturbodecoder Resource utilization for the turbo decoder of the Wildforce CCM Timing information for the turbo decoder of the Wildforce CCM xi

12 Chapter 1 Introduction The past ten years has seen explosive growth in the mobile radio communications industry, and this trend is expected to continue. Improved very large scale integrated (VLSI) circuit fabrication has reduced the cost, size, and power constraints of radio frequency circuits. New developments in digital signal processing (DSP) techniques, spread-spectrum systems, smart antennas, and error correction coding have also fueled the wireless revolution. In order to fully appreciate the significance that mobile and personal communications will have in our lives, this chapter begins with a brief overview of the history of wireless communications. 1.1 History of Wireless Although the age of mobile radio had its beginnings in 1897 when Marconi developed the first wireless telegraph, amplitude modulation (AM) did not see widespread use for mobile communications until police stations around the United States adopted it in the 1920 s. Frequency modulation (FM) became the de facto modulation technique for mobile communications soon after Edwin Armstrong demonstrated its use in The advent of World War II also helped usher in the age of mobile communications because many of the improvements made in RF technology during this time found their way into consumer markets shortly thereafter. 1

13 W. Bruce Puckett Chapter 1. Introduction 2 An important milestone in wireless communications was reached in 1946 with the introduction of the mobile radio telephone. Previously, wireless communication systems had been unconnected to the public switched telephone network (PSTN), but now the mobile user had access to commercial landline systems. Each market for the radiotelephone system was serviced by a tall radio tower and a single, high-powered transmitter, and users were limited to half-duplex FM communications (i.e., only one user could talk at a time). The 1960 s saw the first widespread public embracement of wireless communications with the designation of citizen band (CB) spectrum. New automatic trunking techniques and fullduplex communications were also developed at this time, but these improvements were soon overwhelmed by the sheer demand for mobile communications. By 1976 the entire city of New York, a market of nearly 10 million people, was being serviced by only 12 mobile radio channels. The waiting list for the service was nearly four thousand strong, yet the Bell Mobile Phone system could only accommodate 543 paying customers [4]. In response to the growing demand for wireless communications, Bell Laboratories began developing the concept of cellular communications during the 1960 s. The cellular concept was a groundbreaking solution to the problems of limited frequency spectrum and user capacity. This concept divides a large market into a series of smaller cells, each of which provides service to only a small portion of the market. Only a portion of the total frequency channels are assigned to each base station within a cell, and neighboring base stations have different sets of frequency channels. Cellular communications are interference limited systems, so this technique attempts to minimize interference while maximizing capacity. Thus, the cellular concept lends itself to frequency reuse. Frequency channels can be reused within a market, so long as the co-channel interference is kept below acceptable limits [4]. Practical implementation of the cellular concept, however, was not feasible until the late 1970 s. Nippon Telephone and Telegraph Company, a Japanese firm, established the world s first analog cellular system in This system allocated 30 MHz of spectrum for 600 full-duplex channels. Europe was not far behind in developing an analog system. In 1981 the Nordic Mobile Telephone system (NMT 450) was deployed, and then four years

14 W. Bruce Puckett Chapter 1. Introduction 3 later the European Total Access Cellular System (ETACS) was introduced. When 40 MHz of frequency spectrum in the 800 MHz band was allocated by the Federal Communications Commission, the Advanced Mobile Phone System (AMPS) was introduced by Ameritech in Chicago, IL, in AMPS had 666 duplex channels, and each duplex channel occupied 60 KHz of spectrum. Despite their success, these first generation analog systems suffered from incompatibility and capacity limitations [4]. The early 1990 s saw digital communications supplanting analog technologies. Digital communications offer many practical and economic advantages over analog techniques. Continued improvements in VLSI design helped pave the way for digital communications. Advanced multiple-access techniques such as time-division multiple-access (TDMA) and codedivision multiple-access (CDMA) can only be realized using digital communications. Digital communication systems also support greater user capacities by employing advanced source coding techniques which use the available spectrum more efficiently. Low cost digital speech encoders have also made digital wireless communications more feasible. Lastly, error correction is only possible with digital communications. The additional resistance to interference and the decreased power requirements, which are a result of the error correction coding gain, make digital communication systems more attractive than their analog predecessors. The first digital cellular system was deployed in Europe in The Global System for Mobile communications (GSM) was developed by the Conference Europeenne des Postes et Telecommunications (CEPT) to meet the demand of more users and to ensure compatibility across national boundaries. Unlike the United States, Europe had previously suffered the effects of many incompatible standards. Germany and Portugal used C-450, while France had deployed Radiocom 2000; Italy employed Radio Telephone Mobile System (RMTS). Because of the variety of standards throughout Europe, new spectrum was set aside for the GSM system around the 900 MHz band. GSM experienced enormous success after its deployment because it provided better service, increased roaming capability, and the ability to transmit data [5]. Cellular standards in United States, however, matured in a slightly different way.

15 W. Bruce Puckett Chapter 1. Introduction 4 Because AMPS was the only US standard, new bandwidth was not set aside for emerging standards. New standards, based on digital technologies, were forced to be backwardscompatible with the existing AMPS standard. Therefore, these emerging standards had to operate in dual-mode, providing for both analog and digital operation. A second generation analog system, known as Narrowband AMPS (NAMPS), was essentially equivalent to AMPS except the bandwidth for each user in the system was reduced by a factor of three to only 10 KHz. Second generation digital systems were classified according to the multiple-access technique they employed. Digital systems using TDMA technology multiplexed several users at the same frequency. Digital systems employing CDMA technology took a different approach. Each user in the system was given a unique spreading code which was approximately orthogonal to all other user codes. Each user s signal was then modulated with this high bandwidth spreading code before transmission. All users in the system occupy the same frequency band at the same time. Individual signals can be demodulated at the receiver because of the orthogonality or low cross-correlation of the individual spreading codes [6]. Wireless personal communications take many forms, but cellular systems have clearly been the fast growing segment of the mobile telecommunications market. To meet the growing demand, new spectrum has been allocated in the 1.9 GHz band for personal communication systems (PCS). PCS standards generally fall into two categories: high-tier systems supporting many high-speed mobile users in large cells, and low-tier systems which are designed for low speed, low power, and low complexity mobile users residing in microcells. PCS offers consumers more services than traditional cellular systems, yet the technologies employed in PCS are very similar to those of existing second generation systems [4] [6]. The new millennium is witnessing the birth of truly personal mobile communications with the introduction third generation systems. In an effort to provide compatible, worldwide telecommunications in the 21 st century, the International Telecommunications Union (ITU) has worked with standards committees in Europe, Korea, Japan, and the United States to implement International Mobile Telecommunications by the year 2000 (IMT-2000). All four have proposed a standard based on CDMA technology. Europe, Korea, and Japan have

16 W. Bruce Puckett Chapter 1. Introduction 5 embraced Wideband CDMA (W-CDMA), which is backwards-compatible with GSM, while some US manufacturers have proposed CDMA2000, which is backwards-compatible with IS- 95 [6]. Recently, the Third Generation Partnership Project (3GPP) accepted a harmonized standard for W-CDMA, which supports three modes of operation: a direct-sequence (DS) CDMA mode, a multicarrier CDMA mode, and a time-division duplex (TDD) CDMA mode. 1.2 History of Coding Unlike analog communications, digital communications possess the ability to detect and correct errors introduced by the channel. Forward error correction plays an important role in the system design process which attempts to balance the tradeoffs of power, bandwidth, and data reliability. The realm of coding theory is a rich and interesting field. A major pioneer and the father of modern information theory was Claude Shannon. Shannon s major accomplishments include the development of the noiseless source coding theorem, the ratedistortion theorem, and, of particular interest to this paper, the channel coding theorem. In 1948 Shannon published a groundbreaking paper which showed the maximum, theoretical data rate for which reliable communications could take place [7]. Shannon showed for an additive white Gaussian noise (AWGN) channel that the probability of error can be made vanishingly small, provided the date rate is less than or equal to the channel capacity. This proof used randomly generated codewords and sub-optimal jointly-typical decoding. Using this method, Shannon was able to show that the decoding regions for distinct codewords overlap only in a negligible number of places. Unfortunately, Shannon s proof does not tell us how to construct codes which will achieve channel capacity. Because of their lack of structure, random codes are notoriously difficult to decode. Adding structure to a code greatly simplifies the decoding process, but structured codes perform poorly compared to the theoretical limit. This is the basis of the coding theory paradox: All codes are good...except those we can think of. J. Wolfowitz

17 W. Bruce Puckett Chapter 1. Introduction Turbo Codes The focus of coding theory since Shannon s initial work has been to find a constructive way to place 2 k codewords in an n-dimensional space without overlapping the decoding spheres. Thecoderater is defined as the ratio of k, the number of information symbols transmitted per codeword, to n, the total number of symbols transmitted per codeword. For example, the (7, 4) Hamming code contains 2 4 codewords with 7 symbols and has a rate equal to 4. 7 This code, the first error correcting code, was able to correct a single error in a block of seven encoded bits. Other attempts to solve the problem presented by coding theory have included block codes (such as Golay, BCH, and Reed-Solomon codes) and convolutional codes, but prior to the early 1990 s, no practical techniques achieved the full promise of Shannon s predictions. Turbo codes are an unique approach to the old coding problem. Turbo codes are able to integrate structured codes in a pseudo-random manner which very nearly achieves Shannon s capacity limit; this constitutes a significant increase in power efficiency compared to previous block and convolutional coding schemes. The original turbo code employed two recursive systematic convolutional (RSC) encoders concatenated in parallel and separated by a pseudo-random interleaver [8]. Each rate 1 RSC encoder produces a set of systematic 2 and parity bits. The systematic bits are identical to the input bits; the parity bits are determined from the input bits, the state of the encoder, and the generator matrix. Because transmitting two sets of systematic bits is redundant, the interleaved systematic bits from the second RSC encoder are punctured, or removed, before transmission. The overall rate of the turbo code can be increased from 1 to 1 by alternately puncturing the parity bits from 3 2 each of the constituent encoders. The resulting code has a complex structure and appears quite random. This characteristic of the code results in good performance, particularly at low signal-to-noise ratios (SNRs). The overall code, however, is broken down into its constituent parts at each decoder, and each constituent code can be decoded relatively easily because of its inherent structure. Each decoder operates on the systematic and parity bits associated with its constituent encoder and produces soft outputs of the original data bits in the form of a posteriori probabilities (APPs). The decoders then share their respective soft information

18 W. Bruce Puckett Chapter 1. Introduction 7 Deinterleaver Systematic data Parity data A Priori Information DEMUX Decoder #1 APP Interleaver A Priori Information Decoder #2 APP Hard Bit Decisions Interleaver Figure 1.1: Iterative decoding in an iterative fashion. This principle is illustrated in Figure 1.1. The output of each decoder is interleaved (or deinterleaved) and passed to the next decoding module as its a priori information. Decoding continues in an iterative fashion for a fixed number of iterations or until a given convergence criteria is met. Because iterative decoding is subject to diminishing returns, the coding gains realized with each additional iteration are less than for the previous iteration. Although turbo codes integrate the two desirable qualities of pseudo-randomness and ease of decoding, the important contribution to communication theory lies in the iterative decoding method used to decode them. This iterative strategy has been employed in other communications areas such as iterative multiuser detection, turbo equalization, and turbo code assisted synchronization with good results. 1.4 Practical Implementation Challenges of Turbo Codes Despite their exceptional performance, practical implementations of turbo codes are just now being developed [9] [10]. Challenges which must be overcome before practical turbocoded systems are realized include computational complexity, power consumption, memory limitations, and fixed-point arithmetic. The complex turbo decoding operation is well-suited for configurable computing. Configurable computing machines (CCMs) offer a compromise

19 W. Bruce Puckett Chapter 1. Introduction 8 between the two extremes of custom-built application-specific integrated circuits (ASICs) and general-purpose digital signal processors. Field-programmable gate arrays (FPGAs), which are the main building block of CCMs, allow users to design customized hardware optimized for performance, speed, power consumption, and chip-area. Unlike ASICs, FPGAs can be easily redesigned by simply downloading a new hardware configuration. Although today s FPGAs have integrated internal memory, the memory requirements for turbo decoding exceed their present capacity. Because off-chip memory access time affects system performance, the turbo decoder must be designed to maintain a high data rate with minimal memory storage so as to not present a bottleneck to system performance. Also, quantization of the input and fixed-point arithmetic inevitably add noise to any system. Because the influence of these two factors can dramatically affect the bit error rate (BER) performance of a turbo code, choosing the correct number of quantization bits and scaling the received signal by a balanced scaling factor are important. 1.5 Purpose and Overview of Thesis Before the dramatic gains of turbo codes can be realized in practice, several challenges must be overcome. This thesis presents a practical implementation of a turbo-coded system on a CCM and demonstrates that a flexible, portable design optimized for performance, speed, power consumption, and chip-area can be realized in hardware. Because this turbo decoder will eventually become the error correction component of a reconfigurable software radio, several constraints are imposed so that the decoder will not present a bottleneck to the system [11]. This thesis is organized into six chapters. Chapter 2 presents the historical development of turbo codes and discusses the theoretical background necessary to understand their application. Several algorithms suitable for turbo decoding are discussed, and some performance factors which influence turbo-coded systems are explained and illustrated. Chapter 3 introduces the concept of configurable computing. The details of the spe-

20 W. Bruce Puckett Chapter 1. Introduction 9 cific architecture used for this implementation are described and then the design process is outlined. The hardware implementation, the algorithmic improvements, and the process of porting the design to a newer, more efficient architecture are discussed in Chapter 4. Chapter 5 describes the test verification setup, gives the implementation statistics of the design, and proves its functional correctness. Chapter 6 summarizes the work presented in this thesis, outlines its contributions, and discusses several ideas for improving the current design for future use in a reconfigurable software radio.

21 Chapter 2 Turbo Codes Although turbo codes are a new form of error correction, their foundation is rooted in coding theory. This chapter presents the development of turbo codes and discusses the theoretical background necessary to understand their application. The algorithms used to decode turbo codes are also described, and performance factors which influence turbo-coded systems are explained and illustrated. 2.1 Historical Development of Turbo Codes Although Shannon proved the theoretical limit at which error-free communications could take place using error-correcting codes, all previous coding schemes have fallen far short of this limit. In 1993 a group of French researchers devised a new class of error-correcting codes which achieved near-shannon limit performance [8]. Turbo codes were developed by C. Berrou and A. Glavieux at the Ecole Nationale Superieure des Telecommunications de Bretagne in Brest, France, as an exercise in VLSI design. 1 1 Ironically, the performance of the turbo-coded system was so exceptional that many coding theorists initially dismissed their results. In fact, their first paper was rejected. The paper was resubmitted and was nearly rejected again before a group of independent researchers verified the simulated BERperformance. The original paper was later awarded the 1997 Information Theory Society Paper Award by the IEEE s Information Theory Society when it was formalized and republished in

22 W. Bruce Puckett Chapter 2. Turbo Codes 11 The original turbo code was a parallel concatenated, rate 1, constraint-length 5 code 2 with generator matrices G =[27, 43] octal. A interleaver was used to interleave 65,536-bit data frames. The modified BAHL et al. algorithm was used for decoding. The original turbo code s performance came within 0.7 db of Shannon s theoretical limit after 18 decoding iterations [8] Classification of Concatenated Codes As previously mentioned, the original turbo code was a parallel concatenated convolutional code. Concatenated codes can be classified as either parallel concatenated convolutional codes (PCCCs), in which two encoders operate on the same information bits, or serial concatenated convolutional codes (SCCCs), in which one encoder encodes the output of another encoder. The term turbo code is often associated with PCCCs and will be used to refer to PCCCs throughout the rest of this thesis. PCCCs employ two or more recursive systematic convolutional (RSC) encoders joined in parallel by one or more pseudo-random interleavers. Systematic encoding is desirable for parallel concatenation because it allows easy puncturing of the systematic bits from the output stream of the second encoder. Feedforward implementations of systematic convolutional codes do not generally have good distance properties, but feedback or recursive implementations do. Thus, RSC encoders are generally used for turbo codes. Unlike conventional coding schemes which seek to increase the free distance of a code, turbo codes seek to decrease the multiplicity of low Hamming-weight codewords at the output of the encoders. Pseudo-random interleavers reduce the probability that both constituent encoders will simultaneously produce low weight parity sequences. This technique gives PCCCs their excellent performance despite the relatively small free distance of the constituent codes. Serial concatenated convolutional codes employ the same constituent components as PCCCs; the individual encoders, however, are connected serially by a pseudo-random interleaver. Figure 2.1 illustrates the encoder structures for PCCCs and SCCCs. The class of SCCCs was investigated by Forney in [12]. For a frame size N, the key feature of SCCCs

23 W. Bruce Puckett Chapter 2. Turbo Codes 12 d K Encoder 1 (a) Interleaver x K Encoder 2 (b) d K Outer Encoder Interleaver Inner Encoder x K Figure 2.1: Encoder structures for (a) PCCCs and (b) SCCCs is that, unlike PCCCs whose interleaver gain is fixed at N 1, the slope of the BER curve continues to decrease as a function of N 2, N 3, etc. Thus, SCCCs do not suffer from as shallow an error floor as PCCCs. Although the outer code for SCCCs need not be recursive, the inner code must be recursive in order to exploit the interleaver gain [13]. PCCCs are often chosen over SCCCs in practice because they are less computationally complex given the same constituent codes; they also have a lower BERs than SCCCs at low SNRs. 2.2 Encoding Operation RSC Encoding Turbo encoding employs two or more constituent recursive systematic convolutional (RSC) encoders separated by a pseudo-random interleaver. Although the encoders need not be identical, they often are in practice. An example of a constraint-length 3, RSC encoder with generator matrix G =[7, 5] octal is shown in Figure 2.2. The data bits d k are fed into the first encoder which generates a set of systematic and parity bits. The data bits are passed to the second encoder after being permuted by

24 W. Bruce Puckett Chapter 2. Turbo Codes 13 d K x S K D D x P K Figure 2.2: A constraint-length 3, RSC encoder with generator matrix G =[7, 5] octal a pseudo-random interleaver. The second encoder also generates a set of systematic and parity bits. Because sending two sets of systematic bits is redundant, the overall code is punctured by deleting the second set of systematic bits. The resulting bit stream consists of a systematic bit from the first encoder followed by the parity bits from the first and second encoders, respectively. This technique results in an overall code rate of 1. The code rate 3 can be increased to 1 by alternately puncturing the parity bits from each of the constituent 2 encoders before transmission. As the code rate increases, bandwidth efficiency improves; performance, however, is degraded since the decoder has less information to use in making a decision Interleavers Pseudo-Random Interleavers One of the fundamental components of turbo codes is the pseudo-random interleaver. This design technique generates an overall code which appears random but is actually composed of two or more structured codes. The random characteristics of the code result in good performance, yet the overall code is easily decoded at the receiver by breaking it down into its structured, constituent components. Choosing a good interleaver design is important for obtaining good turbo code performance, but the most significant parameter relating to the interleaver is its size. As the interleaver size increases, performance improves. There is a

25 W. Bruce Puckett Chapter 2. Turbo Codes 14 tradeoff, however, between performance and latency. Convolutional Interleavers There are a number of interleavers to choose from when designing PCCCs. Block interleavers tend to give poor performance because they do not adequately break apart certain input sequences which result in low weight codewords. Convolutional interleaving also results in an interleaving pattern where low weight codewords are likely to degrade performance. Simulation results have shown that convolutional interleaving between constituent RSC encoders yields poor performance for these reasons. A comparison of block, convolutional, and random interleaving is shown in Figure 2.3. A rate 1, constraint-length 4 turbo code with generator 3 matrices G =[13, 15] octal was used to encode 1,024-bit data frames. The Log-MAP algorithm was used for decoding, and plots are shown for six decoding iterations. Twenty-five errors were logged at each value of E b /N o. In general, when structure is introduced to the interleaver design, turbo code performance suffers. With a few exceptions, random interleavers provide good performance. Slightly improved performance can be obtained with a spread interleaver. A spread interleaver is a pseudo-random interleaver designed according to an algorithm which guarantees that consecutive input symbols are always separated by a specified distance in the output sequence. 2.3 Decoding Operation Structure of Iterative Decoding The truly unique aspect of turbo codes is their iterative decoding process. The iterative decoding structure consists of two soft-input, soft-output (SISO) decoding modules which are separated by a pseudo-random interleaver/deinterleaver. The term turbo code was coined because this iterative decoding process resembles the cyclic feedback mechanism of the turbo engine. A conventional turbo decoder is shown in Figure 2.4.

26 W. Bruce Puckett Chapter 2. Turbo Codes frame errors registered at each value of Eb/No frame size = 1024, 6 iterations, rate = 1/3, G=[15,17]octal Convolutional Interleaving Block Interleaving Random Interleaving Probability of Bit Error Parameters: 6 iterations 1024 Frame size Rate 1/3 G=[15,17] octal Log-MAP Eb/No in db Figure 2.3: A performance comparison of different interleaver designs The first decoder operates on the systematic channel observation, y (0) k, the parity channel observation from the first RSC encoder, y (1) k,andtheapriori information, z(1) k. The a priori information for SISO #1 is initially set to all zeros. This implies that each information bit is equally likely to be a 0 or a 1 initially. Both channel observations are multiplied by the channel reliability L c = 4aEs N o. The variable a is the fading amplitude, and Es N o is the SNR, where E s is the average symbol energy, and N o is the noise power spectral density. The channel reliability places more emphasis on the channel observation when the SNR is high and there is no fading. Likewise, more emphasis is placed on the a priori information z k when the SNR is poor or when there is a deep fade. The channel reliability must be estimated in practice, and correct estimation is essential for good turbo code performance [14] [15].

27 W. Bruce Puckett Chapter 2. Turbo Codes /2. L c. 1/2. L c. y (0) k y (1) k (1) z k 1/2. L c. 1/2. L c Interleave y (0) k. y (2) k Decoder #1 (2) Decoder #2 (1) k l (1) k z k (2) k l (2) k Deinterleave Make Decision Figure 2.4: Conventional turbo decoder The output of the SISO decoders is expressed as a log-likelihood ratio (LLR). A decoder s output at time k can be broken down into three distinct parts: the scaled systematic channel estimate 4aEs N o y (0) k k th LLR is expressed as,thea priori information z k, and the extrinsic information l k.the Λ k = 4aE s y (0) k + z k + l k. N o The extrinsic information is the new information generated by the current decoding operation. In a turbo decoder, the extrinsic information for the first decoder is determined by subtracting the systematic channel observation and the current stage s a priori information from the LLR Λ (1) k, thereby preventing positive feedback. The extrinsic information is then permuted by pseudo-random interleaver and used as the weighted a priori information for the second decoding module. The second decoding module operates on the weighted a priori information z (2) k, the permuted channel observation ỹ(0) k, and the parity channel observation from the second RSC encoder y (2) k to generate a new LLR, Λ (2) k. This completes one decoding iteration. If more decoding iterations are required, the extrinsic information from SIS0 #2 is calculated by subtracting the permuted systematic channel observation ỹ (0) k and the a priori information z (2) k from the LLR Λ (2) k. The extrinsic information is then deinterleaved and used as the a priori information z (1) k for the first decoding module in the next decoding iteration.

28 W. Bruce Puckett Chapter 2. Turbo Codes 17 If all the decoding iterations have been completed, the final output Λ (2) k hard-limited to produce the final decision. is deinterleaved and In practice the procedure of subtracting the systematic information is not explicitly necessary since it is just reintroduced at the input to the second decoder in permuted form. This thesis will later describe an improved SISO decoding structure which computes the extrinsic information, Λ k = ˆl k, directly at the output of the decoder. Because the output of the decoder is equivalent to the extrinsic information, it can be interleaved and passed directly to the next decoding module without the need to manually subtract the a priori and systematic information Decoding Algorithms Having outlined the iterative decoding process, the specific decoding algorithms used by the SISO modules will now be described. This section highlights two classes of trellis-based algorithms which are typically used to decode turbo codes, but emphasis is placed on the Log-MAP algorithm. Figure 2.5 lists the two classes of trellis-based algorithms and their derivatives in order to characterize their relationships to one another. The Viterbi algorithm (VA) accepts soft inputs but produces hard outputs. Although the maximum a posteriori (MAP) algorithm accepts soft inputs and produces soft outputs, it suffers from numerical instability. Their derivatives, which are shown below the dotted line, accept soft inputs and produce soft outputs; these algorithms, therefore, are suitable for use in turbo decoding applications. SISO algorithms are necessary for turbo decoding because the decoders are required to share their extrinsic information with each other. Although SISO decoding algorithms are more computationally complex, they allow iterative sharing of results between decoders, which permits the use of powerful concatenated coding structures. SOVA, Improved SOVA In 1967 the VA was presented in [16] as a practical procedure for maximum-likelihood decoding of convolutional codes. The VA is optimal for estimating the state sequence of a

29 W. Bruce Puckett Chapter 2. Turbo Codes 18 Trellis-Based Estimation Algorithms Viterbi Algorithm MAP Algorithm SOVA Max-Log-MAP Improved SOVA Sequence Estimation Algorithms Log-MAP Symbol-by-Symbol Estimation Algorithms Figure 2.5: Trellis-based decoding algorithms finite-state Markov process observed over a discrete memoryless channel (DMC) [17]. The VA minimizes the frame error rate by finding the most likely, connected path through the trellis. The VA is unsuitable for turbo decoding because it is a soft-input, hard-output algorithm. A soft-output VA (SOVA), introduced by Hagenauer and Hoeher in [18], is a SISO algorithm which retains information related to the pruned, competing paths. This information determines the reliability of the bits which differ from those in the surviving path. Although SOVA is more computationally complex than the standard VA, the gains realized from the soft-output decisions more than compensate for the additional complexity. In 1996 the Improved SOVA was developed in [19] to combat an inherent bias with SOVA. The bias is removed by multiplying the SOVA output by a normalizing constant derived from the estimated mean and variance of the output. A small performance increase mitigates the slight increase in computational complexity.

30 W. Bruce Puckett Chapter 2. Turbo Codes 19 MAP Based on an algorithm developed by Chang and Hancock for removing intersymbol interference, the MAP algorithm was introduced in 1974 as an optimal means for estimating the a posteriori probabilities (APPs) for a finite-state Markov process observed over a DMC [20]. The MAP algorithm, also known as the BCJR algorithm for the four researchers who developed it, is a forward-backwards recursion algorithm which minimizes the probability of bit error. Therefore, the path that the MAP algorithm traces through the trellis need not be connected, as is the case for the VA. Unfortunately, a direct implementation of the MAP algorithm suffers from numerical instability. In the 1970 s the MAP algorithm fell out of favor for decoding convolutional codes because it was less stable and more complex than the VA. When SISO decoding of turbo codes became an important issue, the Max-Log-MAP and Log-MAP algorithms were introduced to solve the instability problem; they are now the preferred SISO algorithms used to decode turbo codes. The MAP algorithm calculates the APPs for each code symbol produced by a Markov process given a noisy channel observation y. The APPs are P [d k =1 y], the probability that the information bit is a 1 given the received vector y, andp [d k =0 y], the probability that the information bit is a 0 given the received vector y. Once these probabilities are found, they are put into log-likelihood ratio (LLR) form in order to make a decision on a particular symbol. The general form of the LLR for the k th bit is Λ k =ln P [d k =1 y] P [d k =0 y]. The MAP algorithm calculates the APPs by first finding the state transitional probability P [s k s k+1 y] given the received signal y. The term s k represents the state of the encoder at time k, ands k s k+1 is the state transition from state s k to state s k+1 at time k +1. This transitional probability is zero if state s k is not connected to state s k+1. Using Bayes Law and simplifying, the probability can be expressed as P [s k s k+1 y] = P [s k s k+1, y]. P [y]

31 W. Bruce Puckett Chapter 2. Turbo Codes 20 The denominator in the expression above does not need to be explicitly calculated because it will be canceled when the APPs are placed in LLR form. For notational convenience we define P [s k s k+1, y] =α k (s k ) γ k+1 (s k s k+1 ) β k+1 (s k+1 ), where α k (s k ), γ k+1 (s k s k+1 ), and β k+1 (s k+1 ) are defined in the following discussion. The term γ k+1 (s k s k+1 ) is the branch metric associated with the state transition s k s k+1. The branch metric, which can be calculated from known information, is expressed as γ k+1 (s k s k+1 )=P[s k+1 s k ] P [y k s k s k+1 ]=P[d k ] P [y k x k ]. The probability P [d k ] is derived from the a priori information, and the probability P [y k x k ]is determined from the received signal and knowledge of the trellis structure. The probability α k (s k ) is equal to the probability P [s k, (y 1,y 2,..., y k )] and can be found by the forward recursion α k (s k )= α k 1 (s k 1 ) γ k (s k 1 s k ). S k 1 Similarly, β k (s k )isequaltop[(y k+1,y k+2,..., y L 1 ) s k ] and can be found by the backward recursion β k (s k )= β k+1 (s k+1 ) γ k+1 (s k s k+1 ). S k+1 When α k (s k )andβ k (s k ) have been found for all states along the trellis, the APPs for each state transition are known. The APPs are related to the state transitional probabilities as P [d k = i y] = S i P [s k s k+1 y] where i {0, 1} and S i denotes the set of all state transitions associated with a message bit equal to i. The LLR for the k th symbol can then be calculated as S1 α k (s k ) γ k+1 (s k s k+1 ) β k+1 (s k+1 ) Λ k =ln S0α k (s k ) γ k+1 (s k s k+1 ) β k+1 (s k+1 ). If the LLR Λ k is greater than zero, a binary 1 is chosen as the most likely transmitted symbol; conversely, if the LLR Λ k is less than zero, a binary 0 is chosen. Because the initialization of α and β is similar for the MAP, Max-Log-MAP, and Log-MAP algorithms, this process will be explained in more detail in the following section.

32 W. Bruce Puckett Chapter 2. Turbo Codes 21 Max-Log-MAP and Log-MAP As mentioned previously, the MAP algorithm suffers from two serious drawbacks: its computationally complexity and its numerical instability. The solution to these problems is to operate in the log-domain. One advantage of operating in the log-domain is that multiplication becomes addition. Addition, however, is not as straight-forward. The Jacobian Logarithm illustrates how addition is accomplished in the log-domain. ln(e x + e y )=max(x, y)+f c ( y x ), where f c (x) =ln(1+e x ). Addition is simply a maximization function plus a correction term in the log-domain. The sub-optimal Max-Log-MAP algorithm approximates addition solely as a maximization. This is a reasonable approximation, especially when x and y are dissimilar. The performance of the Log-MAP algorithm, however, is equivalent to the MAP algorithm. The Log-MAP algorithm implements addition exactly as both the maximization function and the correction term. For practical implementations, this correction function can be stored in a lookup table. An 8-input lookup table in [21] was shown to give good performance in practice. Other approximations exist, and the turbo-coded system described in this thesis uses a linear approximation developed in [13]. In the log-domain the branch metric γ k+1 (s k s k+1 ) becomes γ k+1 (s k s k+1 )=lnγ k+1 (s k s k+1 )=lnp[d k ]+lnp[y k x k ]. Similarly, the probability α k (s k ) in the log-domain becomes α k (s k )=lnα k (s k )=ln S k 1 A exp(α k 1 (s k 1 )+γ k (s k 1 s k )) = max [α k 1 (s k 1 )+γ k (s k 1 s k )], S k 1 A where the max ( ) operation is equivalent to max(x, y) for the Max-Log-MAP algorithm and to max(x, y)+fc( y x ) for the Log-MAP algorithm. Notice that the max ( ) operation is taken over A, the set of all states s k 1 which are connected to state s k.

33 W. Bruce Puckett Chapter 2. Turbo Codes 22 Likewise, β k (s k ) becomes β k (s k )=lnβ k (s k )=ln S k+1 B exp(β k+1 (s k+1 )+γ k+1 (s k s k+1 )) = max [β k+1 (s k+1 )+γ k+1 (s k s k+1 )]. S k+1 B Here the max ( ) operation is taken over B, the set of all states s k+1 which are connected to state s k. After α k (s k )andβ k (s k ) are found for all states along the trellis, the LLRs are calculated as Λ k =max [α k (s k )+γ k+1 (s k s k+1 )+β k+1 (s k+1 )] S1 max [α k (s k )+γ k+1 (s k s k+1 )+β k+1 (s k+1 )]. S0 S1 is the set of all state transitions associated with an information bit d k =1,andS0 isthe set of all state transitions associated with an information bit d k = 0. The Max-Log-MAP and the Log-MAP algorithms are initialized in a manner analogous to the MAP algorithm. For a frame size N, assume each constituent encoder starts in the all-zeros state. Then for time k = 0, the forward path metric α k is initialized as α 0 (s 0,0 )=0 and α 0 (s j,0 )= for j 0. For time k = N, the backwards path metric β N is initialized in one of two ways. If the encoder trellis is terminated, The backwards path metric is initialized as β N (s 0,N )=0 and β N (s j,n )= for j 0 If the trellis is not terminated, then all states are equally likely to be the ending state. Therefore, the backwards path metric is initialized as β N (s j,n ) = 0 for all j. 2.4 Performance Examples Turbo code performance is affected by several factors. Figures 2.6 and 2.7 demonstrate the influence of the interleaver size and the number of decoding iterations on turbo code

34 W. Bruce Puckett Chapter 2. Turbo Codes 23 performance, respectively. The most important factor is the size of the interleaver. Because the asymptotic BER of a turbo code is approximately inversely proportional to its interleaver size, the BER decreases as the frame size increases. The design of the interleaver only affects performance minimally, and randomly selected interleavers will achieve near optimal performance on average. Another important performance factor is the number of iterations. As the iteration count increases, the BER decreases; returns diminish, however, as the number of iterations increases. Typically, the decoder requires more iterations to converge for larger frame sizes. Another important design decision which affects performance is the choice of the decoding algorithm. Several decoding algorithms and their relative performance were discussed in the last section. Performance is also dependent on the overall code rate. As the code rate increases, bandwidth efficiency improves at the cost of BER degradation. Trellis termination also has a small affect on performance. Because of the pseudo-random interleaver, terminating each trellis is difficult in practice. Typically, the first encoder is terminated, and the second encoder trellis is left open [22]. Other methods of trellis termination are available, however they require additional processing or impose additional structure on the interleaver design [23] [24]. Because the generator matrix of the constituent RSC encoders does not significantly affect performance, simple codes with constraint-lengths of 3 K 5 are often used in practice. Choosing the proper concatenated code for the application is also important. Because PCCCs provide better coding gain than SCCCs for BERs > 10 5, they should be used in applications that tolerate higher BERs or that operate at lower SNRs. SCCCs, however, do not suffer from the error floor that plagues PCCCs. For applications like data communications, which require BERs < 10 6, SCCCs may offer better performance; the increased performance of SCCCs, however, is offset by a slight increase in computational complexity.

35 W. Bruce Puckett Chapter 2. Turbo Codes frame errors registered at each value of Eb/No Framesize:256 Framesize:1024 Framesize:4096 Probability of Bit Error Decoding Iterations Rate = 1/2 G = [7,5] octal Log-MAP Algorithm Eb/NoindB Figure 2.6: BER vs. E b /N o comparison for turbo codes of different frame sizes frame errors registered at each value of Eb/No 1 Iteration 3 Iterations 6 Iterations 10 Iterations Probability of Bit Error Framesize = 1024 Rate = 1/2 G = [7,5] octal Log-MAP Algorithm Eb/NoindB Figure 2.7: BER vs. E b /N o comparison for turbo codes with different decoding iterations

36 W. Bruce Puckett Chapter 2. Turbo Codes Summary In this chapter the basic encoding and decoding operations of a turbo-coded system were reviewed, and several performance examples were provided. In the next chapter the basic concepts of configurable computing are introduced. Subsequent chapters will describe the details of a turbo-coded system on a configurable computing machine.

37 Chapter 3 Configurable Computing Despite the excellent performance of turbo codes, the challenges relating to computational complexity, power consumption, and memory limitations must be overcome before practical implementations are deployed for everyday use. Configurable computing machines offer a compromise between performance and flexibility and are uniquely suited for implementing turbo-coded systems. Configurable computing is characterized by specialized hardware which can rapidly reconfigure its functionality and interconnectivity to match the requirements of a particular task by reading a new configuration from memory. This ability offers designers a compromise between the two extremes of general-purpose digital signal processors (DSPs) and application-specific integrated circuits (ASICs). General-purpose processors, which are characterized by their flexibility and low cost, are able to perform a wide variety of computational tasks. Because of their flexibility, however, DSPs tend to be computationally inefficient. DSPs also suffer from higher power consumption and larger chip areas as compared to ASICs. At the other extreme, ASICs place a premium on performance by being tailored to execute a specific task. Although ASICs are inflexible and expensive, they offer designers maximum speed and computational performance while minimizing power consumption and chip area. Configurable computing machines (CCMs) attempt to simultaneously achieve the performance of ASICs while maintaining the flexibility of general purpose DSPs. Realization of CCMs is made possible by field-programmable gate arrays (FPGAs). 26

38 W. Bruce Puckett Chapter 3. Configurable Computing Field-Programmable Gate Arrays (FPGAs) The first FPGA was invented by Xilinx, Inc., in 1984 [25]. FPGAs consist of three main elements: configurable logic blocks (CLBs), input-output blocks (IOBs), and reprogrammable interconnects. CLBs are the functional elements used to implement the designer s logic. IOBs provide the interface between the pins on the physical chip and the internal, user-defined signal lines. The reprogrammable interconnects provide routing between the appropriate CLBs and IOBs. Historically, FPGAs have been used as glue logic - a means of interconnecting more complex system components, each with a specific task. Although there have been several traditional technologies used in creating FPGAs, synchronous random access memory (SRAM) FPGAs are by far the most popular because they allow for fast, in-circuit reconfiguration. SRAM-based FPGAs became a popular means of prototyping ASIC designs as their computational performance and gate densities increased. The current functionality for FPGAs employing SRAM technology is determined by the values stored in the FPGA s internal memory. Functional reconfiguration is achieved by reloading the SRAM cells with new values. Because of their inherent flexibility, FPGAs allow engineers to improve and reuse their designs quickly and inexpensively The Virtex Architecture The FPGA used in implementing the improved turbo decoder belongs to the Xilinx Virtex family. Virtex FPGAs have densities ranging from 50,000 to 4 million gates, employ up to 832 Kb of internal block RAM, and typically interface with external memory at speeds of 200 MHz [1]. The Virtex chip is a SRAM-based FPGA which employs a flexible architecture composed of CLBs, IOBs, and reprogrammable interconnects. The logic cell (LC) is the fundamental building block for Virtex-E CLBs. Each LC contains a 4-input function generator, carry logic, and a storage element. Each CLB contains 4 LCs grouped into 2 identical slices. Figures 3.1 and 3.2 depict a 2-slice Virtex CLB and a single Virtex slice, respectively.

39 W. Bruce Puckett Chapter 3. Configurable Computing 28 Figure 3.1: A 2-slice Virtex-E CLB [1] Figure 3.2: A single Virtex-E slice [1]

40 W. Bruce Puckett Chapter 3. Configurable Computing 29 DLL DLL DLL DLL VersaRing IOBs CLBs CLBs CLBs CLBs CLBs CLBs CLBs CLBs IOBs VersaRing DLL DLL DLL DLL Figure 3.3: Overview of the Virtex-E architecture [1] Each slice is capable of implementing any 5- or 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs. The function generators, which are implemented as 4-input lookup tables (LUTs), can be configured as 16 x 1 bit synchronous RAM. Each slice is capable of acting as a 16 x 2 or 32 x 1 bit SRAM. This feature is important because this SRAM is significantly faster than external memory and can be cascaded to form larger memory blocks with some simple logic. Each CLB also contains two direct feedthrough paths per slice which act as additional data or routing lines without expending additional logic resources. Another important feature of the Virtex family is the incorporation of internal Block SelectRAM. These memory blocks are fully synchronous, dual-port 4096-bit RAM which allow simultaneous read\writes to be performed. Figure 3.3 illustrates the Virtex architecture [1] Run-time Reconfiguration (RTR) Recent advances in FPGA technology have reduced configuration times and have even made partial, run-time reconfiguration possible. These techniques have led to a new area of research known as run-time reconfiguration (RTR). RTR systems are characterized by the

41 W. Bruce Puckett Chapter 3. Configurable Computing 30 ability to rapidly create and change distinct computational paths using a distributed control scheme. Wormhole RTR reconfigures the available resources at the onset or completion of computational data streams, allocating the appropriate data and computational resources as needed. The defining elements of Wormhole RTR systems are called streams. Streams are an independent, self-steering concatenation of program instructions and data used to execute a given task. Virginia Tech s first generation experimental Wormhole RTR system was developed on a reconfigurable integrated circuit named Colt [26]. Colt s successor, Stallion, is currently being developed. Stallion is an advanced, more efficient version of Colt. Although Stallion is similar in construction to an FPGA, it has been tailored to better meet the demands of a CCM system. Unlike FPGAs which operate on individual bits, Stallion incorporates 16-bit wide programmable data paths; this allows it to easily interface with word-wide DSP applications. Stallion offers true rapid, run-time, partial reconfiguration. Like its predecessor, Stallion can simultaneously support multiple data-driven streams. Figure 3.4 depicts the Stallion s organization and architecture. Allocable Resources IFU IFU MESH (computational) Programmable Data Data Ports Ports Stream I/O Smart Crossbar Network Integer Multipliers (allocable) Figure 3.4: Overview of the Stallion architecture

42 W. Bruce Puckett Chapter 3. Configurable Computing 31 Streams enter and leave the chip through redefinable data ports. Upon entering, the self-directing streams are routed by a smart crossbar to interconnect functional units (IFUs) which are used to accomplish the given task. IFUs are reconfigurable computing elements which are allocated dynamically by the tunneling streams [27]. A detailed discussion of the Stallion architecture is presented in [28]. The work of this thesis, though designed to be compatible with Wormhole RTR architectures when they become available, will focus on an implementation for a FPGA platform. 3.2 FPGA Platform Although the original design developed in [29] resided on the Wildforce CCM, the improved design was scheduled to be ported to the SLAAC1V architecture once it became available. The SLAAC1V PCI board provides the necessary structure which allows the PC, the FP- GAs, and the external SRAM to communicate. Because it is a PCI card, the SLAAC1V CCM must be installed in a PC to be used. The user controls the SLAAC1V board by developing host code which makes use of the SLAAC1V s application programming interfaces (APIs). The APIs allow the user to program the processing elements (PEs), set up the FPGA clocks, control the FIFOs, access the PE memories, perform PE readback, and control PE interrupts. The SLAAC1V CCM, whose architecture is pictured in Figure 3.5, uses three Xilinx XCV FPGAs as PEs. One of the FPGAs is designated as the control PE (X0). This PE is used to control X1 and X2, to route data to and from the FIFOs, and to buffer data in its memory banks. The main data paths between FPGAs are 72-bits wide. The memory data paths are 36-bits wide. Memory address lines are 20-bits wide [3]. X1 and X2 each have four SRAMs; X0 has two SRAMs. The SRAMs are connected with bus switches so that X0 can swap one SRAM with both X1 and X2. Each memory is a36 256K SRAM. The SLAAC1V memory architecture is illustrated in Figure 3.6. A timing diagram illustrating memory reads and writes is shown in Figure 3.7. The n notation denotes that the chip enable and write enable signals are active low. When

43 W. Bruce Puckett Chapter 3. Configurable Computing 32 Figure 3.5: SLAAC1V architecture [2] Figure 3.6: SLAAC1V memory architecture[2]