APPENDIX 1 FEATURES OF MICROCONTROLLER 89C51

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1 120 APPENDIX 1 FEATURES OF MICROCONTROLLER 89C51

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7 126 APPENDIX 2 ATMEGA8 MICROCONTROLLER CODE ; ; MOSFET Gating Pulse Generation for the ATMEL ATmega8. ; ; General Description of Approach: ; ; We are using PORTB1, 2, 3, 4 as our output gating signals ; It must be noted that on an H-bridge we have defined the following; ; ; Starting at the top left switch in the H-bridge we have switch G1 ; Moving counter-clockwise through the switches we have G2, G4, and ; Finally G3 as the top right-most switch. As labeled on the H-Bridge PCB. ; ; SO! Our Gating pulses come from the following PORTB outputs: ; Switch G1 = PORTB3 = PIN 17 ; Switch G2 = PORTB4 = PIN 18 ; Switch G3 = PORTB2 = PIN 16 ; Switch G4 = PORTB1 = PIN 15 ; ; At 100% load, G1 and G4 are in phase as well as G2 and G2 ; There must also be a delay between the turn off of G1 and G4 ; Into the turn on of G2 and G3. This delay is also seen in the ; reverse where G2 and G3 turn off and G1 and G4 turn on. ; include "m8def.inc" ; Interrupt Service Vectors.org 0x000 rjmp Reset.org OC1Aaddr rjmp T1comA; timer counter 1 compare match A.org OC1Baddr rjmp T1comB; timer counter 1 compare match B

8 127 ; Register definitions for variables.def pwmhi=r16; hi time for main control signal.def pwmlo=r17; lo time for main control signal.def pwmt=r18; Period of control signal.def tf=r19; Delay time for rise and fall.def temp=r20.def temp2=r21 ; Reset vector - initialize interrupts and service routines Reset: ldi temp, low (RAMEND) ;Set stack ptr to ram end out SPL,temp ldi temp,high(ramend) out SPH, temp ; Initialize timercounter1 and interrupts ldi temp,(1<<wgm12)+(1<<cs10) ;WGM12 Clear timer on compare to OCIE1A out TCCR1B, temp ;CS10 no prescale run at clock speed ldi temp,(1<<ocie1a)+(1<<ocie1b) ;tc1 compare matcha and matchb interrupts out TIMSK,temp ; ; Control signal values are here for Peroid value correspond to # of CPU cycles ; loads max count value for TimerCounter1 ; this is our period of control waveform ldi temp,0x01 out OCR1AH,temp ldi temp,0x90 out OCR1AL,temp ; This Changes duty cycle change me change me ; Loads compare value for duty cycle note must load H before low ldi temp,0x01 ;100% 0x01 15% 0x00 out OCR1BH,temp ldi temp,0x90 ;100% 0x90 15% 0x30 out OCR1BL,temp ; ; Initialize outputs ldi temp,(1<<ddb4) (1<<DDB3) (1<<DDB2) (1<<DDB1) ;sets data direction for pins out DDRB,temp ;set data direction to out ldi tf,0x01 sei loop: rjmp loop

9 ; Rising of Control signal T1comA: sbis PORTB,(PORTB2) rjmp bit2clear nop ;these nop s make both pulses have equivalent duty cycle nop nop cbi PORTB,(PORTB2) ;Clear G3 rcall DELAY sbi PORTB,(PORTB1) ;Set G4 reti bit2clear: cbi PORTB,(PORTB1) ;Clear G4 rcall DELAY sbi PORTB,(PORTB2) ;Set G3 reti ; Falling of Control signal T1comB: sbis PORTB,(PORTB4) rjmp bit4clear nop ;these nops make both pulses have equivalent duty cycle nop nop cbi PORTB,(PORTB4) ;Clear G2 rcall DELAY sbi PORTB,(PORTB3) ;Set G1 reti bit4clear: cbi PORTB,(PORTB3) ;Clear G1 rcall DELAY sbi PORTB,(PORTB4) ;Set G2 reti ; Delay subroutine DELAY: ldi temp,0x00 loopy: inc temp cpse temp,tf rjmp loopy ret 128

10 129 APPENDIX 3 FEATURES OF ARM PROCESSOR LPC2148

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28 147 APPENDIX 4 MAIN PROGRAM *******************MAIN PROGRAM**************************/ /***********************(PARTIALLY SHOWN) *****************/ int main (void) { /* main entry for program */ char cmdbuf [15]; int i; int idx; PINSEL1 = 0x ; IODIR1 = 0xFF0000; ADCR = 0x002E0401; init_serial (); T0MR0 = T0MCR = 3; T0TCR = 1; VICVectAddr0 = (unsigned long)tc0; VICVectCntl0 = 0x20 4; VICIntEnable = 0x ; VICDefVectAddr = (unsigned long) DefISR; clear_records (); printf ( menu ); while (1) { /* loop forever */

29 148 printf ("\ncommand: "); getline (&cmdbuf[0], sizeof (cmdbuf)); for (i = 0; cmdbuf[i]!= 0; i++) { /* convert to upper characters */ cmdbuf[i] = toupper(cmdbuf[i]); } for (i = 0; cmdbuf[i] == ' '; i++); switch (cmdbuf[i]) { /* proceed to command function */ case 'R': if ((idx = read_index (&cmdbuf[i+1])) == WRONGINDEX) break; while (idx!= sindex) { /* check end of table */ if (U1LSR & 0x01) { /* check serial interface */ } if (save_record[idx].time.hour!= 0xff) { measure_display (save_record[idx]); } } } } } * * *

30 149 APPENDIX 5 DESIGN OF PI CONTROLLER Controllers based on the PI approach are commonly used for DC DC converter applications. Power converters have relatively low order dynamics that can be well controlled by the PI method. Ziegler and Nichols conducted numerous experiments and proposed rules for determining values of K P and K I based on the transient step response of system. Figure A5.1 S-shaped reaction curve

31 150 Table A5.1 Ziegler-Nichols tuning rule Controller K P K I K D P T L 0 0 PI PID T.9 L T L T.2 L T L T It applies to resonant converter with neither integrator nor dominant complex-conjugate poles, whose unit-step response resemble an S- shaped curve with no overshoot. This S-shaped curve is called the reaction curve. The S-shaped reaction curve (shown in Figure A5.1) can be characterized by two constants, delay time (L) and time constant (T), which are determined by drawing a tangent line at the inflection point of the curve and finding the intersections of the tangent line with the time axis and the steady-state level line. Using the parameters L and T, we can set the values of K P, K I and K D according to the formula shown in the Table A5.1. These parameters will typically give a response with an overshoot about 25% and good settling time. Based on the Ziegler-Nichols Tuning Rule, Proportional gain Constant (K P ) = 0.05 and Integral Time Constant (K I ) = 25 are obtained for the converter under study.

32 151 APPENDIX 6 DC GAIN CHARACTERISTICS AND OPERATING REGION OF LCC AND LCL RESONANT CONVERTERS The quality factor (Q ) and resonant frequency ( f o ) of LCC resonant converter is given below: Q Z L C 1C 2 C C 1 L 2 and (A6.1) f o 2 L 1 C C 1 1 C 2 C 2 Figure A6.1 shows the DC characteristic of LCC resonant converter. The major problems of Series Resonant Converter (SRC) are light-load regulation, high circulating energy and high turn-off current at nominal input voltage. The major problems of Parallel Resonant Converter (PRC) are high circulating energy; high turns off current at high input voltage condition. Compare with SRC, the operating region is much smaller.

33 152 Figure A6.1 DC gain characteristics and operating region of LCC resonant converter At light load, the frequency doesn't need to change too much to keep output voltage regulated. So light load regulation problem doesn't exist in PRC. The LCC resonant tank can be considered as the combination of Series Resonant Converter and Parallel Resonant Converter thereby combining the advantages of both. Figure A6.1 shows that the maximum gain, which is determined by Q, affects the operating range of the switching frequency regulating the output voltage under line variation.

34 153 From the Figure A6.1, it can be observed that LCC resonant converters can achieve a narrow switching frequency range with load change. At light-load conditions, the circulating energy is smaller. The LCC has two resonant frequencies, series resonant frequency and parallel resonant frequency. Although operating at the series resonant frequency is desirable for high efficiency, when doing so, ZVS is lost for certain load conditions. Thus, the operating region is designed to be on the right-hand side of the parallel resonant frequency to achieve ZVS at all load conditions. Unfortunately, like the PRC and SRC, for the LCC, the circulating energy and turn-off current of the device also increases at nominal input voltage Vin_max. In sum, to deal with a wide input voltage range, all these traditional resonant converters encounter some problems. To achieve higher efficiency, LCL resonant topologies should be considered. The quality factor (Q) and resonant frequency ( f o ) of the LCL resonant converter is given below. 1 f o 2 ( L1 L2 ) C and L r Q C Z Where, L L C r L C L r 1 2 (A6.2) The voltage gain of the LCL resonant converter is drawn in Figure A6.2. LCL-T and LCC Resonant converters encounter problems while dealing with a wide input voltage range. Meanwhile, at the nominal condition, the LCL resonant converter operates very close to the resonant frequency,

35 154 which is the best operation point to accomplish high efficiency. In addition, voltage gains of different Q converge at the series resonant point. The LCL resonant tank parameters can be optimized to achieve high efficiency for a wide load range. As a result, holdup time extension capability is accomplished without sacrificing the efficiency at the nominal condition. The LCL resonant converter is considered as one of the most desirable topologies for wide input voltage range. Figure A6.2 DC gain characteristics and operating region of LCL resonant converter