8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash. ATtiny48/88

Transcription

1 Features High Performance, Low Power AVR 8-Bit Microcontroller Advanced RISC Architecture 23 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation High Endurance Non-volatile Memory Segments 4K/8K Bytes of In-System Self-Programmable Flash Program Memory 64/64 Bytes EEPROM 256/52 Bytes Internal SRAM Write/Erase Cycles:, Flash/, EEPROM Data Retention: 2 years at 85 C / years at 25 C Programming Lock for Software Security Peripheral Features One 8-bit Timer/Counter with Separate Prescaler and Compare Mode One 6-bit Timer/Counter with Prescaler, and Compare and Capture Modes 6- or 8-channel -bit ADC Master/Slave SPI Serial Interface Byte-oriented 2-wire Serial Interface (Philips I 2 C Compatible) Programmable Watchdog Timer with Separate On-Chip Oscillator On-Chip Analog Comparator Interrupt and Wake-up on Pin Change Special Microcontroller Features debugwire On-Chip Debug System In-System Programmable via SPI Port Power-On Reset and Programmable Brown-Out Detection Internal Calibrated Oscillator External and Internal Interrupt Sources Three Sleep Modes: Idle, ADC Noise Reduction and Power-Down On-Chip Temperature Sensor I/O and Packages 24 Programmable I/O Lines: 28-pin PDIP 28-pad QFN 28 Programmable I/O Lines: 32-lead TQFP 32-pad QFN 32-ball UFBGA Operating Voltage:.8 5.5V Temperature Range: -4 C to +85 C Speed Grade: 4 5.5V V V Low Power Consumption Active Mode: MHz,.8V: 24 µa Power-Down Mode:. µa at.8v 8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash ATtiny48/88 Rev.

2 . Pin Configurations Figure -. Pinout of ATtiny48/88 TQFP Top View (PCINT9/INT) PD3 (PCINT2/T) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB PD2 (INT/PCINT8) PD (PCINT7) PD (PCINT6) PC6 (RESET/PCINT4) PC5 (ADC5/SCL/PCINT3) PC4 (ADC4/SDA/PCINT2) PC3 (ADC3/PCINT) PC2 (ADC2/PCINT) PC (ADC/PCINT9) PC (ADC/PCINT8) PA (ADC7/PCINT25) GND PC7 (PCINT5) PA (ADC6/PCINT24) AVCC PB5 (SCK/PCINT5) (PCINT4/RESET) PC6 (PCINT6) PD (PCINT7) PD (PCINT8/INT) PD2 (PCINT9/INT) PD3 (PCINT2/T) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT2/T) PD5 (PCINT22/AIN) PD6 (PCINT23/AIN) PD7 (PCINT/CLKO/ICP) PB PDIP PC5 (ADC5/SCL/PCINT3) PC4 (ADC4/SDA/PCINT2) PC3 (ADC3/PCINT) PC2 (ADC2/PCINT) PC (ADC/PCINT9) PC (ADC/PCINT8) GND PC7 (PCINT5) AVCC PB5 (SCK/PCINT5) PB4 (MISO/PCINT4) PB3 (MOSI/PCINT3) PB2 (SS/OCB/PCINT2) PB (OCA/PCINT) (PCINT2/T) PD5 (PCINT22/AIN) PD6 (PCINT23/AIN) PD7 (PCINT/CLKO/ICP) PB (PCINT/OCA) PB (PCINT2/SS/OCB) PB2 (PCINT3/MOSI) PB3 (PCINT4/MISO) PB4 28 QFN Top View PD2 (INT/PCINT8) PD (PCINT7) PD (PCINT6) PC6 (RESET/PCINT4) PC5 (ADC5/SCL/PCINT3) PC4 (ADC4/SDA/PCINT2) PC3 (ADC3/PCINT) 32 QFN Top View PD2 (INT/PCINT8) PD (PCINT7) PD (PCINT6) PC6 (RESET/PCINT4) PC5 (ADC5/SCL/PCINT3) PC4 (ADC4/SDA/PCINT2) PC3 (ADC3/PCINT) PC2 (ADC2/PCINT) (PCINT9/INT) PD3 (PCINT2/T) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT2/T) PD (PCINT9/INT) PD3 (PCINT2/T) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB PC (ADC/PCINT9) PC (ADC/PCINT8) PA (ADC7/PCINT25) GND PC7 (PCINT5) PA (ADC6/PCINT24) AVCC PB5 (SCK/PCINT5) PC2 (ADC2/PCINT) PC (ADC/PCINT9) PC (ADC/PCINT8) GND PC7 (PCI NT5) AVCC PB5 (SCK/PCINT5) NOTE: Bottom pad should be soldered to ground. (PCINT22/AIN) PD6 (PCINT23/AIN) PD7 (PCINT/CLKO/ICP) PB (PCINT/OCA) PB (PCINT2/SS/OCB) PB2 (PCINT3//MOSI) PB3 (PCINT4/MISO) PB4 NOTE: Bottom pad should be soldered to ground. (PCINT2/T) PD5 (PCINT22/AIN) PD6 (PCINT23/AIN) PD7 (PCINT/CLKO/ICP) PB (PCINT/OCA) PB (PCINT2/SS/OCB) PB2 (PCINT3/MOSI) PB3 (PCINT4/MISO) PB4 Table UFBGA Top View. See page A PD2 PD PC6 PC4 PC2 PC B PD3 PD4 PD PC5 PC3 PC C GND PA2 PA GND D VCC PA3 PC7 PA E PB6 PD6 PB PB2 AVCC PB5 F PB7 PD5 PD7 PB PB3 PB4 2 ATtiny48/88

3 ATtiny48/88. Pin Descriptions.. VCC..2 AVCC..3 GND Digital supply voltage. AV CC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should be externally connected to V CC even if the ADC is not used. If the ADC is used, it is recommended this pin is connected to V CC through a low-pass filter, as described in Analog Noise Canceling Techniques on page 72. The following pins receive their supply voltage from AV CC : PC7, PC[5:] and (in 32-lead packages) PA[:]. All other I/O pins take their supply voltage from V CC. Ground...4 Port A (PA3:)..5 Port B (PB7:) Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PA[3:] output buffers have symmetrical drive characteristics with both sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port is available in 32-lead TQFP, 32-pad QFN and 32-ball UFBGA packages, only. Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock operating circuit. The various special features of Port B are elaborated in Alternate Functions of Port B on page Port C (PC7, PC5:) Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC7 and PC[5:] output buffers have symmetrical drive characteristics with both sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running...7 PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for longer than the minimum pulse width will generate a reset, even if the clock is not running. The 3

4 ..8 Port D (PD7:) minimum pulse length is given in Table 22-3 on page 29. Shorter pulses are not guaranteed to generate a reset. The various special features of Port C are elaborated in Alternate Functions of Port C on page 72. Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PD[7:4] output buffers have symmetrical drive characteristics with both sink and source capabilities, while the PD[3:] output buffers have high sink capabilities. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in Alternate Functions of Port D on page ATtiny48/88

5 ATtiny48/88 2. Overview The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2. Block Diagram Figure 2-. Block Diagram GND VCC Watchdog Timer Watchdog Oscillator Power Supervision POR / BOD & RESET debugwire Program Logic Oscillator Circuits / Clock Generation Flash SRAM EEPROM CPU 8bit T/C 6bit T/C A/D Conv. DATABUS 6 Internal Bandgap 2 Analog Comp. SPI TWI PORT D (8) PORT B (8) PORT C (8) PORT A (4) RESET CLKI PD[:7] PB[:7] PC[:7] PA[:3] (in TQFP and MLF) The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 5

6 The ATtiny48/88 provides the following features: 4/8K bytes of In-System Programmable Flash 64/64 bytes EEPROM 256/52 bytes SRAM 24 general purpose I/O lines 28 in 32-lead TQFP, 32-pad QFN, and 32-ball UFBGA packages 32 general purpose working registers Two flexible Timer/Counters with compare modes Internal and external interrupts A byte-oriented, 2-wire serial interface An SPI serial port A 6-channel, -bit ADC 8 in 32-lead TQFP, 32-pad QFN, and 32-ball UFBGA packages A programmable Watchdog Timer with internal oscillator Three software selectable power saving modes. The device includes the following modes for saving power: Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt system to continue functioning ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset The device is manufactured using Atmel s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Flash memory. By combining an 8-bit RISC CPU with In-System Self- Programmable Flash on a monolithic chip, the Atmel ATtiny48/88 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny48/88 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits. 2.2 Comparison Between ATtiny48 and ATtiny88 The ATtiny48 and ATtiny88 differ only in memory sizes, as summarised in Table 2-, below. Table 2-. Memory Size Summary Device Flash EEPROM RAM ATtiny48 4K Bytes 64 Bytes 256 Bytes ATtiny88 8K Bytes 64 Bytes 52 Bytes 6 ATtiny48/88

7 ATtiny48/88 3. General Information 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download at About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, IN, OUT, SBIS, SBIC, CBI, and SBI instructions must be replaced with instructions that allow access to extended I/O. Typically LDS and STS combined with SBRS, SBRC, SBR, and CBR. 3.3 Capacitive Touch Sensing Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch and QMatrix acquisition methods. Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor. The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of implementation, refer to the QTouch Library User Guide also available from the Atmel website. 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than PPM over 2 years at 85 C or years at 25 C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. 7

8 4. AVR CPU Core 4. Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.2 Architectural Overview Figure 4-. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit SPI Unit Instruction Decoder Control Lines Direct Addressing Indirect Addressing ALU Watchdog Timer Analog Comparator I/O Module Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 8 ATtiny48/88

9 ATtiny48/88 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File in one clock cycle. Six of the 32 registers can be used as three 6-bit indirect address register pointers for Data Space addressing enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 6-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 6-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, x2 x5f. In addition, the ATtiny48/88 has Extended I/O space from x6 xff in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 4.3 ALU Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See external document AVR Instruction Set and Instruction Set Summary on page 28 section for more information. 4.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as 9

10 specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 6-bit result input One 6-bit output operand and one 6-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. General Purpose Working Registers 7 Addr. Special Function R R R2 R3 x x x2 x3... R2 R3 R4 R5 R6 R7 xc xd xe xf x x... R26 xa X-register Low Byte R27 xb X-register High Byte R28 xc Y-register Low Byte R29 xd Y-register High Byte R3 xe Z-register Low Byte R3 xf Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. ATtiny48/88

11 ATtiny48/88 As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file The X-register, Y-register, and Z-register The registers R26:R3 have some added functions to their general purpose usage. These registers are 6-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. Figure 4-3. The X-, Y-, and Z-registers 5 X-register 7 XH 7 XL R27 R26 5 Y-register 7 YH 7 YL R29 R28 5 Z-register 7 ZH 7 ZL R3 R3 4.6 Stack Pointer In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack grows from higher memory locations to lower memory locations. This means that the PUSH instructions decreases and the POP instruction increases the stack pointer value. The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack space must be defined by the program before any subroutine calls are executed or interrupts are enabled. The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by one when data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction). The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack pointer and the number of bits implemented is device dependent. In some

12 AVR devices all data memory can be addressed using SPL, only. In this case, the SPH register is not implemented. The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of SRAM. See Table 5-2 on page Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk CPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T T2 T3 T4 4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Lock Bits LB2 or LB are proclk CPU st Instruction Fetch st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation T T2 T3 T4 clk CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 2 ATtiny48/88

13 ATtiny48/88 grammed. This feature improves software security. See the section Lock Bits, Fuse Bits and Device Signature on page 88 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in Interrupts on page 52. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT the External Interrupt Request. Refer to Interrupts on page 52 for more information. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction RETI is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the 3

14 CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r6, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r6 ; restore SREG value (I-bit) C Code Example char csreg; csreg = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR = (<<EEMPE); /* start EEPROM write */ EECR = (<<EEPE); SREG = csreg; /* restore SREG value (I-bit) */ Note: See About Code Examples on page 7. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) C Code Example enable_interrupt(); /* set Global Interrupt Enable */ sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ Note: See About Code Examples on page Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 4 ATtiny48/88

15 ATtiny48/ Register Description 4.9. SPH and SPL Stack Pointer Registers Initial Value RAMEND RAMEND Read/Write R R R R R R R/W R/W Bit x3e (x5e) SP9 SP8 SPH x3d (x5d) SP7 SP6 SP5 SP4 SP3 SP2 SP SP SPL Bit Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND SREG Status Register Bits 9: SP[:]: Stack Pointer The Stack Pointer register points to the top of the stack, which is implemented growing from higher memory locations to lower memory locations. Hence, a stack PUSH command decreases the Stack Pointer. The stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Bit x3f (x5f) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit 7 I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. Bit 6 T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. Bit 5 H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the Instruction Set Description for detailed information. Bit 4 S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two s Complement Overflow Flag V. See the Instruction Set Description for detailed information. 5

16 Bit 3 V: Two s Complement Overflow Flag The Two s Complement Overflow Flag V supports two s complement arithmetics. See the Instruction Set Description for detailed information. Bit 2 N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 6 ATtiny48/88

17 ATtiny48/88 5. Memories The AVR architecture makes a distinction between program memory and data memory, locating each memory type in a separate address space. Executable code is located in non-volatile program memory (Flash), whereas data can be placed in either volatile (SRAM) or non-volatile memory (EEPROM). See Figure 5-, below. Figure 5-. Memory Overview. DATA MEMORY PROGRAM MEMORY EXTENDED I/O REGISTER FILE DATA MEMORY I/O REGISTER FILE GENERAL PURPOSE REGISTER FILE FLASH SRAM EEPROM All memory spaces are linear and regular. 5. Program Memory (Flash) ATtiny48/88 contains 4/8K byte of on-chip, in-system reprogrammable Flash memory for program storage. Flash memories are non-volatile, i.e. they retain stored information even when not powered. Since all AVR instructions are 6 or 32 bits wide, the Flash is organized as 496/892 x 6 bits. The Program Counter (PC) is /2 bits wide, thus capable of addressing all 496/892 locations of program memory, as illustrated in Table 5-, below. Table 5-. Size of Program Memory (Flash). Device Flash Size Address Range ATtiny48 4KB x x7ff ATtiny88 8KB x xfff Constant tables can be allocated within the entire address space of program memory. See instructions LPM (Load Program Memory), and SPM (Store Program Memory) in Instruction Set Summary on page 28. Flash program memory can also be programmed from an external device, as described in External Programming on page 9. Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing on page 2. The Flash memory has a minimum endurance of, write/erase cycles. 7

18 5.2 Data Memory (SRAM) and Register Files Table 5-2 shows how the data memory and register files of ATtiny48/88 are organized. These memory areas are volatile, i.e. they do not retain information when power is removed. Table 5-2. Layout of Data Memory and Register Area. Device Memory Area Size Long Address () Short Address (2) ATtiny48 ATtiny88 General purpose register file 32B x xf n/a I/O register file 64B x2 x5f x x3f Extended I/O register file 6B x6 xff n/a Data SRAM 256B x xff n/a General purpose register file 32B x xf n/a I/O register file 64B x2 x5f x x3f Extended I/O register file 6B x6 xff n/a Data SRAM 52B x x2ff n/a Note:. Also known as data address. This mode of addressing covers the entire data memory and register area. The address is contained in a 6-bit area of two-word instructions. 2. Also known as direct I/O address. This mode of addressing covers part of the register area, only. It is used by instructions where the address is embedded in the instruction word. The 52/768 memory locations include the general purpose register file, I/O register file, extended I/O register file, and the internal data memory. For compatibility with future devices, reserved bits should be written to zero, if accessed. Reserved I/O memory addresses should never be written General Purpose Register File The first 32 locations are reserved for the general purpose register file. These registers are described in detail in General Purpose Register File on page I/O Register File Following the general purpose register file, the next 64 locations are reserved for I/O registers. Registers in this area are used mainly for communicating with I/O and peripheral units of the device. Data can be transferred between I/O space and the general purpose register file using instructions such as IN, OUT, LD, ST, and derivatives. All I/O registers in this area can be accessed with the instructions IN and OUT. These I/O specific instructions address the first location in the I/O register area as x and the last as x3f. The low 32 registers (address range x...xf) are accessible by some bit-specific instructions. In these registers, bits are easily set and cleared using SBI and CBI, while bit-conditional branches are readily constructed using instructions SBIC, SBIS, SBRC, and SBRS. Registers in this area may also be accessed with instructions LD/LDD/LDI/LDS and ST/STD/STS. These instructions treat the entire volatile memory as one data space and, therefore, address I/O registers starting at x2. See Instruction Set Summary on page ATtiny48/88

19 ATtiny48/88 ATtiny48/88 also contains three general purpose I/O registers that can be used for storing any information. See GPIOR, GPIOR and GPIOR2 in Register Summary on page 277. These general purpose I/O registers are particularly useful for storing global variables and status flags, since they are accessible to bit-specific instructions such as SBI, CBI, SBIC, SBIS, SBRC, and SBRS Extended I/O Register File Following the standard I/O register file, the next 6 locations are reserved for extended I/O registers. ATtiny48/88 is a complex microcontroller with more peripheral units than can be addressed with the IN and OUT instructions. Registers in the extended I/O area must be accessed using instructions LD/LDD/LDI/LDS and ST/STD/STS. See Instruction Set Summary on page 28. See Register Summary on page 277 for a list of I/O registers Data Memory (SRAM) Following the general purpose register file and the I/O register files, the remaining 256/52 locations are reserved for the internal data SRAM. There are five addressing modes available: Direct. This mode of addressing reaches the entire data space. Indirect. Indirect with Displacement. This mode of addressing reaches 63 address locations from the base address given by the Y- or Z-register. Indirect with Pre-decrement. In this mode the address register is automatically decremented before access. Address pointer registers (X, Y, and Z) are located in the general purpose register file, in registers R26 to R3. See General Purpose Register File on page. Indirect with Post-increment. In this mode the address register is automatically incremented after access. Address pointer registers (X, Y, and Z) are located in the general purpose register file, in registers R26 to R3. See General Purpose Register File on page. All addressing modes can be used on the entire volatile memory, including the general purpose register file, the I/O register files and the data memory. Internal SRAM is accessed in two clk CPU cycles, as illustrated in Figure 5-2, below. 9

20 Figure 5-2. On-chip Data SRAM Access Cycles T T2 T3 clk CPU Address Compute Address Address valid Data WR Data RD Read Write Memory Access Instruction Next Instruction 5.3 Data Memory (EEPROM) ATtiny48/88 contains 64 bytes of non-volatile data memory. This EEPROM is organized as a separate data space, in which single bytes can be read and written. All access registers are located in the I/O space. The EEPROM memory layout is summarised in Table 5-3, below. Table 5-3. Size of Non-Volatile Data Memory (EEPROM). Device EEPROM Size Address Range ATtiny48/88 64B x x3f The internal 8MHz oscillator is used to time EEPROM operations. The frequency of the oscillator must be within the requirements described in OSCCAL Oscillator Calibration Register on page 34. When powered by heavily filtered supplies, the supply voltage, V CC, is likely to rise or fall slowly on power-up and power-down. Slow rise and fall times may put the device in a state where it is running at supply voltages lower than specified. To avoid problems in situations like this, see Preventing EEPROM Corruption on page 22. The EEPROM has a minimum endurance of, write/erase cycles Programming Methods There are two methods for EEPROM programming: Atomic byte programming. This is the simple mode of programming, where target locations are erased and written in a single operation. In this mode of operation the target is guaranteed to always be erased before writing but programmin times are longer. Split byte programming. It is possible to split the erase and write cycle in two different operations. This is useful when short access times are required, for example when supply voltage is falling. In order to take advantage of this method target locations must be erased 2 ATtiny48/88

21 ATtiny48/88 before writing to them. This can be done at times when the system allows time-critical operations, typically at start-up and initialisation. The programming method is selected using the EEPROM Programming Mode bits (EEPM and EEPM) in EEPROM Control Register (EECR). See Table 5-4 on page 26. Write and erase times are given in the same table. Since EEPROM programming takes some time the application must wait for one operation to complete before starting the next. This can be done by either polling the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR), or via the EEPROM Ready Interrupt. The EEPROM interrupt is controlled by the EEPROM Ready Interrupt Enable (EERIE) bit in EECR Read To read an EEPROM memory location follow the procedure below: Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no other EEPROM operations are in process. If set, wait to clear. Write target address to EEPROM Address Registers (EEARH/EEARL). Start the read operation by setting the EEPROM Read Enable bit (EERE) in the EEPROM Control Register (EECR). During the read operation, the CPU is halted for four clock cycles before executing the next instruction. Read data from the EEPROM Data Register (EEDR) Erase In order to prevent unintentional EEPROM writes, a specific procedure must be followed to erase memory locations. To erase an EEPROM memory location follow the procedure below: Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no other EEPROM operations are in process. If set, wait to clear. Set mode of programming to erase by writing EEPROM Programming Mode bits (EEPM and EEPM) in EEPROM Control Register (EECR). Write target address to EEPROM Address Registers (EEARH/EEARL). Enable erase by setting EEPROM Master Program Enable (EEMPE) in EEPROM Control Register (EECR). Within four clock cycles, start the erase operation by setting the EEPROM Program Enable bit (EEPE) in the EEPROM Control Register (EECR). During the erase operation, the CPU is halted for two clock cycles before executing the next instruction. The EEPE bit remains set until the erase operation has completed. While the device is busy programming, it is not possible to perform any other EEPROM operations Write In order to prevent unintentional EEPROM writes, a specific procedure must be followed to write to memory locations. Before writing data to EEPROM the target location must be erased. This can be done either in the same operation or as part of a split operation. Writing to an unerased EEPROM location will result in corrupted data. 2

22 To write an EEPROM memory location follow the procedure below: Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no other EEPROM operations are in process. If set, wait to clear. Set mode of programming by writing EEPROM Programming Mode bits (EEPM and EEPM) in EEPROM Control Register (EECR). Alternatively, data can be written in one operation or the write procedure can be split up in erase, only, and write, only. Write target address to EEPROM Address Registers (EEARH/EEARL). Write target data to EEPROM Data Register (EEDR). Enable write by setting EEPROM Master Program Enable (EEMPE) in EEPROM Control Register (EECR). Within four clock cycles, start the write operation by setting the EEPROM Program Enable bit (EEPE) in the EEPROM Control Register (EECR). During the write operation, the CPU is halted for two clock cycles before executing the next instruction. The EEPE bit remains set until the write operation has completed. While the device is busy with programming, it is not possible to do any other EEPROM operations Preventing EEPROM Corruption During periods of low V CC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. At low supply voltages data in EEPROM can be corrupted in two ways: The supply voltage is too low to maintain proper operation of an otherwise legitimate EEPROM program sequence. The supply voltage is too low for the CPU and instructions may be executed incorrectly. EEPROM data corruption is avoided by keeping the device in reset during periods of insufficient power supply voltage. This is easily done by enabling the internal Brown-Out Detector (BOD). If BOD detection levels are not sufficient for the design, an external reset circuit for low V CC can be used. Provided that supply voltage is sufficient, an EEPROM write operation will be completed even when a reset occurs. 22 ATtiny48/88

23 ATtiny48/ Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts occur during execution of these functions. Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR, EEPE rjmp EEPROM_write ; Set Programming mode ldi r6, (<<EEPM) (<<EEPM) out EECR, r6 ; Set up address (r8:r7) in address registers out EEARH, r8 out EEARL, r7 ; Write data (r9) to data register out EEDR, r9 ; Write logical one to EEMPE sbi EECR, EEMPE ; Start eeprom write by setting EEPE sbi EECR, EEPE ret Note: See About Code Examples on page 7. C Code Example void EEPROM_write(unsigned int ucaddress, unsigned char ucdata) { /* Wait for completion of previous write */ while(eecr & (<<EEPE)) ; /* Set Programming mode */ EECR = (<<EEPM) (<<EEPM) /* Set up address and data registers */ EEAR = ucaddress; EEDR = ucdata; /* Write logical one to EEMPE */ EECR = (<<EEMPE); /* Start eeprom write by setting EEPE */ EECR = (<<EEPE); } Note: See About Code Examples on page 7. 23

24 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR, EEPE rjmp EEPROM_read ; Set up address (r8:r7) in address registers out EEARH, r8 out EEARL, r7 ; Start eeprom read by writing EERE sbi EECR, EERE ; Read data from data register in r6, EEDR ret Note: See About Code Examples on page 7. C Code Example unsigned char EEPROM_read(unsigned int ucaddress) { /* Wait for completion of previous write */ while(eecr & (<<EEPE)) ; /* Set up address register */ EEAR = ucaddress; /* Start eeprom read by writing EERE */ EECR = (<<EERE); /* Return data from data register */ return EEDR; } Note: See About Code Examples on page ATtiny48/88

25 ATtiny48/ Register Description 5.4. EEARH and EEARL EEPROM Address Register Bit EEARH x2 (x4) EEAR5 EEAR4 EEAR3 EEAR2 EEAR EEAR EEARL Read/Write R R R R R R R R R R R/W R/W R/W R/W R/W R/W Initial Value X X X X X X EEDR EEPROM Data Register Bits 5:6 Res: Reserved Bits These bits are reserved and will always read zero. Bits 5: EEAR[5:]: EEPROM Address The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in the 64/64 bytes EEPROM space. The EEPROM data bytes are addressed linearly between and 63/63. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. Bit x2 (x4) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value EECR EEPROM Control Register Bits 7: EEDR[7:]: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. Bit xf (x3f) EEPM EEPM EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value X X X Bits 7:6 Res: Reserved Bits These bits are reserved and will always read zero. Bits 5:4 EEPM[:]: EEPROM Programming Mode Bits EEPROM programming mode bits define the action that will be triggered when EEPE is written. Data can be programmed in a single atomic operation, where the previous value is automatically 25

26 erased before the new value is programmed, or Erase and Write can be split in two different operations. The programming times for the different modes are shown in Table 5-4. Table 5-4. EEPROM Programming Mode Bits and Programming Times EEPM EEPM Programming Time Operation 3.4 ms Atomic (erase and write in one operation).8 ms Erase, only.8 ms Write, only Reserved When EEPE is set any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to b unless the EEPROM is busy programming. Bit 3 EERIE: EEPROM Ready Interrupt Enable Writing this bit to one enables the EEPROM Ready Interrupt. Provided the I-bit in SREG is set, the EEPROM Ready Interrupt is triggered when non-volatile memory is ready for programming. Writing this bit to zero disables the EEPROM Ready Interrupt. Bit 2 EEMPE: EEPROM Master Write Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set and EEPE written within four clock cycles the EEPROM at the selected address will be programmed. Hardware clears the EEMPE bit to zero after four clock cycles. If EEMPE is zero the EEPE bit will have no effect. Bit EEPE: EEPROM Write Enable The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):. Wait until EEPE becomes zero. 2. Wait until SELFPRGEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 6. Within four clock cycles after setting EEMPE, write a logical one to EEPE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. If the Flash is never being updated by the CPU, step 2 can be omitted. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the 26 ATtiny48/88

27 ATtiny48/88 interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. Bit EERE: EEPROM Read Enable This is the read strobe of the EEPROM. When the target address has been set up in the EEAR, the EERE bit must be written to one to trigger the EEPROM read operation. EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it not possible to read the EEPROM, or to change the address register (EEAR) GPIOR2 General Purpose I/O Register 2 Bit x2b (x4b) MSB LSB GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value This register may be used freely for storing any kind of data GPIOR General Purpose I/O Register Bit x2a (x4a) MSB LSB GPIOR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value This register may be used freely for storing any kind of data GPIOR General Purpose I/O Register Bit xe (x3e) MSB LSB GPIOR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value This register may be used freely for storing any kind of data. 27