Brief Manual of MiDAS2.0 Family. FLASH / ISP / IAP 8-bit Turbo Microcontrollers. V1.2 June 2005

Transcription

1 MiDAS Family BM-MiDAS2.-V.2 Brief Manual of MiDAS2. Family FLASH / ISP / IAP 8-bit Turbo Microcontrollers V.2 June 25 GenCore Technology reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. The GenCore products listed in this document are intended for usage in general electronics applications. These GenCore products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury. ( mcu-support@gencore.co.kr)

2 Contents. Product Overview 2. Features 3. Block Diagram 4. Pin Configurations 5. Pin Descriptions 6. Function Descriptions CPU Descriptions - Memory Organization - SFR Map and Description - Instruction Set Summary -CPU Timing - IO configuration Peripheral Descriptions -I/O Ports -LVD (Low Voltage Detector) -WDT (Watchdog Timer) - Timer//2 -UART/(Universal Async. RX/TX) - 2 PWM outputs in PCA/ (Programmable Counter Array) -ADC -Interrupt - Reset Circuit -Clock Circuit - Power Management - FLASH Parallel Programming -FLASH ISP/IAP 7. Strong Points Compared to Conventional 8C52 8. Absolute Maximum Ratings 9. DC Characteristics. AC Characteristics.ADC Specifications 2.Package Dimensions 3.Product Numbering System 4.Supporting Tools Appendix A. Instruction Set B. SFR Descriptions C. Update History MiDAS2. Family [2]

3 . Product Overviews GenCore s MiDAS2. family is a group of fast 8C52 compatible microcontrollers The instruction execution time is max. 3 times faster than that of traditional 8C52. Machine cycle = 4 clocks vs. 2 clocks MiDAS2. family s additional peripherals: bit ADC / 2 PWM outputs in two 6-module PCA's / Extra UART / WDT / LVD / POR. Power saving modes to reduce power consumption Noise tolerant scheme Support ISP / IAP of FLASH memory Provides User-Friendly MDS environment with on-chip HW debug engine Provides Easy-to-Use training-kit system MiDAS2. Family [3]

4 . Product Overviews (Cont d) A. MiDAS. Family - GC8C52G Series (General MCU) Product Mask-ROM (byte) EPROM (byte) RAM (Byte) Volt (V) Freq. T/C (MHz) (6bits) Serial I/O WDT ADC PWM (bit x ch) (bit x ch) I/O Pins Package Others Available Time GC87C52G-PL44I GC87C52G-LQ44I GC87C52G-P4I GC87C52G-SP28I GC87C52G-SO28I - 8K ~5.5 4 (2) 3 UART YES PLCC 44-LQFP 4-PDIP 28-SPDIP 28-SOIC LVD POR Now Now Now Now Now GC8C52G-PL44I GC8C52G-LQ44I GC8C52G-P4I GC8C52G-SP28I GC8C52G-SO28I 8K ~5.5 4 (2) 3 UART YES PLCC 44-LQFP 4-PDIP 28-SPDIP 28-SOIC LVD POR Now Now Now Now Now GC8C32G-PL44I GC8C32G-LQ44I GC8C32G-P4I ROMless ~5.5 4 (2) 3 UART YES PLCC 44-LQFP 4-PDIP LVD POR Now Now Now * Operating frequency of MiDAS family is 4 MHz at 5. voltage. MiDAS2. Family [4]

5 . Product Overviews (Cont d) B. MiDAS. Family - GC8C52A Series (ADC Application MCU) Product Mask-ROM (byte) EPROM (byte) RAM (Byte) Volt (V) Freq. T/C (MHz) (6bits) Serial I/O WDT ADC PWM (bit x ch) (bit x ch) I/O Pins Package Others Available Time GC87C52A-PL44I GC87C52A-LQ44I GC87C52A-P4I GC87C52A-SP28I GC87C52A-SO28I - 8K ~5.5 4 (2) 3 UART YES 9x4 8x PLCC 44-LQFP 4-PDIP 28-SPDIP 28-SOIC LVD POR Now Now Now Now Now GC8C52A-PL44I GC8C52A-LQ44I GC8C52A-P4I GC8C52A-SP28I GC8C52A-SO28I 8K ~5.5 4 (2) 3 UART YES 9x4 8x PLCC 44-LQFP 4-PDIP 28-SPDIP 28-SOIC LVD POR Now Now Now Now Now GC8C32A-PL44I GC8C32A-LQ44I GC8C32A-P4I ROMless ~5.5 4 (2) 3 UART YES 9x4 8x PLCC 44-LQFP 4-PDIP LVD POR Now Now Now * Operating frequency of MiDAS. family is 4 MHz at 5. voltage. MiDAS2. Family [5]

6 . Product Overviews (Cont d) C. MiDAS. Family -GC8C5A Series (Low Cost ADC Application MCU) Product Mask-ROM (byte) EPROM (byte) RAM (Byte) Volt (V) Freq. T/C (MHz) (6bits) Serial I/O WDT ADC PWM (bit x ch) (bit x ch) I/O Pins Package Others Available Time GC87C5A-SP2I GC87C5A-SO2I GC87C5A-SP6I GC87C5A-SO6I GC87C5A-SP4I GC87C5A-SO4I GC87C5A-SP8I GC87C5A-SO8I - 4K ~5.5 2 () 2 UART x2 X2 X8 X8 X6 X6 X2 X2 8x SPDIP 2-SOIC 6-SPDIP 6-SOIC 4-SPDIP 4-SOIC 8-SPDIP 8-SOIC LVD POR Ring OSC Now Now Now Now Now Now Now Now GC87C5A-SO8I GC87C5A-SP8I - 4K ~5.5 2 () X3 2 UART 8x X3 6 8-SOIC 8-SPDIP LVD POR Ring OSC Now Now GC8C5A-SP2I GC8C5A-SO2I GC8C5A-SP6I GC8C5A-SO6I GC8C5A-SP4I GC8C5A-SO4I GC8C5A-SP8I GC8C5A-SO8I 4K ~5.5 2 () 2 UART x2 X2 X8 X8 X6 X6 X2 X2 8x SPDIP 2-SOIC 6-SPDIP 6-SOIC 4-SPDIP 4-SOIC 8-SPDIP 8-SOIC LVD POR Ring OSC Now Now Now Now Now Now Now Now GC8C5A-SO8I GC8C5A-SP8I 4K ~5.5 2 () X3 2 UART 8x X3 6 8-SOIC 8-SPDIP LVD POR Ring OSC Now Now * Operating frequency of MiDAS. family is 2 MHz at 5. voltage. MiDAS2. Family [6]

7 . Product Overviews (Cont d) D. MiDAS2. Family - GC8C59AE Series (ISP Flash MCU) Product EEPROM (byte) Mask-ROM (byte) Flash (byte) RAM (Byte) Volt (V) Freq. (MHz) T/C (6bits) Serial I/O ADC PWM WDT (bit x ch) (bit x ch) I/O Pins Package Others Available Time GC89C59A-TQC GC89C59A-TQ8C GC89C59A-P64C GC89C59A-TQ64C GC89C59A-PL44C GC89C59A-MQ44C 2K - 62K 2K 3.~ UART Yes X8 8x TQFP 8-TQFP 64-PDIP 64-TQFP 44-PLCC 44-MQFP ISP IAP EJTAG LVD POR Ring OSC. Now Now Now Now Now Now GC89C59G-PL44C GC89C59G-MQ44C 2K - 62K 2K 3.~ UART Yes - 8x PLCC 44-MQFP ISP IAP EJTAG LVD POR Ring OSC. Now Now GC8C59A-TQC GC8C59A-TQ8C GC8C59A-P64C GC8C59A-TQ64C GC8C59A-PL44C GC8C59A-MQ44C 2K 62K - 2K 3.~ UART Yes X8 8x TQFP 8-TQFP 64-PDIP 64-TQFP 44-PLCC 44-MQFP ISP IAP EJTAG LVD POR Ring OSC. Now Now Now Now Now Now GC8C59G-PL44C GC8C59G-MQ44C 2K 62K - 2K 3.~ UART Yes - 8x PLCC 44-MQFP ISP IAP EJTAG LVD POR Ring OSC. Now Now MiDAS2. Family [7]

8 Application with GenCore MiDAS MCU Families MiDAS2. Family [8]

9 2. Features CPU 8-bit turbo 8C52 architecture 4 cycles/ machine cycle Pin/instruction level compatible with Intel 8C52 62 KBytes FLASH ISP by serial interface IAP and virtual EEPROM for data (2KByte) On-chip H/W debug engine for ICE. 2 KBytes RAM 256 bytes IRAM,792 bytes AUXRAM (Accessed with MOVX) EMI reduction mode : Optional ALE disable Low Voltage Detector 27-bit Programmable Watchdog Timer Three 6-bit Timer/Counters Two Full-Duplex UART Automatic address recognition 2 PWM outputs provided by two 6-module Programmable Counter Arrays 8-bit dynamic PWM (2 channels). 6-bit Compare/Capture counter (2 channels). High Speed Output (2 channels). Fully programmable 8 I/O pins (for -TQFP) Quasi-bidirectional intel type ports : P ~ P4 Input/Output and pull-up control : P5 ~ P9 TTL & CMOS compatible logic levels : P ~ P3 CMOS levels : P4 ~ P9 All ports are initialized with asynchronous reset on power up. 8-channel -bit ADC Max 4K sample per second (@4 MHz) Programmable input clock frequency 6 interrupt sources (with 6 external sources) Timer//2, UART/, PCA/, ADC, WDT, LVD, and 6 External Four/Two-level interrupt priority MiDAS2. Family [9]

10 2. Features (Cont d) Wake-up from power-down External reset External interrupt / WDT interrupt or reset Reset scheme On-chip power-on-reset External reset Low voltage detector reset Optional Watchdog timer reset Internal power stabilization counter Extends power on reset up to 5ms. 3.V to 3.6V supply voltage Operating temperature : C to 7 C On-chip oscillator with external crystal Max. 4 MHz internal operating frequency Internal Ring oscillator running at 2.8 MHz Power consumption Active current : Max 3.3V, 4MHz Stop current : Typ. 2 ua (Max. ua) E.S.D. protection greater than 2,V Latch-up protection greater than 2mA Package 44-PLCC/MQFP (A/G) 64-PDIP/TQFP 8-TQFP -TQFP MiDAS2. Family []

11 3. Block Diagram RESET XTAL XTAL2 P3[7:] P2[7:] P[7:] P[7:] RESET External Osc. Internal Ring Osc. WDT Port Controller Interrupt Controller MDS Controller ISP/IAP Controller MDS_SCK MDS_SDA TURBO 8C52 CORE CPU BUS LVD RAM (2KB) FLASH (62KB) EEPROM (2KB) Timer Timer Timer2 UART UART PCA (PWM) PCA (PWM) ALE PSEN VDD EA VSS [ 44-PLCC/MQFP, G-type ] MiDAS2. Family []

12 3. Block Diagram (Cont d) RESET XTAL XTAL2 P3[7:] P2[7:] P[7:] P[7:] RESET External Osc. Internal Ring Osc. WDT Port Controller ADC x 8 Interrupt Controller MDS Controller ISP/IAP Controller MDS_SCK MDS_SDA TURBO 8C52 CORE CPU BUS LVD RAM (2KB) FLASH (62KB) EEPROM (2KB) Timer Timer Timer2 UART UART PCA (PWM) PCA (PWM) ALE PSEN VDD EA VSS [ 44-PLCC/MQFP, A-type ] * PKGOPT (IOCFG.) flag bit must be set to. MiDAS2. Family [2]

13 3. Block Diagram (Cont d) RESET XTAL XTAL2 P5[7:] P4[7:] P3[7:] P2[7:] P[7:] P[7:] RESET External Osc. Internal Ring Osc. WDT Port Controller ADC x 8 Interrupt Controller MDS Controller ISP/IAP Controller MDS_SCK MDS_SDA TURBO 8C52 CORE CPU BUS LVD RAM (2KB) FLASH (62KB) EEPROM (2KB) Timer Timer Timer2 UART UART PCA (PWM) PCA (PWM) ALE PSEN VDD EA VSS [ 64-PDIP/TQFP ] MiDAS2. Family [3]

14 3. Block Diagram (Cont d) RESET XTAL XTAL2 P7[5:] P6[7:] P5[7:] P4[7:] P3[7:] P2[7:] P[7:] P[7:] RESET External Osc. Internal Ring Osc. WDT Port Controller ADC x 8 Interrupt Controller MDS Controller ISP/IAP Controller MDS_SCK MDS_SDA TURBO 8C52 CORE CPU BUS LVD RAM (2KB) FLASH (62KB) EEPROM (2KB) Timer Timer Timer2 UART UART PCA (PWM) PCA (PWM) ALE PSEN VDD EA VSS [ 8-TQFP ] MiDAS2. Family [4]

15 3. Block Diagram (Cont d) RESET XTAL XTAL2 P9[7:] P8[7:] P7[5:] P6[7:] P5[7:] P4[7:] P3[7:] P2[7:] P[7:] P[7:] RESET External Osc. Internal Ring Osc. WDT Port Controller ADC x 8 Interrupt Controller MDS Controller ISP/IAP Controller MDS_SCK MDS_SDA TURBO 8C52 CORE CPU BUS LVD RAM (2KB) FLASH (62KB) EEPROM (2KB) Timer Timer Timer2 UART UART PCA (PWM) PCA (PWM) ALE PSEN VDD EA VSS [ -TQFP ] MiDAS2. Family [5]

16 VDD P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX3 P.4 / INT2 P.3 P.2 P. / T2EX P. / T2 NC [6] MiDAS2. Family 4. Pin Configurations INT3 / P P.4 / AD4 / CEX4 INT4 / P P.5 / AD5 / CEX5 INT5 / P P.6 / AD6 / ECI RESET 36 P.7 / AD7 / ECI RXD / P3. 35 EA MDS_SDA 2 34 MDS_SCK GC89C59G-PL44C TXD / P ALE / PROG INT / P PSEN INT / P P2.7 / A5 / TXD T / P P2.6 / A4 / RXD T / P P2.5 / A3 / CEX5 WR / P3.6 RD / P3.7 XTAL2 XTAL VSS NC CEX / A8 / P2. CEX / A9 / P2. CEX2 / A / P2.2 CEX3 / A / P2.3 CEX4 / A2 / P2.4 P.4 / INT2 P.3 P.2 P. / T2EX P. / T2 NC VDD P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX3 [ 44-PLCC, G-type ] INT3 / P.5 33 / CEX4 32 / CEX5 3 / ECI 3 / ECI P.4 / AD4 INT4 / P.6 2 P.5 / AD5 INT5 / P.7 3 P.6 / AD6 RESET 4 P.7 / AD7 RXD / P3. 5 EA MDS_SDA 6 MDS_SCK ALE / PROG PSEN P2.7 / A5 / TXD 25 9 P2.6 / A4 / RXD P2.5 / A3 / CEX5 24 GC89C59G-MQ44C 23 TXD / P3. INT / P3.2 INT / P3.3 T / P3.4 T / P NC CEX / A8 / P2. CEX / A9 / P2. CEX2 / A / P2.2 CEX3 / A / P2.3 CEX4 / A2 / P2.4 VSS WR / P3.6 RD / P3.7 XTAL2 XTAL : 5V Tolerant Input (3.3V Output) : 3.3V Tolerant Input (3.3V Output) [ 44-MQFP, G-type ]

17 VDD P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX3 P.4 / INT2 / ADC4 P.3 / ADC3 P.2 / ADC2 P. / T2EX / ADC P. / T2 / ADC NC 4. Pin Configurations (Cont d) [7] MiDAS2. Family ADC5 / INT3 / P P.4 / AD4 / CEX4 ADC6 / INT4 / P P.5 / AD5 / CEX5 ADC7 / INT5 / P P.6 / AD6 / ECI RESET 36 P.7 / AD7 / ECI RXD / P3. 35 EA MDS_SDA 2 34 MDS_SCK GC89C59A-PL44C TXD / P ALE / PROG INT / P PSEN INT / P P2.7 / A5 / TXD T / P P2.6 / A4 / RXD T / P P2.5 / A3 / CEX5 [ 44-MQFP, A-type ] WR / P3.6 RD / P3.7 XTAL2 XTAL VSS NC CEX / A8 / P2. CEX / A9 / P2. CEX2 / A / P2.2 CEX3 / A / P2.3 CEX4 / A2 / P2.4 P.4 / INT2 / ADC4 P.3 / ADC3 P.2 / ADC2 P. / T2EX / ADC P. / T2 / ADC NC VDD P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX ADC5 / INT3 / P P.4 / AD4 / CEX4 ADC6 / INT4 / P.6 2 P.5 / AD5 / CEX5 ADC7 / INT5 / P.7 3 P.6 / AD6 / ECI RESET 4 P.7 / AD7 / ECI RXD / P3. 5 EA MDS_SDA 6 MDS_SCK TXD / P3. 7 ALE / PROG INT / P3.2 8 PSEN INT / P3.3 9 P2.7 / A5 / TXD T / P3.4 P2.6 / A4 / RXD T / P3.5 P2.5 / A3 / CEX5 [ 44-PLCC, A-type ] GC89C59A-MQ44C NC CEX / A8 / P2. CEX / A9 / P2. CEX2 / A / P2.2 CEX3 / A / P2.3 CEX4 / A2 / P2.4 VSS WR / P3.6 RD / P3.7 XTAL2 XTAL : 5V Tolerant Input (3.3V Output) : 3.3V Tolerant Input (3.3V Output)

18 4. Pin Configurations (Cont d) T2EX / P. P.2 P.3 ADC / P4. ADC / P4. ADC2 / P4.2 ADC3 / P4.3 ADC4 / P4.4 ADC5 / P4.5 ADC6 / P4.6 ADC7 / P4.7 INT2 / P.4 INT3 / P.5 INT4 / P.6 INT5 / P.7 RESET V DD V SS RXD / P3. MDS_SDA TXD / P3. INT / P3.2 INT / P3.3 T / P3.4 T / P3.5 WR / P3.6 RD / P3.7 XTAL2 XTAL V SS AV SS P GC89C59A-P64C P./ T2 AV DD V DD P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX3 P.4 / AD4 / CEX4 P.5 / AD5 / CEX5 P.6 / AD6 / ECI P.7 / AD7 / ECI V DD V SS EA MDS_SCK ALE / PROG PSEN P5.7 P5.6 P5.5 P5.4 P2.7 / A5 / TXD P2.6 / A4 / RXD P2.5 / A3 / CEX5 P2.4 / A2 / CEX4 P2.3 / A / CEX3 P2.2 / A / CEX2 P2. / A9 / CEX P2. / A8 / CEX P5.3 P5.2 P5. : 5V Tolerant Input (3.3V Output) : 3.3V Tolerant Input (3.3V Output) ADC5 / P4.5 ADC6 / P4.6 ADC7 / P4.7 INT2 / P.4 INT3 / P.5 INT4 / P.6 INT5 / P.7 RESET V DD V SS RXD / P3. MDS_SDA TXD / P3. INT / P3.2 INT / P3.3 T / P T / P3.5 P4.4 / ADC4 WR / P3.6 P4.3 / ADC3 RD / P3.7 P4.2 / ADC2 P4. / ADC P4. / ADC XTAL2 XTAL P.3 P.2 P. P. V SS AV DD V DD AV SS P5. P5. P5.2 P5.3 P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX3 P.4 / AD4 / CEX GC89C59A-TQ64C CEX / A8 / P2. CEX / A9 / P2. CEX2 / A / P2.2 CEX3 / A / P2.3 CEX4 / A2 / P P.5 / AD5 / CEX5 P.6 / AD6 / ECI P.7 / AD7 / ECI V DD V SS EA MDS_SCK ALE / PROG PSEN P5.7 P5.6 P5.5 P5.4 P2.7 / A5 / TXD P2.6 / A4 / RXD P2.5 / A3 / CEX5 [ 64-PDIP ] [ 64-TQFP ] MiDAS2. Family [8]

19 P.5 / AD5 / CEX5 P.6 / AD6 / ECI P.7 / AD7 / ECI P6.3 P6.2 P6. P6. V DD V SS 4. Pin Configurations (Cont d) EA MDS_SCK ALE / PROG PSEN P5.7 P5.6 P5.5 P5.4 P2.7 / A5 / TXD P2.6 / A4 / RXD P2.5 / A3 / CEX5 MiDAS2. Family [9] P.4 / AD4 / CEX4 P.3 / AD3 / CEX3 P.2 / AD2 / CEX2 P. / AD / CEX P. / AD / CEX : 5V Tolerant Input (3.3V Output) : 3.3V Tolerant Input (3.3V Output) P6.4 P6.5 P6.6 P6.7 VDD AVDD P. P. P.2 P.3 P4. / ADC P4. / ADC ADC5 / P4.5 ADC6 / P4.6 ADC7 / P4.7 RESET RXD / P3. MDS_SDA P7. P7. P7.2 P7.3 TXD / P3. INT / P3.2 INT / P3.3 T / P3.4 CEX4 / A2 / P2.4 CEX3 / A / P2.3 CEX2 / A / P2.2 CEX / A9 / P2. CEX / A8 / P2. VSS XTAL XTAL2 RD / P3.7 P4.2 / ADC2 P4.3 / ADC3 P4.4 / ADC INT2 / P.4 INT3 / P.5 INT4 / P.6 INT5 / P.7 GC89C59A-TQ8C V DD V SS P5.3 P5.2 P5. AVSS P5. P7.7 P7.6 P7.5 P7.4 [ 8-TQFP ] WR / P3.6 T / P3.5

20 P.5 / AD5 / CEX5 P.6 / AD6 / ECI P.7 / AD7 / ECI P6.3 P6.2 P6. P6. 4. Pin Configurations (Cont d) P.4 / AD4 / CEX4 V DD V SS EA MDS_SCK ALE / PROG PSEN P9.7 P9.6 P9.5 P9.4 P5.7 P5.6 P5.5 P5.4 P2.7 / A5 / TXD P2.6 / A4 / RXD P2.5 / A3 / CEX5 MiDAS2. Family [2] P6.4 P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX3 : 5V Tolerant Input (3.3V Output) : 3.3V Tolerant Input (3.3V Output) P6.7 P6.6 P6.5 P8. P8. P8.2 P8.3 VDD AVDD VSS VDD P4.4 / ADC4 P4.3 / ADC3 P4.2 / ADC2 P4. / ADC P4. / ADC P.3 P.2 P. P ADC5 / P4.5 ADC6 / P4.6 ADC7 / P INT2 / P.4 INT3 / P.5 INT4 / P.6 INT5 / P.7 8 RESET GC89C59A-TQC 9 2 P8.4 P8.5 P8.6 P V DD V SS 5 6 RXD / P3. MDS_SDA P7. P7. P7.2 P TXD / P3. INT / P3.2 INT / P3.3 T / P T / P P5. P5. P5.2 P5.3 CEX / A8 / P2. CEX / A9 / P2. CEX2 / A / P2.2 CEX3 / A / P2.3 CEX4 / A2 / P2.4 VSS VDD AVSS VSS P9. P9. P9.2 P9.3 XTAL2 XTAL [ -TQFP ] P7.4 P7.5 P7.6 P7.7 WR / P3.6 RD / P3.7

21 5. Pin Descriptions Symbol Direction Description Share Pins V DD Input Voltage Power Source - AV DD Input Voltage Power Source for ADC - V SS Input Voltage Power Ground - AV SS Input Voltage Power Ground for ADC - RESET Input External Reset - XTAL Input External Crystal Input - XTAL2 Output External Crystal Output - EA Input External ROM Access Enable (MiDAS2. family dose not use this pin.) - ALE Input/Output Address Latch Enable (If ALEOFF is set, active only for external RAM access) This pin is also used for the parallel programming of FLASH memory. PROG PSEN Input/Output Program Strobe Enable. Pull-up. Used for Special Input only. (MiDAS2. does not support the code fetch from external ROM.) - MDS_SDA, MDS_SCK Input/Output I/O for MDS/ISP. Pull-up resistor is always on. This port is quasi-bidirectional. - P[7:] Input/Output 5V Tolerant Input and Open-Drain Output. The Address/Data to access external RAM and PCA Output is fully driven. P. ~ P.7 AD ~ AD7 : Low address or data input/output P. ~ P.5 CEX ~ CEX5 for PCA P.6 ECI for PCA P.7 ECI for PCA P. / AD / CEX P. / AD / CEX P.2 / AD2 / CEX2 P.3 / AD3 / CEX3 P.4 / AD4 / CEX4 P.5 / AD5 / CEX5 P.6 / AD6 / ECI P.7 / AD7 / ECI MiDAS2. Family [2]

22 5. Pin Descriptions (Cont d) Symbol Direction Description Share Pins 5V Tolerant Input and Quasi-bidirectional Port. 44 pins G-type, and 64/8/ pins Package : General I/O. P. T2 : External Input for Timer/Counter 2 P. T2EX : Timer/Counter 2 Capture/Reload Trigger P.4 INT2 : External Interrupt 2 (Positive Edge) P.5 INT3 : External Interrupt 3 (Negative Edge) P.6 INT4 : External Interrupt 4 (Positive Edge) P.7 INT5 : External Interrupt 5 (Negative Edge) P. / T2 P. / T2EX P.4 / INT2 P.5 / INT3 P.6 / INT4 P.7 / INT5 3.3V Tolerant Input and Quasi-bidirectional Port. 44 pins A-type : Port for Digital I/O or ADC Input (3.3V). P[7:] Input/Output P. T2 : External Input for Timer/Counter 2 P. T2EX : Timer/Counter 2 Capture/Reload Trigger P.4 INT2 : External Interrupt 2 (Positive Edge) P.5 INT3 : External Interrupt 3 (Negative Edge) P.6 INT4 : External Interrupt 4 (Positive Edge) P.7 INT5 : External Interrupt 5 (Negative Edge) P. ADC : A/D converter Input P. ADC : A/D converter Input P.2 ADC2 : A/D converter Input 2 P.3 ADC3 : A/D converter Input 3 P.4 ADC4 : A/D converter Input 4 P.5 ADC5 : A/D converter Input 5 P.6 ADC6 : A/D converter Input 6 P.7 ADC7 : A/D converter Input 7 P. / T2 / ADC P. / T2EX / ADC P.2 / ADC2 P.3 / ADC3 P.4 / INT2 / ADC4 P.5 / INT3 / ADC5 P.6 / INT4 / ADC6 P.7 / INT5 / ADC7 MiDAS2. Family [22]

23 5. Pin Descriptions (Cont d) Symbol Direction Description Share Pins P2[7:] Input/Output 5V Tolerant Input and Quasi-bidirectional Port. P2.~P2.7 AD8 ~ AD5 : High address output P2.~P2.5 CEX ~ CEX5 for PCA P2.6 RXD : Serial Port Output P2.7 TXD : Serial Port Input P2. / AD8 / CEX P2. / AD9 / CEX P2.2 / AD / CEX2 P2.3 / AD / CEX3 P2.4 / AD2 / CEX4 P2.5 / AD3 / CEX5 P2.6 / AD4 / RXD P2.7 / AD5 / TXD P3[7:] Input/Output 5V Tolerant Input and Quasi-bidirectional Port. P3. RXD : Serial Port Input P3. TXD : Serial Port Output P3.2 INT : External Interrupt Input P3.3 INT : External Interrupt Input P3.4 T : Timer External Input P3.5 T : Timer External Input P3.6 WR : External Data Memory Writer Strobe P3.7 RD : External Data Memory Read Strobe P3. / RXD P3. / TXD P3.2 / INT P3.3 / INT P3.4 / T P3.5 / T P3.6 / WR P3.7 / RD P4[7:] Input/Output 3.3V Operation and Quasi-bidirectional Port. Port for digital I/O or ADC Input (3.3V). P4. ADC : A/D converter Input P4. ADC : A/D converter Input P4.2 ADC2 : A/D converter Input 2 P4.3 ADC3 : A/D converter Input 3 P4.4 ADC4 : A/D converter Input 4 P4.5 ADC5 : A/D converter Input 5 P4.6 ADC6 : A/D converter Input 6 P4.7 ADC7 : A/D converter Input 7 P4. / ADC P4. / ADC P4.2 / ADC2 P4.3 / ADC3 P4.4 / ADC4 P4.5 / ADC5 P4.6 / ADC6 P4.7 / ADC7 MiDAS2. Family [23]

24 5. Pin Descriptions (Cont d) Symbol Direction Description Share Pins P5[7:] Input/Output 3.3V Operation Programmable I/O Port for Schmitt Trigger Input or Push-pull Output. Internal Pull-up Resistor may be enabled/disabled by S/W. On Reset, configured as Input with Pull-up Resistor. - P6[7:] Input/Output 3.3V Operation Programmable I/O Port for Schmitt Trigger Input or Push-pull Output. Internal Pull-up Resistor may be enabled/disabled by S/W. On Reset, configured as Input with Pull-up Resistor. - P7[7:] Input/Output 3.3V Operation Programmable I/O Port for Schmitt Trigger Input or Push-pull Output. Internal Pull-up Resistor may be enabled/disabled by S/W. On Reset, configured as Input with Pull-up Resistor. - P8[7:] Input/Output 3.3V Operation Programmable I/O Port for Schmitt Trigger Input or Push-pull Output. Internal Pull-up Resistor may be enabled/disabled by S/W. On Reset, configured as Input with Pull-up Resistor. - P9[7:] Input/Output 3.3V Operation Programmable I/O Port for Schmitt Trigger Input or Push-pull Output. Internal Pull-up Resistor may be enabled/disabled by S/W. On Reset, configured as Input with Pull-up Resistor. - MiDAS2. Family [24]

25 6.. Memory Organization FFFFh F8h F7FFh On-chip Program Memory h ROM (ISP/MDS) Internal FLASH Interrupt Vector 3h 2h 8 x 8 bits (Scratch Pad) 6 x 8 bits (28 bits) Bit Addressable 8h R R R2 R3 R4 R5 R6 R7 h R R R2 R3 R4 R5 R6 R7 8h R R R2 R3 R4 R5 R6 R7 h R R R2 R3 R4 R5 R6 R7 7Fh 2Fh BANK3 BANK2 BANK BANK FFh 8h 7Fh h Internal RAM (Only Indirect) Internal RAM (Indirect or Direct) On-chip Data Memory Refer to Family Table SFR (Only Direct) FFFFh F8h 6FFh h EEPROM Refer to Next Slide. (SFR Map) Internal RAM (MOVX) F7FFh Off-chip Data Memory 7h External RAM WR RD [ On-chip Program Memory ] (Read/Write with IAP) [ On-chip Data Memory ] (Read and Write) [ Off-chip Data Memory ] (Read and Write) MiDAS2. Family [25]

26 6.2. SFR (Special Function Register) Map Refer to Family Table Bit addressable : Newly added SFR at MiDAS2. Family : Reserved for future use. FFh 8h h Internal RAM (Only Indirect) Internal RAM (Indirect or Direct) SFR (Only Direct) F8h EIP FFh Fh B FAEN F7h E8h EIE P9PUP CL CH ADCHEN ADCSEL ADCR ADCON EFh Eh ACC P8PUP CCAPM CCAPM CCAPM2 CCAPM3 CCAPM4 CCAPM5 E7h D8h WDCON P7PUP CCAPH CCAPH CCAP2H CCAP3H CCAP4H CCAP5H DFh Dh PSW CCAPL CCAPL CCAP2L CCAP3L CCAP4L CCAP5L D7h C8h T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CCON CMOD CFh Ch P4 P5PUP P6PUP PMR STATUS OSCICN IOCFG C7h B8h IP SADEN P5DIR P6DIR P7DIR P8DIR P9DIR AUXAD BFh Bh P3 SCON P5 P6 P7 P8 P9 IPH B7h A8h IE SADDR SADDR SADEN CCON CMOD CL CH AFh Ah P2 SBUF CCAPM CCAPM CCAPM2 CCAPM3 CCAPM4 CCAPM5 A7h 98h SCON SBUF CCAPH CCAPH CCAP2H CCAP3H CCAP4H CCAP5H 9Fh 9h P EXIF CCAPL CCAPL CCAP2L CCAP3L CCAP4L CCAP5L 97h 88h TCON TMOD TL TL TH TH CKCON 8Fh 8h P SP DPL DPH PCON 87h (for -TQFP) MiDAS2. Family [26]

27 6.2. SFR Brief Description 8C52 SFR Registers Newly added SFR Registers in MiDAS2. Family Register Name Reset Value ACC B PSW SP DPTR DPL DPH P P P2 P3 IP IPH IE TCON TMOD T2CON T2MOD TH TL TH TL TH2 TL2 RCAP2H RCAP2L SCON SBUF SADEN SADDR Accumulator B Register Program Status Word Stack Pointer Data Pointer (2 bytes) Low byte High byte Port Port Port 2 Port 3 Interrupt Priority Low Interrupt Priority High Interrupt Enable Control T/C / Control T/C / Mode Control T/C 2 Control T/C 2 Mode Selection T/C High byte T/C Low byte T/C High byte T/C Low byte T/C 2 High byte T/C 2 Low byte T/C 2 Capture Reg. High byte T/C 2 Capture Reg. Low byte Serial Port Control of UART Serial Data Buffer of UART Slave Address Mask Enable of UART Slave Address of UART ****** PCON Power Control * Register Name Reset Value P5PUP P6PUP P7PUP P8PUP P9PUP P5DIR P6DIR P7DIR P8DIR P9DIR P4 P5 P6 P7 P8 P9 SCON SBUF SADDR SADEN ADCON ADCR ADCSEL ADCHEN EIP EIE Port 5 Pull-up Control Port 6 Pull-up Control Port 7 Pull-up Control Port 8 Pull-up Control Port 9 Pull-up Control Port 5 Input/Output Control Port 6 Input/Output Control Port 7 Input/Output Control Port 8 Input/Output Control Port 9 Input/Output Control Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Serial Port Control of UART Serial Data Buffer of UART Slave Address of UART Slave Address Mask Enable of UART AUXAD High Address for MOVX with Ri WDCON Watchdog Timer & Power Status * FAEN IAP Routine Access Enable ******* * : Don t touch bit. ADC Control & ADC Result Low ADC Result High ADC Clock & MUX Selection ADC Input Channel Enable Extended Interrupt Priority Extended Interrupt Enable ** ** MiDAS2. Family [27]

28 6.2. SFR Brief Description (Cont d) Newly added SFR Registers in MiDAS2. Family (Cont d) Register Name Reset Value Register Name Reset Value PMR EXIF CKCON STATUS OSCICN IOCFG CL CH CCON CMOD Power Management External Interrupt Flag Clock Control Crystal Status Internal RING Oscillator Control I/O Configuration Low Byte of PCA Counter High Byte of PCA Counter PCA Counter Control PCA Counter Mode ****** * ******* ***** ****** * CL CH CCON CMOD CCAPM CCAPM CCAPM2 CCAPM3 CCAPM4 CCAPM5 Low Byte of PCA Counter High Byte of PCA Counter PCA Counter Control PCA Counter Mode Mode Control of PCA MODULE Mode Control of PCA MODULE Mode Control of PCA MODULE2 Mode Control of PCA MODULE3 Mode Control of PCA MODULE4 Mode Control of PCA MODULE5 * CCAPM CCAPM CCAPM2 CCAPM3 CCAPM4 CCAPM5 Mode Control of PCA MODULE Mode Control of PCA MODULE Mode Control of PCA MODULE2 Mode Control of PCA MODULE3 Mode Control of PCA MODULE4 Mode Control of PCA MODULE5 CCAPL CCAPL CCAP2L CCAP3L CCAP4L CCAP5L Low Capture/Compare of PCA MODULE Low Capture/Compare of PCA MODULE Low Capture/Compare of PCA MODULE2 Low Capture/Compare of PCA MODULE3 Low Capture/Compare of PCA MODULE4 Low Capture/Compare of PCA MODULE5 CCAPL CCAPL CCAP2L CCAP3L CCAP4L CCAP5L Low Capture/Compare of PCA MODULE Low Capture/Compare of PCA MODULE Low Capture/Compare of PCA MODULE2 Low Capture/Compare of PCA MODULE3 Low Capture/Compare of PCA MODULE4 Low Capture/Compare of PCA MODULE5 CCAPH CCAPH CCAP2H CCAP3H CCAP4H CCAP5H High Capture/Compare of PCA MODULE High Capture/Compare of PCA MODULE High Capture/Compare of PCA MODULE2 High Capture/Compare of PCA MODULE3 High Capture/Compare of PCA MODULE4 High Capture/Compare of PCA MODULE5 CCAPH CCAPH CCAP2H CCAP3H CCAP4H CCAP5H High Capture/Compare of PCA MODULE High Capture/Compare of PCA MODULE High Capture/Compare of PCA MODULE2 High Capture/Compare of PCA MODULE3 High Capture/Compare of PCA MODULE4 High Capture/Compare of PCA MODULE5 * : Don t touch bit. MiDAS2. Family [28]

29 6.3. Instruction Set Summary Refer to Appendix A (Instruction Set) for more details. Type Instruction Description Type Instruction Description Arithmetic Logical Data Transfer ADD ADDC SUBB INC DEC MUL DIV DA ANL ORL XRL CLR CPL RL RLC RR RRC SWAP MOV MOVC MOVX PUSH POP XCH XCHD Addition Addition with Carry Subtraction with Borrow Increment Decrement Multiply Divide Decimal Adjust AND OR Exclusive OR Clear Complement Rotate Left Rotate Left with Carry Rotate Right Rotate Right with Carry Swap Nibbles Move Data Move Code Move Data to Ext. RAM PUSH POP Exchange Exchange Low-digit Boolean Branch CLR SETB CPL ANL ORL MOV JC JNC JB JNB JBC ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ CJNE DJNZ NOP Clear bit Set bit Complement bit AND bit OR bit Move bit Jump if Carry is set Jump if Carry is not set Jump if bit is set Jump if bit is not set Jump if bit is set & clear Absolute Call Long Call Return from Subroutine Return from Interrupt Absolute Jump Long Jump Short Jump Jump with DPTR Jump if ACC is zero Jump if ACC is not zero Compare and Jump if not equal Decrement and Jump if not zero No Operation MiDAS2. Family [29]

30 6.4. CPU Timing Comparative timing of the MiDAS2. family and Intel 8C52 XTAL GenCore GC8C52 IR ALE PSEN PORT PORT2 INST INST INST2 INST3 INST ADDL_ INST ADDL_2 INST2 ADDL_3 INST3 ADDH_ ADDH_ ADDH_2 ADDH_3 S S2 S3 S4 -byte -machine Cycle Instruction (4 clocks) -byte -machine Cycle Instruction (2 clocks) S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 XTAL Intel 8C52 IR ALE INST INST INST2 PSEN PORT ADDL_2 INST2 ADDL_2 INST2 ADDL_22 INST22 PORT2 ADDH_2 ADDH_2 ADDH_22 MiDAS2. Family [3]

31 6.4. CPU Timing : MOVX Write Timing st Machine Cycle 2nd Machine Cycle 3rd Machine Cycle S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 XTAL IR ALE PSEN WR INST INST MOVX Write Instruction INST2 PORT INST ADDL_ MOVX ADDL_2 INST2 XRAM_L MOVX Write Data ADDL_3 INST3 MOVX write data MOVX address PORT2 ADDH_ ADDH_ ADDH_2 XRAM_H ADDH_3 MiDAS2. Family [3]

32 6.4. CPU Timing : MOVX Read Timing st Machine Cycle 2nd Machine Cycle 3rd Machine Cycle S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 XTAL IR ALE PSEN RD INST INST MOVX Read Instruction INST2 PORT INST ADDL_ MOVX ADDL_2 INST2 XRAM_L MOVX Read Data ADDL_3 INST3 MOVX read data MOVX address PORT2 ADDH_ ADDH_ ADDH_2 XRAM_H ADDH_3 MiDAS2. Family [32]

33 6.4. CPU Timing : Execution Time Table Fastest instruction execution time in the world Instruction GC8C59 (GenCore) W77C32 (Winbond) DS8C32 (Maxim) 87C52 (Intel) MUL AB DIV AB 2 clocks 2 clocks 2 clocks 48 clocks MOVC MOVC 8 clocks 8 clocks 2 clocks 24 clocks 8 clocks 8 clocks 2 clocks 24 clocks RET RETI 8 clocks 8 clocks 6 clocks 24 clocks INC DPTR DEC DPTR 4 clocks 4 clocks 8 clocks 8 clocks 2 clocks Not exist 24 clocks Not exist Others Same Same Same - MiDAS2. Family [33]

34 6.5. I/O Ports : PORT[7:] 5V tolerant input and open-drain output as default (Intel 852 compatible). When external access, P register will automatically set to FFh. Read-Modify-Write instructions do not read port pin but SFR register. ANL / OPL / XRL / JBC / CPL / INC / DEC / DJNZ / MOV PX.Y, C / CLR PX.Y / SETB PX.Y Alternative input function (PCA and PCA input pins) CEX(P.), CEX(P.), CEX2(P.2), CEX3(P.3), CEX4(P.4), CEX5(P.5), ECI(P.6), ECI(P.7) PORT Description P (8h) : PORT Register P.7 P.6 P.5 P.4 P.3 P.2 P. P. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() External Address/Data CPU BUS Q P. SFR QB P. External Access Digital Input MiDAS2. Family [34]

35 6.5. I/O Ports : PORT[7:] (Except 44-pin A-type) 5V tolerant input and quasi-bidirectional port (Intel 852 compatible). Read-Modify-Write instructions do not read port pin but SFR register. ANL / OPL / XRL / JBC / CPL / INC / DEC / DJNZ / MOV PX.Y, C / CLR PX.Y / SETB PX.Y Alternative input function is available when SFR bit is. P. = T2 / P. = T2EX / P.4 = INT2 / P.5 = INT3 / P.6 = INT4 / P.7 = INT5 PORT Description P (9h) : PORT Register P.7 P.6 P.5 P.4 P.3 P.2 P. P. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Alternative Function Output CPU BUS Q P. SFR QB 2 OSC Pulse Pullup P. Digital Input MiDAS2. Family [35]

36 6.5. I/O Ports : PORT[7:] (44-pin A-type) 3.3V operation ADC input and quasi-bidirectional port (Intel 852 compatible). Alternative input function is available when SFR bit is. But ADC input function don t care the state of SFR value. P. = T2 / P. = T2EX / P.4 = INT2 / P.5 = INT3 / P.6 = INT4 / P.7 = INT5 ADC(P.), ADC(P.), ADC2(P.2), ADC3(P.3), ADC4(P.4), ADC5(P.5), ADC6(P.6), ADC7(P.7) To use the digital I/O and alternative function of P, user must set PKGOPT bit (IOCFG.). PORT Description of 44-pin A-type ADCHEN (ECh) : ADC Input Channel Enable Register ADCHEN.7 ADCHEN.6 ADCHEN.5 ADCHEN.4 ADCHEN.3 ADCHEN.2 ADCHEN. ADCHEN. ADCHEN.X P (9h) : PORT Register : ADC Input Channel Enable = ADC input disable / Pull-up Resistor ON (Default) = ADC input enable / Pull-up Resistor OFF P.7 P.6 P.5 P.4 P.3 P.2 P. P. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Alternative Function Output CPU BUS Q P. SFR QB 2 OSC Pulse Pullup ADCHEN. P. IOCFG (C7h) : I/O Configuration Register ENAUX - - PKGOPT Digital Input ADC Block Input PKGOPT : Configure ports for 44-pin A/G-type package. = G-type (General purpose version) = A-type (ADC version) ADCHEN. MiDAS2. Family [36]

37 6.5. I/O Ports : PORT2[7:] 5V tolerant input and quasi-bidirectional port (Intel 852 compatible). Read-Modify-Write instructions do not read port pin but SFR register. ANL / OPL / XRL / JBC / CPL / INC / DEC / DJNZ / MOV PX.Y, C / CLR PX.Y / SETB PX.Y Alternative input function is available when SFR bit is. High address output when external RAM access PCA inputs : CEX(P2.), CEX(P2.), CEX2(P2.2), CEX3(P2.3), CEX4(P2.4), CEX5(P2.5) UART : RXD(P2.6), TXD(P2.7) PORT 2 Description P2 (Ah) : PORT 2 Register P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2. P2. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Alternative Function Output CPU BUS Q P2. SFR QB 2 OSC Pulse Pullup P2. Digital Input MiDAS2. Family [37]

38 6.5. I/O Ports : PORT3[7:] 5V tolerant input and quasi-bidirectional port (Intel 852 compatible). Read-Modify-Write instructions do not read port pin but SFR register. ANL / OPL / XRL / JBC / CPL / INC / DEC / DJNZ / MOV PX.Y, C / CLR PX.Y / SETB PX.Y Alternative input function is available when SFR bit is. P3. = RXD / P3. = TXD / P3.2 = INT / P3.3 = INT / P3.4 = T / P3.5 = T / P3.6 = WR / P3.7 = RD PORT 3 Description P3 (Bh) : PORT 3 Register P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3. P3. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Alternative Function Output CPU BUS Q P3. SFR QB 2 OSC Pulse Pullup P3. Digital Input MiDAS2. Family [38]

39 6.5. I/O Ports : PORT4[7:] 3.3V operation and quasi-bidirectional port (Intel 852 compatible). ADC input channel and Digital Input/Output. Read-Modify-Write instructions do not read port pin but SFR register. ANL / OPL / XRL / JBC / CPL / INC / DEC / DJNZ / MOV PX.Y, C / CLR PX.Y / SETB PX.Y Alternative input function (ADC input pins) ADC(P4.), ADC(P4.), ADC2(P4.2), ADC3(P4.3), ADC4(P4.4), ADC5(P4.5), ADC6(P4.6), ADC7(P4.7) PORT 4 Description ADCHEN (ECh) : ADC Input Channel Enable ADCHEN.7 ADCHEN.6 ADCHEN.5 ADCHEN.4 ADCHEN.3 ADCHEN.2 ADCHEN. ADCHEN. ADCHEN.X P4 (Ch) : PORT 4 Register : ADC Input Channel Enable = ADC input disable / Pull-up Resistor ON (Default) = ADC input enable / Pull-up Resistor OFF P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4. P4. Alternative Function Output CPU BUS Q P4. SFR QB 2 OSC Pulse Pullup ADCHEN. P4. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Digital Input ADC Block Input ADCHEN. MiDAS2. Family [39]

40 6.5. I/O Ports : PORT5[7:] 3.3V operation and push-pull output. Pull-up control by software. I/O direction control by software. PORT 5 Description P5DIR (BAh) : PORT 5 Input/Output Control Register P5DIR. P5PUP. P5DIR.7 P5DIR.6 P5DIR.5 P5DIR.4 P5DIR.3 P5DIR.2 P5DIR. P5DIR. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Pullup P5DIR.X : = Input (Default) / = Output P5PUP (C2h) : PORT 5 Pull-up Control Register P5PUP.7 P5PUP.6 P5PUP.5 P5PUP.4 P5PUP.3 P5PUP.2 P5PUP. P5PUP. CPU BUS Q P5. SFR QB P5. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() P5PUP.X : = Pull-up resistor OFF, = Pull-up resistor ON (Default) Digital Input P5 (B2h) : PORT 5 Register P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5. P5. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() MiDAS2. Family [4]

41 6.5. I/O Ports : PORT6[7:] 3.3V operation and push-pull output. Pull-up control by software. I/O direction control by software. PORT 6 Description P6DIR (BBh) : PORT 6 Input/Output Control Register P6DIR. P6PUP. P6DIR.7 P6DIR.6 P6DIR.5 P6DIR.4 P6DIR.3 P6DIR.2 P6DIR. P6DIR. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Pullup P6DIR.X : = Input (Default) / = Output P6PUP (C3h) : PORT 6 Pull-up Control Register P6PUP.7 P6PUP.6 P6PUP.5 P6PUP.4 P6PUP.3 P6PUP.2 P6PUP. P6PUP. CPU BUS Q P6. SFR QB P6. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() P6PUP.X : = Pull-up resistor OFF, = Pull-up resistor ON (Default) Digital Input P6 (B3h) : PORT 6 Register P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6. P6. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() MiDAS2. Family [4]

42 6.5. I/O Ports : PORT7[7:] 3.3V operation and push-pull output. Pull-up control by software. I/O direction control by software. PORT 7 Description P7DIR (BCh) : PORT 7 Input/Output Control Register P7DIR. P7PUP. P7DIR.7 P7DIR.6 P7DIR.5 P7DIR.4 P7DIR.3 P7DIR.2 P7DIR. P7DIR. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Pullup P7DIR.X : = Input (Default) / = Output P7PUP (D9h) : PORT 7 Pull-up Control Register P7PUP.7 P7PUP.6 P7PUP.5 P7PUP.4 P7PUP.3 P7PUP.2 P7PUP. P7PUP. CPU BUS Q P7. SFR QB P7. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() P7PUP.X : = Pull-up resistor OFF, = Pull-up resistor ON (Default) Digital Input P7 (B4h) : PORT 7 Register P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7. P7. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() MiDAS2. Family [42]

43 6.5. I/O Ports : PORT8[7:] 3.3V operation and push-pull output. Pull-up control by software. I/O direction control by software. PORT 8 Description P8DIR (BDh) : PORT 8 Input/Output Control Register P8DIR. P8PUP. P8DIR.7 P8DIR.6 P8DIR.5 P8DIR.4 P8DIR.3 P8DIR.2 P8DIR. P8DIR. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Pullup P8DIR.X : = Input (Default) / = Output P8PUP (Eh) : PORT 8 Pull-up Control Register P8PUP.7 P8PUP.6 P8PUP.5 P8PUP.4 P8PUP.3 P8PUP.2 P8PUP. P8PUP. CPU BUS Q P8. SFR QB P8. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() P8PUP.X : = Pull-up resistor OFF, = Pull-up resistor ON (Default) Digital Input P8 (B5h) : PORT 8 Register P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8. P8. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() MiDAS2. Family [43]

44 6.5. I/O Ports : PORT9[7:] 3.3V operation and push-pull output. Pull-up control by software. I/O direction control by software. PORT 9 Description P9DIR (BEh) : PORT 9 Input/Output Control Register P9DIR. P9PUP. P9DIR.7 P9DIR.6 P9DIR.5 P9DIR.4 P9DIR.3 P9DIR.2 P9DIR. P9DIR. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() Pullup P9DIR.X : = Input (Default) / = Output P9PUP (E9h) : PORT 9 Pull-up Control Register P9PUP.7 P9PUP.6 P9PUP.5 P9PUP.4 P9PUP.3 P9PUP.2 P9PUP. P9PUP. CPU BUS Q P9. SFR QB P9. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() P9PUP.X : = Pull-up resistor OFF, = Pull-up resistor ON (Default) Digital Input P9 (B6h) : PORT 9 Register P9.7 P9.6 P9.5 P9.4 P9.3 P9.2 P9. P9. R/W() R/W() R/W() R/W() R/W() R/W() R/W() R/W() MiDAS2. Family [44]

45 6.5. I/O Ports : PORT Configuration MiDAS2. family provides a dedicated address register for movx instructions using Ri. If configured, AUXAD register provides the high byte of address for movx instruction instead of P2 SFR. Hence, PORT2 is fully available as general purpose I/O or PCA I/O on the condition that user uses only the internal RAM (h ~ 6FFh). To enable this feature, set ENAUX bit (IOCFG.3). PORT enable of 44-pin A-type packages. To use digital I/O and alternative function of PORT, user must set PKGOPT bit (IOCFG.). This configuration is required only for 44-PLCC (A-type) and 44-MQFP (A-type). AUXAD (BFh) : High Address Register for MOVX with Ri AUXAD.7 AUXAD.6 AUXAD.5 AUXAD.4 AUXAD.3 AUXAD.2 AUXAD. AUXAD. If ENAUX bit (IOCFG.3) is set, MOVX and A instructions refer to AUXAD instead of P2 register for high address. IOCFG (C7h) : I/O Configuration Register ENAUX - - PKGOPT ENAUX PKGOPT : Select AUXAD for MOVX with Ri. = AUXAD register serves high address for MOVX with Ri. = P2 register serves high address for MOVX with Ri. : Configure ports for 44-pin A/G-type package. = G-type (General purpose version) = Need to be set only for 44-pin A-type (ADC version) packages. MiDAS2. Family [45]

46 6.6. LVD (Low Voltage Detector) On-chip power-on reset : 2.V On-chip power-fail reset : 2.V Optional power-fail interrupt : 2.7V After POR pulse is off, the internal power stabilization counter starts to run, which lengthens power-up reset to 5ms. Flag Transition POF POR PFI A X X X B X C X X X D X X - POF is a mirror of POR. EXIF (9h) : External Interrupt Flag Register IE5 IE4 IE3 IE2 XT/RG RGMD RGSL BGS R/W() R() R/W() BGS : Band-gap Select = LVD (POR) Block Off / = LVD(POR) Block ON PCON (87h) : Power Control Register SMOD SMOD - POF GF GF PD IDL R/W() POF : Power-off Flag PD : Power-down mode bit WDCON (D8h) : Watchdog Timer & Power Status Register - POR EPFI PFI WDIF WTRF EWT RWT R/W() R/W() POR : Power-on Reset Flag EPFI : Enable Power-fail Interrupt PFI : Power-Fail interrupt Flag V DD [V] POR Pulse PFI Pulse A B C SLOPE_R SLOPE_F 2.V 2.V 2.7 V 2.7 V D TIME PD BGS LVD_OFF POR Pulse LVD EPFI PFI Pulse PFI POR POF POR Reset PFI interrupt MiDAS2. Family [46]

47 6.7. WDT (Watch Dog Timer) Detect the malfunction of program due to external noise or other causes. Return the operation to the normal condition using WDT interrupt If enabled, WDT interrupt or WDT reset makes MCU wake up from stop mode. Watchdog Time-out Values (CKCON[7:6]) Default : WD,WD = [,] WDCON (D8h) : Watchdog Timer & Power Status Register - POR EPFI PFI WDIF WTRF EWT RWT WD WD Interrupt Time-out (@25MHz) Reset Time-out (@25MHz) 2 7 clocks 5.24 ms clocks 5.26 ms 2 2 clocks 4.94 ms clocks 4.96 ms 2 23 clocks ms clocks ms 2 26 clocks 2, ms clocks 2, ms R/W() R/W() POR : Power-on Reset Flag EPFI : Enable Power-fail Interrupt PFI : Power-Fail interrupt Flag WDIF : Watchdog Timer Interrupt Flag WTRF : Watchdog Timer Reset Flag EWT : Watchdog Timer Reset Enable RWT : Restart Watchdog Timer 27-bit Counter CKCON[7:6] CLK WD WD EIE.4 RESET RWT WDCON WDCON.3 WDIF 52 clocks Delay EWDT EWT Interrupt WDT Reset WDCON. WTRF WDCON.2 MiDAS2. Family [47]

48 6.8. Timer/Counter : Timer / Compatible with traditional 8C52 Timer/Counter function Time base is selectable by S/W : 4 clocks or 2 clocks CKCON (8Eh) : Clock Control Register WD WD T2M TM TM - UT2DIS U2T2DIS Mode Timer Timer Timer Mode Mode (M,M=) (M,M=) 3-bit T/C 3-bit T/C 6-bit T/C 6-bit T/C Mode 2 (M,M=) 8-bit T/C with automatic reload (TL TH) 8-bit T/C with automatic reload (TL TH) TMOD (89h) : Timer / Mode Control Register GATE C/T M M GATE C/T M M GATE[7] C/T[6] M, M GATE[3] C/T[2] M, M Mode 3 (M,M=) 8-bit T/C (TL) Timer interrupt 8-bit T/C (TH) Timer interrupt Halt : Timer Gate Control : Timer Counter/Timer Select. When set, Counter by T pin. : Timer Mode Select [,] : Mode. 3-bit T/C. [,] : Mode. 6-bit T/C. [,] : Mode 2. 8-bit T/C with automatic reload [,] : Mode 3. Timer Halt : Timer Gate Control : Timer Counter/Timer Select. When set, Counter by T pin. : Timer Mode Select [,] : Mode. 3-bit T/C. [,] : Mode. 6-bit T/C. [,] : Mode 2. 8-bit T/C with automatic reload [,] : Mode 3. Two 8-bit T/C R/W() R/W() TM TM : Timer Clock Time-base Selection TM=, Time-base is 4 clocks not 2 clocks. : Timer Clock Time-base Selection TM=, Time-base is 4 clocks not 2 clocks. TCON (88h) : Timer / Control Register TF TR TF TR IE IT IE IT TF TR TF TR IE IT IE IT : Timer Overflow Flag : Timer Run Enable : Timer Overflow Flag : Timer Run Enable : External Interrupt Flag : External Interrupt Type Select Edge Detect (IT=). Level Detect (IT=) : External Interrupt Flag : External Interrupt Type Select Edge Detect (IT=). Level Detect (IT=) TL (8Ah) : Timer Low Byte Register TL.7 TL.6 TL.5 TL.4 TL.3 TL.2 TL. TL. TH (8Ch) : Timer High Byte Register TH.7 TH.6 TH.5 TH.4 TH.3 TH.2 TH. TH. TL (8Bh) : Timer Low Byte Register TL.7 TL.6 TL.5 TL.4 TL.3 TL.2 TL. TL. TH (8Dh) : Timer High Byte Register TH.7 TH.6 TH.5 TH.4 TH.3 TH.2 TH. TH. MiDAS2. Family [48]

49 6.8. Timer/Counter : Timer / Mode Description OSC /2 /4 OSC /2 /4 TxM Tx PIN C/T= CONTROL TLx C/T= (5bits) THx (8bits) TFx Interrupt TxM Tx PIN C/T= CONTROL TLx C/T= (8bits) THx (8bits) TFx Interrupt GATE INTx PIN TRx GATE INTx PIN TRx [Mode ] [Mode ] OSC /2 /4 TxM Tx PIN GATE INTx PIN TRx C/T= CONTROL TLx C/T= (8bits) THx (8bits) RELOAD TFx Interrupt OSC /2 /4 TM T PIN GATE INT PIN OSC /2 /4 TR C/T= CONTROL TL C/T= CONTROL (8bits) TH (8bits) TF TF Timer Interrupt Timer Interrupt TM TR [Mode 2] [Mode 3(Timer only)] MiDAS2. Family [49]

50 6.8. Timer/Counter : Timer 2 Compatible with traditional 8C52 Timer/Counter 2 function Up and down count enable by S/W Time base is selectable by S/W : 4 clocks or 2 clocks CKCON (8Eh) : Clock Control Register WD WD T2M TM TM - UT2DIS U2T2DIS R/W() R/W(). 6-bit Auto-reload [RCLK+TCLK=, CP/RL2=, T2OE=] 2. 6-bit Capture [RCLK+TCLK=, CP/RL2=, T2OE=] 3. Baud Rate Generator [RCLK+TCLK=, CP/RL2=X, T2OE=X] 4. Programmable Clock Out [RCLK+TCLK=X, CP/RL2=, T2OE=] 6-bit Timer/Counter With Automatic Reload (TH2, TL2 RCAP2H, RCAP2L) 6-bit Timer/Counter with Capture (RCAP2H, RCAP2L TH2, TL2 ) Baud Rate Generation * Timer 2 Interrupt Disable Clock-out on P. T2M : Timer 2 Clock Time-base Selection T2M=, Time-base is 4 clocks not 2 clocks. T2MOD (C9h) : Timer 2 Mode Register T2OE DCEN T2OE : Timer 2 Clock Output to P. DCEN : Timer 2 Down Count Enable TL2 (CCh) : Timer 2 Low Byte Register TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2. TL2. T2CON (C8h) : Timer 2 Control Register TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 TH2 (CDh) : Timer 2 High Byte Register TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2. TH2. TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 : Timer 2 Overflow Flag : Timer 2 External Flag : Receive Clock Flag : Transmit Clock Flag : Timer 2 External Enable Flag : Timer 2 Run Enable : Timer or Counter Selection. If C/T2=, Timer Operation. : Capture/Reload Flag. CP/RL2=, Reload. (TH2,TL2) (RCAP2H, RCAP2L) CP/RL2=, Capture. (RCAP2H, RCAP2L) (TH2,TL2) RCAP2L (CAh) : Timer 2 Capture/Reload Low Byte Register RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L. RCAP2L. RCAP2H (CBh) : Timer 2 Capture/Reload High Byte Register RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H. RCAP2H. MiDAS2. Family [5]

51 6.8. Timer/Counter : Timer 2 Mode Description OSC /2 T2EX PIN /4 T2M T2 PIN Transition Detection C/T2= CONTROL Overflow TL2 TH2 TF2 C/T2= Capture CONTROL EXEN2 TR2 RCAP2L RCAP2H EXF2 Timer 2 Interrupt OSC /2 T2EX PIN /4 T2M T2 PIN Transition Detection C/T2= CONTROL TL2 TH2 Overflow C/T2= Reload CONTROL EXEN2 TR2 RCAP2L RCAP2H TF2 EXF2 Timer 2 Interrupt [Capture Mode] [Auto Reload Mode (DCEN=)] OSC /2 /4 T2M T2 PIN C/T2= C/T2= (Down Counting Reload Value) CONTROL TR2 FFh TL2 RCAP2L FFh TH2 RCAP2H Overflow (Up Counting Reload Value) T2EX PIN Toggle Count Direction =UP =Down EXF2 TF2 Timer 2 Interrupt OSC /2 T2 (P.) T2EX (P.) Transition Detection CONTROL EXEN2 CONTROL TR2 C/T2 /2 EXF2 TL2 RCAP2L Timer 2 Interrupt TH2 RCAP2H CONTROL T2OE (T2MOD.) [Auto Reload Mode (DCEN=)] [Clock-Out Mode] MiDAS2. Family [5]

52 6.8. Timer/Counter : Timer 2 Mode Description Timer Overflow /2 OSC /2 T2 PIN C/T2= CONTROL C/T2= TL2 TR2 RCAP2L TH2 RCAP2H Reload SMOD RCLK /6 TCLK /6 RX Clock TX Clock Transition Detection CONTROL T2EX (P.) EXEN2 EXF2 Timer 2 Interrupt [Baud Rate Generator Mode] MiDAS2. Family [52]

53 6.9. UART (UART/UART) Function-level compatible with traditional 8C52 UART. Automatic address recognition : Multi processor communication. The name of SFR's for UART is the same as legacy UART. PCON (87h) : Power Control Register SMOD SDMO - POF GF GF PD IDL R() R/W() SMOD : Timer baud rate double in UART mode, 2, and 3 SMOD : Enable SM access. Don t modify this bit. SCON (98h) : Serial Port Control Register for UART Mode Mode Mode 2 Mode 3 8 bits bits bits bits Data Size 8 data bits Start bit() 8 data bit Stop bit() Start bit() 8 data bit Programmable bit Stop bit() Start bit() 8 data bit Programmable bit Stop bit() Baud Rate /4 x Oscillator Clock /32 x Timer Overflow (SMOD=) /6 x Timer Overflow (SMOD=) /6 x Timer 2 Overflow Rate /32 x Oscillator Clock (SMOD=) /6 x Oscillator Clock (SMOD=) /32 x Timer Overflow (SMOD=) /6 x Timer Overflow (SMOD=) /6 x Timer 2 Overflow Rate Timer Overflow is variable with CKCON register. 2 clocks time-base or 4 clocks time-base. SM SM SM2 REN TB8 RB8 TI RI SM, SM : Serial Port Mode Select [,] : Mode. 8-bit Shift Register (OSC/4) [,] : Mode. 8-bit UART (Variable) [,] : Mode 2. 9-bit UART (OSC/32 or OSC/6) [,] : Mode 3. 9-bit UART (Variable) SM2 : Enable the Automatic Address Recognition in Mode 2 and 3. Clear after receiving the address. In Mode, Valid Stop Bit Check if SM2=. In Mode, SM2 should be. REN : Serial Reception Enable. TB8 : 9th data bit that will be transmitted in Mode 2 and 3. RB8 : 9th data bit that was received in Mode 2 and 3. In Mode, RB8 is equal to Stop Bit if SM2=. In Mode, RB8 is not used. TI : Transmission Interrupt Flag. Must be cleared by S/W. RI : Reception Interrupt Flag. Must be cleared by S/W. SBUF (99h) : Serial Data Buffer Register for UART SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF. SBUF. Transmission buffer and reception buffer are separated. Read and Write address are same. MiDAS2. Family [53]

54 6.9. UART : Automatic Address Recognition Example Baud Rate Discrimination of UART and UART User may selectively disable TCLK or RCLK to run UART and UART at different baud rate. Slave : For instance, if UT2DIS is set, UART may use Timer SADDR = for baud rate generation even though TCLK or RCLK SADEN = bit is set. GIVEN = XX Slave 2: SADDR = SADEN = GIVEN = XX Master sends to select Slave. Master sends to select Slave 2. Master sends or to select Slave and Slave 2. UT2DIS UT2DIS TCLK UART_TCLK UART_RCLK UART_TCLK SADDR(A9h) : Slave Address Register of UART SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR. SADDR. RCLK CKCON(8Eh) : Clock Control Register UART_RCLK Programmed with the given or broadcast address assigned to serial port. WD WD T2M TM TM - UT2DIS UT2DIS R/W() R/W() SADEN(B9h) : Slave Address Mask Enable Register of UART SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN. SADEN. UT2DIS UT2DIS : Used to disable RCLK/TCLK control for UART to use T overflow for baud rate generation : Used to disable RCLK/TCLK control for UART to use T overflow for baud rate generation MiDAS2. Family [54]

55 6.9. UART : UART SFRs SCON (Bh) : Serial Port Control Register for UART SM SM SM2 REN TB8 RB8 TI RI SM, SM : Serial Port Mode Select [,] : Mode. 8-bit Shift Register (OSC/4) [,] : Mode. 8-bit UART (Variable) [,] : Mode 2. 9-bit UART (OSC/32 or OSC/6) [,] : Mode 3. 9-bit UART (Variable) SM2 : Enable the Automatic Address Recognition in Mode 2 and 3. Clear after receiving the address. In Mode, Valid Stop Bit Check if SM2=. In Mode, SM2 should be. REN : Serial Reception Enable. TB8 : 9th data bit that will be transmitted in Mode 2 and 3. RB8 : 9th data bit that was received in Mode 2 and 3. In Mode, RB8 is equal to Stop Bit if SM2=. In Mode, RB8 is not used. TI : Transmission Interrupt Flag. Must be cleared by S/W. RI : Reception Interrupt Flag. Must be cleared by S/W. SBUF (Ah) : Serial Data Buffer for UART SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF. SBUF. Transmission buffer and reception buffer are separated. Read and Write address are same. SADDR(AAh) : Slave Address Register of UART SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR. SADDR. Programmed with the given or broadcast address assigned to serial port. SADEN(ABh) : Slave Address Mask Enable Register of UART SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN. SADEN. MiDAS2. Family [55]

56 6.9. UART : Baud Rate Example Serial Port Mode Baudrate = Serial Port Mode 2 Baudrate = Oscillator Frequency 4 2 SMOD PCON.7 X Oscillator Frequency 32 EX) Timer Generated Commonly Used Baud Rates EX) Timer 2 Generated Commonly Used Baud Rates Serial Port Mode, 3 Using Timer Overflow 2 Mode & 3 Baudrate = SMOD 3 TM X F OSC X X 32 2 [ 256 (TH) ] Mode & 3 Baudrate = X F OSC X 32 [65536 (RCAPH,RCAPL) ] Baudrate = Using Timer 2 Overflow Baudrate = 2 SMOD 32 X Timer overflow Timer 2 overflow 6 If SMOD(PCON.7) = Double Buadrate If TM(CKCON.4) = /2 x F OSC If TM(CKCON.4) = /4 X F OSC Baudrate UART Timer F SMOD TM= Mode OSC TM= C/T Mode Reload Value (TH) Max : 3 MHz Max : 3 MHz Mode 2 MHz X X X X Max : 75 KHz Max : 75 KHz Mode 2 2 MHz X X X 62.5 KHz 9.2 KHz 9.6 KHz 4.8 KHz 2.4 KHz.2 KHz 37.5 Hz Hz Hz 87.5 KHz 57.6 KHz 28.8 KHz 4.4 KHz 7.2 KHz 3.6 KHz 42.5 Hz 33 Hz 33 Hz Mode & 3 2 MHz.592 MHz.592 MHz.592 MHz.592 MHz.592 MHz.592 MHz 6 MHz 2 MHz FFh FDh FDh FAh F4h E8h Dh 72h FEEBh MiDAS2. Family [56]

57 6.9. UART : Mode Function TB8 Internal BUS Write to SBUF D CL S Q SBUF Zero Detector RXD P3. ALT OUTPUT FUNCTION S4 (F OSC / 4) Serial Port Interrupt START SHIFT TX CONTROL TX CLOCK TI SEND Shift Clock TXD P3. ALT OUTPUT FUNCTION REN RI RX CLOCK RI RECEIVE RX CONTROL START SHIFT Load SBUF Input Shift Register Shift RXD P3. ALT INPUT FUNCTION SBUF Read SBUF Internal BUS MiDAS2. Family [57]

58 6.9. UART : Mode Timing [Transmit] S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S ALE Write to SBUF SEND Shift RXD (Data Out) D D D2 D3 D4 D5 D6 D7 TXD (Shift Clock) TI S2 S4 [Receive] Write to SCON (Clear RI) RI Receive Shift RXD (Data Out) D D D2 D3 D4 D5 D6 D7 TXD (Shift Clock) MiDAS2. Family [58]

59 6.9. UART : Mode Function SMOD Timer Overflow /2 Timer 2 Overflow Write to SBUF TB8 D S Q CL Internal BUS SBUF Zero Detector TXD TCLK T2CON.4 /6 START SHIFT TX CONTROL TX CLOCK TI DATA SEND RCLK T2CON.5 Serial Port Interrupt /6 -to- Transition Detector Sample RX CLOCK RI RX CONTROL START FFh LOAD SBUF SHIFT Bit Detector RXD Input Shift Register (9 bits) Load SBUF Shift SBUF Read SBUF Internal BUS MiDAS2. Family [59]

60 6.9. UART : Mode Timing [Transmit] TX Clock Write to SBUF SEND S Data Shift TXD Start bit D D D2 D3 D4 D5 D6 D7 Stop bit TI [Receive] /6 Reset RX CLOCK RXD Start bit D D D2 D3 D4 D5 D6 D7 Stop bit Bit Detector Sample Times Shift RI MiDAS2. Family [6]

61 6.9. UART : Mode 2 Function TB8 Internal BUS F OSC /2 Write to SBUF D CL S Q SBUF TXD /2 Zero Detector SMOD (SMOD is PCON.7) /6 STOP BIT SHIFT START TX CONTROL TX CLOCK TI DATA SEND Serial Port Interrupt /6 -to- Transition Detector Sample RX CLOCK RI RX CONTROL START FFh LOAD SBUF SHIFT Bit Detector RXD Input Shift Register (9 bits) Load SBUF Shift SBUF Read SBUF Internal BUS MiDAS2. Family [6]

62 6.9. UART : Mode 2 Timing [Transmit] TX Clock Write to SBUF SEND Data S Shift TXD Start bit D D D2 D3 D4 D5 D6 D7 TB8 Stop bit TI Stop bit Gen. [Receive] /6 Reset RX CLOCK RXD Start bit D D D2 D3 D4 D5 D6 D7 RB8 Stop bit Bit Detector Sample Times Shift RI MiDAS2. Family [62]

63 6.9. UART : Mode 3 Function SMOD Timer Overflow /2 Timer 2 Overflow Write to SBUF TB8 D S Q CL Internal BUS SBUF Zero Detector TXD TCLK T2CON.4 /6 START SHIFT TX CONTROL TX CLOCK TI DATA SEND RCLK T2CON.5 Serial Port Interrupt /6 -to- Transition Detector Sample RX CLOCK RI RX CONTROL START FFh LOAD SBUF SHIFT Bit Detector RXD Input Shift Register (9 bits) Load SBUF Shift SBUF Read SBUF Internal BUS MiDAS2. Family [63]

64 6.9. UART : Mode 3 Timing [Transmit] TX Clock Write to SBUF SEND Data S Shift TXD Start bit D D D2 D3 D4 D5 D6 D7 TB8 Stop bit TI Stop bit Gen. [Receive] /6 Reset RX CLOCK RXD Start bit D D D2 D3 D4 D5 D6 D7 RB8 Stop bit Bit Detector Sample Times Shift RI MiDAS2. Family [64]

65 6.. PCA (Programmable Counter Arrays) Basic Feature Support Intel/Philips compatible functions. Unique Features Each PCA provides 6 modules. PCA counter can run in auto-reset mode such that CL (or CL) is reset when CL (or CL) is equal to CH (or CH). Support Dynamic PWM (Pulse Width Modulation) by virtue of above behavior. 8-bit pre-scale counter to generate PCA clock. [ PCA ] [ PCA ] 6 bits 6 bits MODULE P2. / CEX MODULE P. / CEX 6 bits MODULE P2. / CEX 6 bits MODULE P. / CEX Time Base for PCA Module PCA Timer/Counter MODULE2 MODULE3 P2.2 / CEX2 P2.3 / CEX3 Time Base for PCA Module PCA Timer/Counter MODULE2 MODULE3 P.2 / CEX2 P.3 / CEX3 MODULE4 P2.4 / CEX4 P.7 / ECI P.6 / ECI MODULE4 P.4 / CEX4 MODULE5 P2.5 / CEX5 MODULE5 P.5 / CEX5 Module Functions: 6-bit Capture 6-bit Timer 6-bit High Speed Output 8-bit Fixed PWM Output 8-bit Dynamic PWM Output Module Functions: 6-bit Capture 6-bit Timer 6-bit High Speed Output 8-bit Fixed PWM Output 8-bit Dynamic PWM Output MiDAS2. Family [65]

66 6.. PCA : Interrupt Sources of a PCA CCON ( ACh) : PCA Counter Control Register CnMOD. ECF PCA Timer/Counter MODULE MODULE MODULE2 MODULE3 MODULE4 CnCON.7. CF CR CCF5 CCF4 CCF3 CCF2 CCF CCF EIE.6/7 EPCAn IE.7 EA Interrupt Priority Decoder CF CR CCF5 CCF4 CCF3 CCF2 CCF CCF CF CR CCF5 CCF4 CCF3 CCF2 CCF CCF : PCA counter overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software : PCA counter run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. : PCA module 5 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. : PCA module 4 interrupt flag. : PCA module 3 interrupt flag. : PCA module 2 interrupt flag. : PCA module interrupt flag. : PCA module interrupt flag. MODULE5 ECCFm CnCAPMm. CCON ( CEh) : PCA Counter Control Register CF CR CCF5 CCF4 CCF3 CCF2 CCF CCF MiDAS2. Family [66]

67 6.. PCA : PCAn Counter Control Registers To use PCA Counter as a 8-bit Auto-reset Counter Turn off the PCAn by clearing CR bit (CnCON.6) Write proper values to CnL and CnH. Set PWMDYN bit (CnMOD.6) and set CF bit (CnCON.7) Run PCAn by setting CR bit (CnCON.6) Interrupt occurs when CnL reaches to CnH. Do proper action at PCAn counter overflow interrupt. overflow CMOD (ADh) : PCA Counter Mode Register CIDL PWMDYN - CPS3 CPS2 CPS CPS ECF CIDL : Counter idle control. CIDL = programs the PCA counter to continue functioning during idle mode. CIDL = programs it to be stop during idle mode. PWMDYN : If this bit is set, PCA counter runs for dynamic PWM. That is, CL is cleared when CL matches to C and the overflow signal for PWM is replaced by the match signal. In fact, PWMDYN = makes the PCA counter run like a 8-bit auto-reload counter. CPS[3:] : PCA count rate (F PCA ) select. (Refer to below Table) ECF : Enable PCA counter overflow interrupt. ECF = enables CF bit in CCON to generate an interrupt. ECF = disables that function. [ count rate (F PCA ) Selection ] PWMDYN CnMOD.6 CnL 8-BIT COMPARATOR CnH CPS3 CPS2 CPS CPS Description Internal clock, F OSC Internal clock, F OSC / 2 2 Internal clock, F OSC / 4 3 Internal clock, F OSC / 8 4 Internal clock, F OSC / 2 5 Internal clock, F OSC / 6 6 Internal clock, F OSC / 32 7 Internal clock, F OSC / 64 8 Internal clock, F OSC / 28 9 Internal clock, F OSC / 256 External clock at ECIn pin (max rate = F OSC / 2) Timer overflow [ Counter in Dynamic Mode (PWMDYN=) ] CMOD (CFh) : PCA Counter Mode Register MiDAS2. Family [67]

68 6.. PCA : PCAn Module Control Registers CCAPM (A2h) : Mode Control Register of PCA MODULE IPWM ECOM CAPP CAPN MAT TOG PWM ECCF R/W() IPWM ECOM CAPP CAPN MAT TOG PWM ECCF : Inverted PWM. If this bit is set, the PWM output is inverted. That is, PWM output is high when CL CCAPmL. The change of this flag is in effect at the next overflow / match time of PWM. : Enable comparator. ECOM = enables the comparator function. : Capture positive. CAPP = enables positive edge capture. : Capture negative. CAPN = enables negative edge capture. : Match. When MAT =, a match of the PCA counter with this module s comparator/capture register causes the CCF bit int CCON to be set, flagging an interrupt. : Toggle. When TOG =, a match of the PCA counter with this module s comparator/capture register causes the CEX pin to toggle. : Pulse width modulation mode. PWM = enables the CEX pin to be used as a pulse width modulated output. : Enable CCF interrupt. Enables compare/capture flag CCF in the CCON register to generate an interrupt. CCAPM (A3h) : Mode Control Register of PCA MODULE CCAPM2 (A4h) : Mode Control Register of PCA MODULE2 CCAPM3 (A5h) : Mode Control Register of PCA MODULE3 CCAPM4 (A6h) : Mode Control Register of PCA MODULE4 CCAPM5 (A7h) : Mode Control Register of PCA MODULE5 CCAPM (E2h) : Mode Control Register of PCA MODULE CCAPM (E3h) : Mode Control Register of PCA MODULE CCAPM2 (E4h) : Mode Control Register of PCA MODULE2 CCAPM3 (E5h) : Mode Control Register of PCA MODULE3 CCAPM4 (E6h) : Mode Control Register of PCA MODULE4 CCAPM5 (E7h) : Mode Control Register of PCA MODULE5 [ PCA Module Modes (CnCAPMm Register) ] IPWMmECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm X X X X X X X X X X X X X X Module Function No operation ) 6-bit capture by a positive-edge trigger on CnEXm ) 6-bit capture by a negative-edge trigger on CnEXm ) 6-bit capture by any transition on CnEXm 2) 6-bit software timer 3) 6-bit high speed output 4) 5) 8-bit PWM normal output 4) 5) 8-bit PWM inverted output * ) ~ 5) : Refer to next slides. MiDAS2. Family [68]

69 6.. PCA : PCA Modes ) Capture Mode CnCON CF CR CCF5 CCF4 CCF3 CCF2 CCF CCF PCA Interrupt (to CCFm) PCA Timer/Counter (F PCA ) CnH CnL CnEXm CAPTURE CnCAPMm IPWMmECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm X X X [,], [,], [,] CnCAPmH CnCAPmL n = PCA Number, m = Module Number ex) CCAPL : Low Capture/Compare Register for Module of PCA 2) Compare/Timer Mode CnCON CF CR CCF5 CCF4 CCF3 CCF2 CCF CCF RESET PCA Timer/Counter (F PCA ) PCA Interrupt Write to CnCAPmH CnH CnL 6-BIT COMPARATOR MATCH (to CCFm) CnCAPmH CnCAPmL Write to CnCAPmL ENABLE CnCAPMm IPWMmECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm X X MiDAS2. Family [69]

70 6.. PCA : PCA Modes 3) PCA High Speed Output Mode CnCON CF CR CCF5 CCF4 CCF3 CCF2 CCF CCF RESET PCA Timer/Counter (F PCA ) PCA Interrupt Write to CnCAPmH CnH CnL 6-BIT COMPARATOR MATCH (to CCFm) CnCAPmH CnCAPmL CnEXm Write to CnCAPmL ENABLE CnCAPMm IPWMmECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm X X [ Update of CnCAPmH & CnCAPmL ] During the interrupt routine, a new 6-bit compare value can be written to the compare register (CnCAPmH & CnCAPmL) Notice, however, that a write to CnCAPmL clears the ECOMm bit when temporarily disables the comparator function while these registers are being updated so an invalid match does not occur. A write to CnCAPmH sets the ECOMm bit and re-enables the comparator. For this reason, user software should write to CnCAPmL first, the CnCAPmH. MiDAS2. Family [7]

71 6.. PCA : PCA Modes 4) PWM Mode (Fixed : PWMDYN = ) PCA Timer/Counter CnL (F PCA ) 8-BITCOMPARATOR CnCAPmL [ IPWMm= ] CnL < CnCAPmL CnL CnCAPmL CnEXm [ IPWMm= ] CnL CnCAPmL CnL < CnCAPmL CnEXm CnCAPmH CnCAPMm IPWMmECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm or 5) PWM Mode (Dynamic : PWMDYN = ) CnMOD.6 PWMDYN CnH CnH == CnL 8-BITCOMPARATOR CnL PCA Timer/Counter (F PCA ) 8-BITCOMPARATOR CnCAPmL [ IPWMm= ] CnL < CnCAPmL CnL CnCAPmL CnEXm [ IPWMm= ] CnL CnCAPmL CnL < CnCAPmL CnEXm CnCAPmH CnCAPMm IPWMmECOMm CAPPm CAPNm MATm TOGm PWMm ECCFm or MiDAS2. Family [7]

72 6.. PCA : Examples of Fixed PWM Output Duty Cycle (CnCAPmH) with IPWMm = % () Period : 256 / F PCA 9% (25) 5% (28) % (23).4% (255) Duty Cycle (CnCAPmH) with IPWMm = (Inverted PWM Output) % () Period : 256 / F PCA 9% (25) 5% (28) % (23).4% (255) MiDAS2. Family [72]

73 6.. PCA : Examples of Dynamic PWM Output Duty Cycle (CnCAPmH) with IPWMm = % () Period : 48 / F PCA 83% (8) 5% (24) 7% (4) 2% (47) Duty Cycle (CnCAPmH) with IPWMm = (Inverted PWM Output) % () Period : 48 / F PCA 83% (8) 5% (24) 7% (4) 2% (47) MiDAS2. Family [73]

74 6.. ADC (Analog-to-Digital Converter) 8-channel -bit ADC (SAR Type) Max. 4ksps(samples per F ADC = 2MHz & 3.3V ADCSEL (EDh) : ADC Clock and MUX Selection Register ADIV2 ADIV ADIV - - ADCS2 ADCS ADCS ADCHEN (ECh) : ADC Input Channel Enable Register ADCHEN.7 ADCHEN.6 ADCHEN.5 ADCHEN.4 ADCHEN.3 ADCHEN.2 ADCHEN. ADCHEN. ADCON (EFh) : ADC Control & ADC Result Low Register AD_EN AD_REQ AD_END ADCF - - SAR SAR R() ADCR (EEh) : ADC Result High Register SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 ADC (P.) ADC (P.) ADC7 (P.7) ADCHEN. ADCHEN ADCHEN ADCHEN.7 ADCHEN7 ADCSEL[2:] ADCS2 ADCS ADCS Analog MUX ADCON.7 AD_EN Control Circuit ADCON.6 AD_REQ D/A Converter AV REF (= V DD ) Analog Comparator V SS ADSEL[7:5] ADIV2 ADIV ADIV System Clock Clock Divide F ADC Successive Approximation Register ADCR SAR[9:] SAR[9:2] ADCON.5 AD_END ADCON.4 ADCF ADC Interrupt Flag SAR[:] ADCON MiDAS2. Family [74]

75 6.. ADC : Conversion Timing AD_EN Set by S/W AD_REQ Set by S/W Cleared by H/W AD_END Cleared by H/W 4F ADC Set by H/W Valid Bit Setup Time Hold Time 5F ADC (4F ADC ) x bits = 4F ADC 5F ADC ADCF 5F ADC Set by H/W ADC Interrupt AD_EN : ADC Block Enable Signal. Set or Cleared by S/W. [An Example of ADC Conversion Table] AD_REQ AD_END ADCF : ADC Conversion Request Start Bit. Set by S/W and Cleared by H/W. This bit must be set at each sample conversion. : Set or Cleared by H/W. Clear when Conversion started. Set when Conversion ended. : ADC Interrupt Flag. Set by H/W and Cleared by S/W. You should clear ADCF bit in ADC interrupt routine. OSC Divide (ADCSEL[7:5]) (OSC/2) (OSC/4) (OSC/8) (OSC/6) (OSC/32) F ADC T (/F ADC ) 2MHz MHz 5MHz 2.5MHz.25MHz 5ns ns 2ns 4ns 8ns Sample Conversion Time 2.5us 5.us.us 2.us 4.us MiDAS2. Family [75]

76 6.2. Interrupt : 6 Sources / 4-level Priority Interrupt Sources : Timer //2, UART/, PCA/, ADC, WDT, LVD, 6 External. 4-level Interrupt Priority * Interrupt related to SFR (refer to Appendix B : SFR Description) TCON (88h) EXIF (9h) TF TR TF TR IE IT IE IT IE5 IE4 IE3 IE2 XT/RL RGM RGSL BGS [Interrupt Vector Address] IE (A8h) EA EADC ET2 ES ET EX ET EX HIGH PRIORITY LOW Interrupt Sources Address Priority Level LVD 33h Highest INT 3h 4 Levels TF Bh 4 Levels INT 3h 4 Levels TF Bh 4 Levels RI+TI 23h 4 Levels TF2 2Bh 4 Levels ADC 3Bh 4 Levels INT2 43h 2 Levels INT3 4Bh 2 Levels INT4 53h 2 Levels INT5 5Bh 2 Levels WDT 63h 2 Levels RI+TI 6Bh 2 Levels PCA 73h 2 Levels PCA 7Bh 2 Levels NMI 852 Interrupt Sources EIE IP IPH EIP (E8h) (B8h) (B7h) (F8h) WDCON (D8h) Interrupt Flag bits IE EPCA EPCA ES EWDT EX5 EX4 EX3 EX2 - PADC PT2 PS PT PX PT PX - PADCH PT2H PSH PTH PXH PTH PXH PPCA PPCA PS PWDT PX5 PX4 PX3 PX2 - POR EPFI PRI WDIF WTRF EWT RWT [Interrupt Vector Generation Flow] Individual Enable bits EX Global Enable bits EA Priority bits PXH PX Polling & Vector Generation 3h Interrupt Vector 3h [Response Sequence] Sample & Flag Set Polling LCALL Service Routine Last Cycle & High Priority & Not-update Interrupt Register MiDAS2. Family [76]

77 6.2. Interrupt Functional Description LVD (Power Fail) INT Timer/Counter INT Timer/Counter UART Timer/Counter 2 ADC INT2 INT3 INT4 INT5 RI TI PFI IE TF IE TF TF2 ADCF IE2 IE3 IE4 IE5 Interrupt Enable Bits EPFI EX ET EX ET ES ET2 EADC EX2 EX3 EX4 EX5 EA High Priority PXH PTH PXH PTH PSH PT2H PADCH Low Priority PX PT PX PT PS PT2 PADC PX2 PX3 PX4 PX5 Highest High Priority High Priority High Priority High Priority High Priority Interrupt Polling Sequence Interrupt Level Lowest Interrupt Vector WDT WDIF EWDT PWDT UART PCA RI TI CF ES EPCA PS PPCA PCA CF EPCA PPCA Low Priority Low Priority MiDAS2. Family [77]

78 6.3. Reset Circuit : 3 Reset Sources LVD(POR) Reset Power-on Reset (POR) when power-up. Power-fail Reset under certain voltage. External RESET Pin RESET Pin must hold H for min. 24 clocks period. WDT Reset : Optional Control by S/W Once triggered by any one of reset sources, the internal reset of MiDAS2. remains high at least 28 clocks. WDCON (D8h) : Watchdog Timer & Power Status Register - POR EPFI PFI WDIF WTRF EWT RWT R/W() R/W() WTRF : Watchdog Timer Reset Flag. EWT : Watchdog Timer Reset Enable. V DD LVD POR LVD RESET Generation RESET External RESET Generation (Min. 24 Clocks Period) WTRF Internal RESET (Min. 28 clocks) Clock WDT 27 bits Counter Delay 52 Clocks WDT RESET Generation Initialize EWT MiDAS2. Family [78]

79 6.4. Clock Circuit System Clock Sources Crystal Oscillator External Oscillator Internal Ring Oscillator Disable of External Clock (Crystal or External Oscillator) If XTOFF is set. When MCU is in stop mode and WDT is not active. Disable of the Internal RING Oscillator If RINGON is cleared. When MCU is in stop mode and WDT is not active. Wake-up from stop by WDT WDT is active in stop mode if EWT is set or WDT interrupt is enabled. In this case, the clock of WDT is alive during stop mode. OSCICN[:] IE.7 EA EIE.4 OSCICN.2 RINGON DIV DIV EWDT WDCON.2 Divider EWT PCON. PD Internal RING Oscillator RCLK PMR.3 STATUS.4 XTOFF XTUP SYS_CLK Crystal OSC. Clock Stable Circuit (6-bit Counter) XCLK System Clock Generation Peri. Clock CPU Clock XT/RG PD IDL EXIF.3 PCON. PCON. MiDAS2. Family [79]

80 6.4. Clock Circuit : SFR IE (A8h) : Interrupt Enable Register EA EADC ET2 ES ET EX ET EX PMR (C4h) : Power Management Control Register XTOFF ALEOFF - - EA : Global interrupt enable EIE (E8h) : Extended Interrupt Enable Register EWDT EX5 EX4 EX3 EX2 EWDT : Watchdog timer interrupt enable PCON (87h) : Extended Interrupt Enable Register SMOD SMOD - POF GF GF PD IDL R/W() PD IDL : Power-down (Stop) mode enable. : IDL mode enable EXIF (9h) : External Interrupt Flag Bit Register IE5 IE4 IE3 IE2 XT/RG RGMD RGSL BGS R/W() R() R/W() XT/RG : System clock selection. = Internal RING oscillator is selected as system clock. = External clock is selected as system clock. XTOFF : = External crystal will be killed. = External crystal will run (Default). STATUS (C5h) : Crystal Status Register XTUP XTUP R() : Crystal oscillator warm-up status. It represents the crystal clock is stable() or not(). Cleared by H/W if XTOFF is set of if PD is set and WDT is not enabled. Set by H/W after crystal stabilization time. OSCICN (C6h) : Internal RING Oscillator Control Register RINGON DIV DIV R/W() RINGON : = Internal RING oscillator is running. = Internal RING oscillator is killed. Don t clear RINGON bit when XTRG =. DIV, DIV : RING oscillator divider. [,] = 4MHz/ [,] = 4MHz/2 (2MHz) [,] = 4MHz/4 (MHz) [,] = 4MHz/8 (5kHz) WDCON (D8h) : Watchdog Timer & Power Status Register - POR EPFI PFI WDIF WTRF EWT RWT R/W() R/W() EWT : Watchdog timer reset enable MiDAS2. Family [8]

81 6.4. Clock Circuit : Guideline for Configuration Crystal Oscillator Oscillator Module Internal Ring Oscillator XTAL2 MiDAS XTAL2 MiDAS XTAL2 MiDAS XTAL XTAL XTAL RING OSC OSC Oscillator Module RC Oscillator MiDAS2. Family [8]

82 6.5. Power Management : 3 Modes Active Mode : CPU and Peripheral are running. Idle Mode : Only Peripheral is running. Wake-up by all kinds of interrupts. CPU continues execution. Wake-up by all kinds of resets. CPU restarts. Stop Mode : Both are not running. Wake-up by external interrupt or (level detect). External pins must hold during at least crystal stabilization time. CPU continues execution. Wake-up by all kinds of resets. CPU restarts. Wake-up by WDT interrupt or reset. PCON (87h) : Power Control Register SMOD SMOD - POF GF GF PD IDL R/W() PD IDL : Stop Mode (Power-down) Enable. : IDLE Mode Enable. IDL XTAL2 C C XTAL Peripheral (Interrupt / Timer / UART / ADC / PCA / WDT / PORT) OSC CPU PD PD MiDAS2. Family [82]

83 6.6. FLASH Parallel Programming Programming Mode Parallel interface is supported for fast programming. Memory Area Main Area = 62 KBytes EEPROM Area = 2 KBytes Information Area = 6 Bytes Signature Area = 4 Bytes 6-level Protection is supported. Mode RESET, PSEN ALE P3. Control (PROG/ERASE) (INVSTR/RD) P3.7 P3.6 P3.5 P3.4 Program Main Read Main Program EEPROM Read EEPROM RESET = Program Information PSEN = Read Information Erase Read Signature Reliability Characteristics Parameter Endurance Data Retention Minimum Specification, Unit Cycles Years MiDAS2. Family [83]

84 6.7. ISP (In-System Programming) Code memory (62KBytes) can be programmed using EJTAG in target system. EEPROM (2KBytes) can be programmed using EJTAG in target system. EJTAG Port VDD, VSS, MDS_SCK, MDS_SDA, PSEN GENICE Equipment EJTAG Port User s PC MCU MDS Bridge VDD VSS MDS_SCK MDS_SDAT PSEN Target System MiDAS2. Family [84]