Mono/Stereo High-Power Class D Amplifier

Transcription

1 9-38; Rev ; /8 EVALUATION KIT AVAILABLE Mono/Stereo High-Power Class D Amplifier General Description The A/B Class D amplifiers provide high-performance, thermally efficient amplifier solutions. The A delivers 2 x W into 8Ω loads, or x 3W into a Ω load. The B delivers 2 x 6W into 8Ω loads or x 2W into a Ω load. These devices are pinfor-pin compatible, allowing a single audio design to work across a broad range of platforms, simplifying design efforts, and reducing PCB inventory. Both devices operate from 8V to 28V and provide a high PSRR, eliminating the need for a regulated power supply. The offers up to 88% efficiency at 2V supply. Pin-selectable modulation schemes select between filterless modulation and classic PWM modulation. Filterless modulation allows the to pass CE EMI limits with m cables using only a low-cost ferrite bead and capacitor on each output. Classic PWM modulation is optimized for best audio performance when using a full LC filter. A pin-selectable stereo/mono mode allows stereo operation into 8Ω loads or mono operation into Ω loads. In mono mode, the right input op amp becomes available as a spare device, allowing flexibility in system design. Comprehensive click-and-pop reduction circuitry minimizes noise coming into and out of shutdown or mute. Input op amps allow the user to create summing amplifiers, lowpass or highpass filters, and select an optimal gain. The A/B are available in 32-pin TQFN packages and specified over the - C to +8 C temperature range. Features Wide 8V to 28V Supply Voltage Range Spread-Spectrum Modulation Enables Low EMI Solution Passes CE EMI Limits with Low-Cost Ferrite Bead/Capacitor Filter Low BOM Cost, Pin-for-Pin Compatible Family High 67dB PSRR at khz Reduces Supply Cost 88% Efficiency Eliminates Heatsink Thermal and Output Current Protection < µa Shutdown Mode Mute Function Space-Saving, 7mm x 7mm x.8mm, 32-Pin TQFN Package Applications LCD/PDP/CRT Monitors LCD/PDP/CRT TVs MP3 Docking Stations PART AETJ+ 8V TO 28V Ordering Information STEREO/MONO OUTPUT POWER W stereo/ 3W mono Notebook PCs PC Speakers All-in-One PCs PIN-PACKAGE 32 TQFN-EP* 6W stereo/ BETJ+ 32 TQFN-EP* 2W mono Note: All devices are specified over the - C to +8 C operating temperature range. +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad. Simplified Diagram 8Ω AUDIO INPUTS 8Ω INPUT RESISTORS AND CAPACITORS SELECT GAIN AND CUTOFF FREQUENCY SHDN MUTE MONO Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS PVDD to PGND...-.3V to +3V AGND to PGND...-.3V to +.3V INL, INR, FBL, FBR, COM to AGND...-.3V to (V REG +.3V) MUTE, SHDN, MONO, MOD, REGEN to AGND...-.3V to +6V REG to AGND...-.3V to (VS +.3V) VS to AGND (Note )...-.3V to +6V OUTL+, OUTL-, OUTR+, OUTR-, to PGND...-.3V to (PVDD +.3V) CN to PGND...-.3V to (PVDD +.3V) CP to PGND...(PVDD -.3V) to (V BOOT +.3V) BOOT to PGND...(V CP -.3V) to 36V OUTL+, OUTL-, OUTR+, OUTR-, Short Circuit to PGND or PVDD...Continuous Thermal Limits (Notes 2, 3) Continuous Power Dissipation (T A = +7 C) 32-Pin TQFN Single-Layer PCB (derate 27mW/ C above +7 C)...2.6W θ JA...37 C/W θ JC... C/W Continuous Power Dissipation (T A = +7 C) 32-Pin TQFN Multiple Layer PCB (derate 37mW/ C above +7 C) W θ JA...27 C/W θ JC... C/W Operating Temperature Range...- C to +8 C Storage Temperature Range...-6 C to + C Junction Temperature...+ C Lead Temperature (soldering, s)...+3 C Note : VS cannot exceed PVDD +.3V. See the Power Sequencing section. Note 2: Thermal performance of this device is highly dependant on PCB layout. See the Applications Information section for more details. Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD-7, using a -layer board. For detailed information on package thermal considerations, visit Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V PVDD = 2V, V VS = V, AGND = PGND = V, V MOD = V SHDN = V MUTE = V, REGEN = MONO = AGND, C =.µf, C2 = µf, R IN _ = 2kΩ and R FB_ = 2kΩ, R L =, AC measurement bandwidth 22Hz to 22kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +2 C.) (Notes, ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AMPLIFIER DC CHARACTERISTICS Speaker Supply Voltage Range PVDD Inferred from PSRR test 8 28 V Preamplifier Supply Voltage Range VS (Notes and 7).. V Undervoltage Lockout UVLO 7 V Quiescent Supply Current Shutdown Supply Current I SHDN V SHDN = V R T A = +2 C 3 I L =, V REGEN = V, PVDD V VS = open T A = T MIN to T MAX R T A = +2 C 2 I L =, V REGEN = V, VS V VS = V T A = T MIN to T MAX 22 I PVDD I VS REG Voltage V REG.2 V Preregulator Voltage VS Internal regulated V, V REGEN = V.8 V COM Voltage V COM V INPUT AMPLIFIER CHARACTERISTICS Capacitive Drive C L 3 pf Output Swing (Note 6) Sinking ±ma ±2 V Open-Loop Gain A VO V FB_ = V COM ±mv, R FB_ = 2kΩ to IN_ 88 db Input Offset Voltage V OS ± mv ma ma µa 2

3 ELECTRICAL CHARACTERISTICS (continued) (V PVDD = 2V, V VS = V, AGND = PGND = V, V MOD = V SHDN = V MUTE = V, REGEN = MONO = AGND, C =.µf, C2 = µf, R IN _ = 2kΩ and R FB_ = 2kΩ, R L =, AC measurement bandwidth 22Hz to 22kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +2 C.) (Notes, ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Amplifier Slew Rate 2. V/µs Input Amplifier Unity-Gain Bandwidth AMPLIFIER CHARACTERISTICS 3. MHz A Output Amplifier Gain (Note 8) A V B db Output Current Limit A Output Offset V OS OUT_+ to OUT_-, T A = +2 C ±2 ± mv Power-Supply Rejection Ratio A Output Power (THD+N = %) PSRR P OUT_% PVDD = 8V to 28V, T A = +2 C 6 8 f = khz, mv P-P ripple 67 PVDD = 2V R L = 8Ω 8 Stereo R L = Ω 3 Mono R L = Ω. Stereo R L = 8Ω 3. PVDD = 8V Mono RL = Ω 27 Stereo R L = 8Ω 3. PVDD = 2V Mono RL = Ω 27 db W B Output Power (THD+N = %) P OUT_% PVDD = 2V R L = 8Ω 6 Stereo R L = Ω Mono R L = Ω 2 Stereo R L = 8Ω 6 PVDD = 8V Mono RL = Ω 2 W Stereo R L = 8Ω 6 PVDD = 2V Mono RL = Ω 2 A Output Power (THD+N = %) P OUT_% PVDD = 2V R L = 8Ω Stereo R L = Ω 6 Mono R L = Ω 9. Stereo R L = 8Ω 7. PVDD = 8V Mono RL = Ω 3 W Stereo R L = 8Ω 7. PVDD = 2V Mono RL = Ω 3 B Output Power (THD+N = %) P OUT_% PVDD = 2V R L = 8Ω 7. Stereo R L = Ω Mono R L = Ω Stereo R L = 8Ω 7. PVDD = 8V Mono RL = Ω W Stereo R L = 8Ω 7. PVDD = 2V Mono RL = Ω 3

4 ELECTRICAL CHARACTERISTICS (continued) (V PVDD = 2V, V VS = V, AGND = PGND = V, V MOD = V SHDN = V MUTE = V, REGEN = MONO = AGND, C =.µf, C2 = µf, R IN _ = 2kΩ and R FB_ = 2kΩ, R L =, AC measurement bandwidth 22Hz to 22kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +2 C.) (Notes, ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Total Harmonic Distortion Plus Noise THD+N Signal-to-Noise Ratio SNR A-weighted A, P OUT = W, f = khz, PWM modulation mode, R L = 8Ω B, P OUT = 2W, f = khz, PWM modulation mode, R L = 8Ω A, P OUT = 8W, R L = 8Ω B, P OUT = 6W, R L = 8Ω A-weighted A 2 Noise V N (Note 9) B Crosstalk L to R, R to L, P OU T = W, f = kh z, R L = 8Ω db Efficiency η P OU T = 8W, M AX 9736A, P V D D = 2V, R L = 8Ω 88 % Click-and-Pop Level K CP samples/second, A-weighted Peak voltage, 32 (Notes 9 and ) Into mute 36 Out of mute 36 Switching Frequency khz Spread-Spectrum Bandwidth ± khz Thermal Shutdown Level 6 C Thermal Shutdown Hysteresis 3 C Turn-On Time t ON ms DIGITAL INTERFACE Input Voltage High V INH 2 V Input Voltage Low V INL.8 V Input Voltage Hysteresis mv Input Leakage Current ± µa Note : All devices are % production tested at +2 C. All temperature limits are guaranteed by design. Note : Stereo mode (MONO = GND) specified with 8Ω resistive load in series with a 68µH inductive load connected across BTL outputs. Mono mode (MONO = V) specified with a Ω resistive load in series with a 33µH inductive load connected across BTL outputs. Note 6: Output swing is specified with respect to V COM. Note 7: For typical applications, an external V supply is not required. Therefore, set REGEN = V. If thermal performance is a concern, set REGEN = V and provide an external regulated V supply. Note 8: Output amplifier gain is defined as: % db µv RMS dbv ( VOUT_ + ) ( VOUT _ ) 2 log VFB_ Note 9: Amplifier inputs AC-coupled to GND. Note : Specified at room temperature with an 8Ω resistive load in series with a 68µH inductive load connected across BTL outputs. Mode transitions controlled by SHDN control pin.

5 Typical Operating Characteristics (A, PVDD = 2V, MOD = high, spread-spectrum modulation mode, V GND = V PGND = V, V SHDN = V MUTE = V, unless otherwise noted.).. PLUS NOISE vs. FREQUENCY PVDD = 2V, P OUT = W P OUT = 3W toc.. PLUS NOISE vs. FREQUENCY PVDD = 2V, P OUT = W P OUT = 3W toc2.. PLUS NOISE vs. FREQUENCY PVDD = 2V, Ω LOAD P OUT = W P OUT = 3W toc3. k k k FREQUENCY (Hz). k k k FREQUENCY (Hz). k k k FREQUENCY (Hz).. PLUS NOISE vs. FREQUENCY PVDD = 2V, Ω LOAD P OUT = W P OUT = 3W toc. PVDD = 2V, khz toc. PVDD = 2V, khz toc6.. 2Hz 2Hz. k k k FREQUENCY (Hz) PVDD = 8V, khz toc7. PVDD = 8V, khz toc8. PVDD = 2V, toc9. 2Hz. 2Hz. khz 2Hz

6 Typical Operating Characteristics (continued) (A, PVDD = 2V, MOD = high, spread-spectrum modulation mode, V GND = V PGND = V, V SHDN = V MUTE = V, unless otherwise noted.).. PVDD = 2V, khz 2Hz toc.. PVDD = 2V, Ω LOAD khz 2Hz toc.. PVDD = 2V, Ω LOAD khz 2Hz toc (%) vs. TOTAL OUTPUT POWER toc3 PVDD = 2V, POWER DISSIPATION POWER DISSIPATION (W) (%) vs. TOTAL OUTPUT POWER PVDD = 2V, POWER DISSIPATION toc POWER DISSIPATION (W) TOTAL TOTAL (%) vs. TOTAL OUTPUT POWER PVDD = 8V, POWER DISSIPATION toc POWER DISSIPATION (W) (%) vs. TOTAL OUTPUT POWER PVDD = 8V, POWER DISSIPATION toc POWER DISSIPATION (W) TOTAL TOTAL 6

7 Typical Operating Characteristics (continued) (A, PVDD = 2V, MOD = high, spread-spectrum modulation mode, V GND = V PGND = V, V SHDN = V MUTE = V, unless otherwise noted.) (%) vs. TOTAL OUTPUT POWER toc7 PVDD = 2V, POWER DISSIPATION TOTAL POWER DISSIPATION (W) (%) vs. TOTAL OUTPUT POWER toc8 PVDD = 2V, POWER DISSIPATION TOTAL POWER DISSIPATION (W) (%) vs. TOTAL OUTPUT POWER PVDD = 2V, Ω LOAD POWER DISSIPATION toc9 2 TOTAL TOTAL OUTPUT POWER vs. V DD LOAD = 8Ω, f = khz % THD+N % THD+N toc POWER DISSIPATION (W) (%) TOTAL OUTPUT POWER vs. LOAD RESISTANCE V DD = 2V, f = khz, SPREAD SPECTRUM % THD+N % THD+N vs. TOTAL OUTPUT POWER toc2 PVDD = 2V, Ω LOAD POWER DISSIPATION TOTAL toc POWER DISSIPATION (W) TOTAL OUTPUT POWER vs. LOAD RESISTANCE V DD = 8V, f = khz, SPREAD SPECTRUM % THD+N % THD+N toc SUPPLY VOLTAGE (V) LOAD RESISTANCE (Ω) LOAD RESISTANCE (Ω) 7

8 Typical Operating Characteristics (continued) (A, PVDD = 2V, MOD = high, spread-spectrum modulation mode, V GND = V PGND = V, V SHDN = V MUTE = V, unless otherwise noted.) TOTAL TOTAL OUTPUT POWER vs. LOAD RESISTANCE % THD+N % THD+N LOAD RESISTANCE (Ω) PVDD = 2V, SPREAD SPECTRUM toc2 PSRR (db) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY mv P-P, PVDD RIPPLE, -9 k k k FREQUENCY (Hz) toc2 CROSSTALK (db) CROSSTALK vs. FREQUENCY W OUTPUT,, SPREAD SPECTRUM RIGHT TO LEFT LEFT TO RIGHT -2 k k k FREQUENCY (Hz) toc26-2 INBAND OUTPUT SPECTRUM, FIXED FREQUENCY toc27-2 INBAND OUTPUT SPECTRUM, SPREAD SPECTRUM toc28 2 WIDEBAND OUTPUT SPECTRUM, FIXED FREQUENCY toc29 OUTPUT AMPLITUDE (dbv) OUTPUT AMPLITUDE (dbv) OUTPUT AMPLITUDE (dbv) FREQUENCY (khz) -2 2 FREQUENCY (khz) -2. FREQUENCY (MHz) OUTPUT AMPLITUDE (dbv) WIDEBAND OUTPUT SPECTRUM -. FREQUENCY (MHz), SPREAD SPECTRUM toc3 SHDN ON-/OFF-RESPONSE ms/div toc3 SHDN 2V/div OUTPUT V/div MUTE ON-/OFF-RESPONSE ms/div toc32 MUTE 2V/div OUTPUT V/div 8

9 Typical Operating Characteristics (continued) (A, PVDD = 2V, MOD = high, spread-spectrum modulation mode, V GND = V PGND = V, V SHDN = V MUTE = V, unless otherwise noted.) SUPPLY CURRENT (ma) 3 2 SUPPLY CURRENT vs. PVDD SUPPLY VOLTAGE V REGEN = V MUTE = V SHDN = 3.3V toc33 SUPPLY CURRENT (ma) 2 SUPPLY CURRENT vs. PVDD SUPPLY VOLTAGE V REGEN = V, V MUTE = V SHDN = 3.3V, VS = V toc3 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. VS SUPPLY VOLTAGE V REGEN = V, V MUTE = V SHDN = 3.3V toc SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VS VOLTAGE (V) SHUTDOWN CURRENT (μa) SHUTDOWN CURRENT vs. PVDD SUPPLY VOLTAGE V REGEN = V SHDN = V, V MUTE = 3.3V toc36.. PLUS NOISE vs. FREQUENCY PVDD = 2V, Ω LOAD, MONO P OUT = 6W P OUT = W toc37.. PLUS NOISE vs. FREQUENCY PVDD = 2V, Ω LOAD, MONO P OUT = W P OUT = 6W toc SUPPLY VOLTAGE (V) PVDD = 2V, Ω LOAD, MONO. k k k FREQUENCY (Hz) toc39. k k k FREQUENCY (Hz) PLUS NOISE vs. OUTPUT POWER (V DD = 2V, Ω LOAD, MONO) toc khz. khz.. 2Hz Hz

10 Typical Operating Characteristics (continued) (A, PVDD = 2V, MOD = high, spread-spectrum modulation mode, V GND = V PGND = V, V SHDN = V MUTE = V, unless otherwise noted.) PVDD = 8V, Ω LOAD, MONO toc PVDD = 8V, Ω LOAD, MONO toc2 PVDD = 2V, Ω LOAD, MONO toc3. khz. khz. khz PLUS NOISE vs. OUTPUT POWER (V DD = 2V, Ω LOAD, MONO). khz 2Hz 2Hz toc (%) 2Hz Hz vs. OUTPUT POWER PVDD = 8V PVDD = 2V PVDD = 2V Ω LOAD, MONO, khz FIXED FREQUENCY 2 toc (%) vs. OUTPUT POWER PVDD = 2V PVDD = 8V PVDD = 2V Ω LOAD, MONO, f = khz SPREAD SPECTRUM 2 toc6 OUTPUT POWER vs. V DD (LOAD = Ω, f = khz, MONO) % THD+N Ω LOAD f = khz, MONO SUPPLY VOLTAGE (V) % THD+N toc7

11 Typical Operating Characteristics (continued) (A, PVDD = 2V, MOD = high, spread-spectrum modulation mode, V GND = V PGND = V, V SHDN = V MUTE = V, unless otherwise noted.) OUTPUT POWER vs. LOAD RESISTANCE % THD+N PVDD = 2V, MONO, SPREAD SPECTRUM % THD+N LOAD RESISTANCE (Ω) toc OUTPUT POWER vs. LOAD RESISTANCE % THD+N PVDD = 8V, MONO, SPREAD SPECTRUM % THD+N LOAD RESISTANCE (Ω) toc OUTPUT POWER vs. LOAD RESISTANCE % THD+N PVDD = 2V, MONO, SPREAD SPECTRUM % THD+N LOAD RESISTANCE (Ω) toc SUPPLY CURRENT (ma) 3 SUPPLY CURRENT vs. PVDD SUPPLY VOLTAGE V REGEN = V MUTE = V SHDN = 3.3V, MONO toc SUPPLY CURRENT (ma) 2 SUPPLY CURRENT vs. PVDD SUPPLY VOLTAGE V REGEN = V, V MUTE = V SHDN = 3.3V, VS = V, MONO toc2 SUPPLY CURRENT (ma) 2 SUPPLY CURRENT vs. VS VOLTAGE V REGEN = V, V MUTE = V SHDN = 3.3V, MONO toc SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VS VOLTAGE (V)

12 PIN NAME FUNCTION, 2 OUTL- Left-Channel Negative Speaker Output 3 BOOT Charge-Pump Output. Connect a µf charge-pump holding capacitor from BOOT to PGND. MONO Mono Select. Set MONO high for mono mode, low for stereo mode. Pin Description FBL Left-Channel Feedback. Connect feedback resistor between FBL and INL to set amplifier gain. 6 INL Stereo Left-Channel Inverting Input. In mono mode, INL is the inverting audio input for the mono amplifier. 7, 8, 7 N.C. No Connection. Not internally connected. OK to connect to PGND. 9 MUTE Mute Input. Drive MUTE low to place the device in mute mode. SHDN Shutdown Input. Drive SHDN low to place the device in shutdown mode. REGEN Internal Regulator Enable Input. Connect REGEN to SHDN to enable the internal regulator. Drive REGEN low to disable the internal regulator, and supply the device with an external V supply on VS. See the Power-Supply Sequencing section. 2 COM Internal 2V Bias. Bypass COM to AGND with a µf capacitor. 3, AGND Analog Ground REG Internal Regulator Output. Bypass REG to AGND with a µf capacitor. 6 VS V Regulator Supply. Bypass VS to AGND with a µf capacitor. If REGEN is low, the internal regulator is disabled, and an external V supply must be connected to VS. See the Power-Supply Sequencing section. 8 INR Stereo Right-Channel Inverting Audio Input. In mono mode, INR is the inverting audio input for the uncommitted preamplifier (see the Mono Configuration section for more details). 9 FBR Right-Channel Feedback. Connect feedback resistor between FBR and INR to set amplifier gain. 2 MOD Output Modulation Select. Sets the output modulation scheme: V MOD = Low, classic PWM/fixed-frequency mode V MOD = High, filterless modulation/spread-spectrum mode 2 CN Charge-Pump Flying-Capacitor Negative Terminal 22 CP Charge-Pump Flying-Capacitor Positive Terminal 23, 2 OUTR- Right-Channel Negative Speaker Output 2, 26 OUTR+ Right-Channel Positive Speaker Output 27, 3 PVDD Power Supply. Bypass each PVDD pin to ground with.µf capacitors. Also, use a single 22µF capacitor between PVDD and PGND. 28, 29 PGND Power Ground 3, 32 OUTL+ Left-Channel Positive Speaker Output EP Exposed Pad. Must be externally connected to PGND. 2

13 Detailed Description The A/B filterless, stereo Class D audio power amplifiers offer Class AB performance and Class D efficiency with minimal board space. The A outputs 2xW in stereo mode and 3W in mono mode. The B outputs 2x6W in stereo mode and 2W in mono mode. These devices operate from an 8V to 28V supply range. The features a filterless, spread-spectrum switching mode (MOD = high) or a classic PWM fixedfrequency switching mode (MOD = low). The features externally set gain and a lowpower shutdown mode that reduces supply current to less than µa. Comprehensive click-and-pop circuitry minimizes noise into and out of shutdown or mute. Operating Modes Filterless Modulation/PWM Modulation The features two output modulation schemes, filterless modulation (MOD = high) or classic PWM (MOD = low). Maxim s unique, filterless modulation scheme eliminates the LC filter required by traditional Class D amplifiers, reducing component count, conserving board space, and reducing system cost. Configure for classic PWM output when using a full LC filter. Click-and-pop protection does not apply when the output is switching between modulation schemes. To maintain click-and-pop protection when switching between output schemes the device must enter shutdown mode and be configured to the new output scheme before the startup sequence is finished. Spread-Spectrum Mode The features a unique, patented spread-spectrum mode that flattens the wideband spectral components, improving EMI radiated by the speaker and cables. The switching frequency of the Class D amplifier varies randomly by ± around the 3kHz center frequency. Instead of a large amount of spectral energy present at multiples of the switching frequency, the energy is spread over a bandwidth that increases with frequency. Above a few megahertz, the wideband spectrum looks like white noise for EMI purposes. A proprietary amplifier topology ensures this white noise does not corrupt the noise floor in the audio bandwidth. The spreadspectrum mode is enabled only with filterless modulation. Efficiency The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as switches and consume negligible power. Power loss associated with the Class D output stage is due to the I 2 R loss of the MOSFET on-resistance, various switching losses, and quiescent current overhead. The theoretical best efficiency of a linear amplifier is 78% at peak output power. Under typical music reproduction levels, the efficiency falls below 3%, whereas the exhibits > 8% efficiency under the same conditions (Figure ). Shutdown The features a shutdown mode that reduces power consumption and extends battery life in portable applications. The shutdown mode reduces supply current to µa (typ). Drive SHDN high for normal operation. Drive SHDN low to place the device in low-power shutdown mode. In shutdown mode, the outputs are high impedance; and the common-mode voltage at the output decays to zero. In shutdown mode, connect REGEN low to minimize current consumption. Mute Function The features a clickless-and-popless mute mode. When the device is muted, the signal is attenuated at the speaker and the outputs stop switching. To mute the, drive MUTE low. Hold MUTE low during system power-up and power-down to ensure that clicks and pops caused by circuits before the are suppressed. (%) vs. TOTAL OUTPUT POWER A CLASS AB 2 TOTAL fig Figure. A Efficiency vs. Class AB Efficiency 3

14 Click-and-Pop Suppression The features comprehensive click-and-pop suppression that minimizes audible transients on startup and shutdown. While in shutdown, the H-bridge is in a high-impedance state. Mono Configuration The features a mono mode that allows the right and left channels to operate in parallel, achieving up to 3W (A) of output power. Apply a logichigh to MONO to enable mono mode. In mono mode, an audio signal applied to the left channel (INL) is routed to the H-bridges of both channels. Also in mono mode, the right-channel preamplifier becomes an uncommitted operational amplifier, allowing for flexibility in system design. Connect OUTL+ to OUTR+ and OUTL- to OUTR- using heavy PCB traces as close as possible to the device. Driving MONO low (stereo mode) while the outputs are wired together in mono mode can trigger the short-circuit or thermal-overload protection or both. Current Limit When the output current reaches the current limit,.6a (typ), the disables the outputs and initiates a µs startup sequence. The shutdown and startup sequence is repeated until the output fault is removed. Properly designed applications do not enter currentlimit mode unless the output is short circuited or connected incorrectly. Thermal Shutdown When the die temperature reaches the thermal shutdown threshold, +6 C (typ), the outputs are disabled. When the die temperature decreases by 3 C, normal operation resumes. Some causes of thermal shutdown are excessively low load impedance, poor thermal contact between the s exposed pad and the PCB, elevated ambient temperature, or poor PCB layout and assembly. Applications Information Filterless Class D Operation The meets EN22B EMC radiation limits with an inexpensive ferrite bead and capacitor filter when the speaker leads are less than or equal to m. Select a ferrite bead with Ω to 6Ω impedance and rated for at least 2A. The capacitor value varies based on the ferrite bead chosen and the speaker lead length. See Figure 3 for the correct connections of these components. AMPLITUDE (dbμv/m) Figure 2. EMI Performance FB AND FB2 = WURTH Figure 3. Ferrite Bead Filter EN22B LIMIT FREQUENCY (MHz) FB FB2 Figure. Output Filter for PWM Mode L L2 C 33pF C2 33pF When evaluating the with a ferrite bead filter and resistive load, include a series inductor (68µH for 8Ω load and 33µH for Ω load) to model the actual loudspeaker s behavior. Omitting the series inductor C C3 C2 C R2 C R

15 Table. Suggested Values for LC Filter R L (Ω) L, L2 (µh) C (µf) C2, C3 (µf) C, C (µf) R, R2 (Ω) reduces the efficiency, the THD+N performance, and the output power of the. When evaluating with a load speaker, no series inductor is required. Inductor-Based Output Filters Some applications use the with a full inductor-/capacitor-based (LC) output filter. Select the PWM output mode for best audio performance. See Figure for the correct connections of these components. The load impedance of the speaker determines the filter component selection (see Table ). Inductors L and L2, and capacitor C form the primary output filter. Capacitors C2 and C3 provide commonmode filtering to reduce radiated emissions. Capacitors C and C, plus resistors R and R2, form a Zobel at the output. A Zobel corrects the output loading to compensate for the rising impedance of the loudspeaker. Without a Zobel the filter exhibits a peak response near the cutoff frequency. Component Selection Gain-Setting Resistors External feedback resistors set the gain of the. The output stage provides a fixed internal gain in addition to the externally set input stage gain. For the A, the fixed output-stage gain is set at 7dB (7V/V). For the B, the fixed output-stage gain is set at 3.6dB (.8V/V). Set overall gain by using resistors R F and R IN (Figure ) as follows: R MAX A A F 9736 : V = 7. V/ V R IN R MAX B A F 9736 : V =. 8 V/ V R IN where A V is the desired voltage gain. Choose R F between kω and kω. The FB terminal is an op amp output and the IN terminal is the op amp inverting input, allowing the to be configured as a summing amplifier, a filter, or an equalizer. Input Capacitor An input capacitor, C IN, in conjunction with the input resistor, R IN, of the forms a highpass filter that removes the DC bias from an incoming signal. The AC-coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: f 3dB = 2πRINCIN Choose C IN so that f -3dB is well below the lowest frequency of interest. Use capacitors whose dielectrics have low voltage coefficients. Capacitors with high-voltage coefficients cause increased distortion close to f -3dB. COM Capacitor COM is the output of the internally generated DC bias voltage. Bypass COM with a µf capacitor to AGND. Power Supplies The features separate supplies for signal and power portions of the device, allowing for the optimum combination of headroom, power dissipation, and noise immunity. The speaker amplifiers are powered from PVDD and can range from 8V to 28V. The remainder of the is powered by VS. Power-Supply Sequencing During power-up and power-down, VS must not exceed PVDD. VS greater than PVDD will damage the device. AUDIO INPUT C IN R IN C COM R F FB_ IN_ COM OUT_+ OUT_- Figure. Setting Gain

16 Internal Regulator The features an internal V regulator, VS, powered from PVDD. Connect REGEN to SHDN so that the internal V regulator is enabled/disabled when the is enabled/disabled. If an external V supply is available, drive REGEN low and connect external V supply to VS to minimize the power dissipation of the. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. Use wide traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents switching noise from coupling into the audio signal. Connect PGND and AGND together at a single point on the PCB. Route all traces that carry switching transients away from AGND and the traces/components in the audio signal path. Bypass each PVDD pin with a.µf capacitor to PGND. Place the bypass capacitors as close as possible to the. Place a 22µF capacitor between PVDD and PGND. Bypass VS with a µf capacitor to AGND. Use wide, low-resistance output traces. Current drawn from the outputs increases as load impedance decreases. High-output trace resistance decreases the power delivered to the load. The TQFN package features an exposed thermal paddle on its underside. This paddle lowers the package s thermal resistance by providing a heat conduction path from the die to the PCB. Connect the exposed thermal pad to PGND by using a large pad and multiple vias to the PGND plane. 6

17 Typical Application Circuit for Stereo Output Configuration μf 8V TO 28V.μF.μF C BULK 22μF C.μF VS PVDD CP CN 6 27, μf REG REGULATOR CHARGE PUMP 3 BOOT C2 μf 2kΩ FBL 2kΩ INL 6 3, 32 OUTL+ 7nF, 2 OUTL- μf COM 2 BIAS POWER STAGE 2kΩ INR 8 2, 26 OUTR+ 7nF 2kΩ FBR 9 23, 2 OUTR- REGEN SHUTDOWN MUTE V SHDN MUTE MOD 9 2 CONTROL MONO 3, 28, 29 7, 8, 7 AGND PGND N.C. NOTE: PREAMPLIFIER GAIN SET AT db. 7

18 Typical Application Circuit for Single (Mono) Output Configuration 8V TO 28V.μF.μF C BULK 22μF μf C.μF VS PVDD CP CN 6 27, μf REG REGULATOR CHARGE PUMP 3 BOOT C2 μf LPF FBR FBL INL 6 3, 32 OUTL+, 2 OUTL- HPF μf COM 2 BIAS POWER STAGE AUDIO INPUT INR 8 FBR 9 2, 26 OUTR+ 23, 2 OUTR- FBR REGEN SHUTDOWN MUTE V SHDN MUTE MOD 9 2 CONTROL MONO 3, 28, 29 7, 8, 7 AGND PGND N.C. 8

19 TOP VIEW OUTR+ OUTR+ PVDD PGND PGND PVDD OUTL+ OUTL+ OUTL- OUTR- OUTR- Pin Configuration VS 26 REG 27 AGND 28 3 AGND 29 2 COM 3 REGEN OUTL- BOOT CP CN MOD MONO FBL FBR INR 3 + EP* INL N.C. N.C. N.C. SHDN MUTE PROCESS: BiCMOS Chip Information TQFN-EP (7mm 7mm.8mm) EP* = EXPOSED PAD, CONNECT TO PGND. 9

20 Package Information For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 TQFN-EP T ,, 8L QFN.EPS 2

21 Package Information (continued) For the latest package outline information and land patterns, go to 2

22 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED /8 Initial release 2/8 Corrected various errors, 7 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.