PIDcontrollerIPCoreusermanual
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1 Author:ZhuXu Introduction PIDcontrollerIPCoreusermanual The PID controller IP core performs digital proportional integral derivative controller (PID controller) algorithm. The algorithm first calculates the error betweenameasuredvalue(pv)anditsidealvalue(sp),thenusetheerrorasan argumenttocalculatethemanipulatevalue(mv).themvwilladjusttheprocessto minimizetheerror.itcanbeusedtocalculatedutycycleforpwm(pulse Width Modulation). Features 16-bitsignedcoefficientanddatainput:Kp,Ki,Kd,SPandPV. 32-bitsignedu(n)output. Containingonehighspeed32-bitprefix-2Han-Carlsonadderand one high speedpipelined16x16-bitmultiplier. LatencyfrominputofPVtofinishedcalculationandupdateofu(n)is17clock cycles. Ki,Kp,Kd,SP,PVcanbeupdatedanytimeafterreset. AftereveryupdateofKporKd,registerKpdwhichstoresKp+Kd will be calculatedandupdated. AftereveryupdateofPV,calculationandupdateofe(n),e(n-1),sigmaandu(n) willbetriggeredinsequence. OverflowregisterrecordsoverflowsignalswhencalculatingKpd,e(n),e(n-1),u(n) andsigma. Using2278of4608(49%)CoreCellsinActelA2F200M3FFPGAandrunningat 100MHzclockfrequency. WishboneB4compliantinterface.Support16-bit,32-bitand64-bitbuswidth. PIDcontrollerdescription BelowdescribethealgorithmofPIDcontroller. Analog APIDismadeofthreebasicblockswhoseoutputsare: Proportionaltotheinput Theintegraloftheinput 1
2 Thederivativeoftheinput Figure1showstheblockdiagramofagenericsystemcontrolledbyPIDcontroller. ThegoalofthePIDblockistogenerateanoutputu(t)thatdrivesthesystemat hand(the PLANT )sothatitsoutput[y(t)orpv,processvalue] matches a referencesignal[x(t)orsp,setpoint].theinputtothepidistheerrorbetweenthe reference signal (ideal or desired behavior of the PLANT) and the real output behavior.obviously,thetargetistogettheerrorasclosetozeroaspossible. Figure1:agenericsystemcontrolledbyPID TheequationthatdescribesthePIDcontrollerbehaviorincontinuoustimedomain isshowninequation1. Equation1 Digital Transformequation1intodiscretetimedomainwegetequation2. u(n) (K p K )e(n) K d n i j 1 e(j) K e(n 1) Equation2 Fromequation2wecanconstructthealgorithm sblockdiagramshowninfigure2. d 2
3 Operation Figure2:digitalPIDcontrolleralgorithm Coefficients and Data Update Coefficients(Kp,Ki,Kd,PV)andmeasuredprocessvalue(PV)arestoredindifferent registersthatbereadandwrittenanytimeafterresetbyahostthroughwishbone slaveinterface.normally,kp,ki,kd,pvareupdatedrightafter reset before continuouslyupdateofpv.youalsocanupdatecoefficientsrandomlyfordynamic tuning.writingactiontospecificregistersmentionedabovewon tberesponded untilfinishedcalculationofthelastu(n). Calculation of u(n) Calculation of u(n) will be triggered every time PV is updated.thecalculation procedureisdemonstratedinfigure3. Update of overflow register OverflowregisterrecordsanyoverflowsignalinpreviouscalculationsofKpd,e(n), e(n-1),u(n)andsigma.itwillbeupdatedaftereveryadditionoperation.ifanyof the5overflowregisterbitsisset,thenthefinalu(n)isincorrect. 3
4 Figure3:calculationprocedureofu(n) Registers Address for Name 16-bit/32-bit/64-bitbus Width Access Description width Kp Base+0x0/0/0 16 R/W StorescoefficientKp Ki Base+0x2/4/8 16 R/W StorescoefficientKi Kd Base+0x4/8/10 16 R/W StorescoefficientKd SP Base+0x6/C/18 16 R/W StoresreferenceSP PV Base+0x8/10/20 16 R/W StoresPV Kpd Base+0xA/14/28 16 R StorescoefficientKp+Kd err[0] Base+0xC/18/30 16 R Storese(n) err[1] Base+0xE/1C/38 16 R Storese(n-1) un Base+0x10/20/40 32 R Storesu(n) sigma Base+0x12/24/48 32 R Stores K e(j n i ) j 1 of Base+0x14/28/50 5 R of[0]==1ifkpdoverflows, of[1]==1iferr[0]overflows, of[2]==1iferr[1]overflows, of[3]==1ifunoverflows, of[4]==1ifsigmaoverflows 4
5 I/Oports TheIPcorehasaWishboneSlaveInterfaceandanotherinterfacefordirect32-bit u(n)output. Wishbone Slave Interface It swishboneb4compliant. Name in Name Wishbone Size Direction Description B4 i_clk CLK_I 1 input Clockinput i_rst RST_I 1 input Resetinput i_wb_cyc CYC_I 1 input Indicatesvalidbuscycle(coreselect) i_wb_stb STB_I 1 input Indicatesvaliddatatransfercycle i_wb_we WE_I 1 input Writetransactionwhenassertedhigh i_wb_adr ADR_I 16 input Addressinput i_wb_data DAT_I 16/32/64 input Datainput o_wb_ack ACK_O 1 output Acknowledgment output (indicates normaltransactiontermination) o_wb_data DATA_O 16/32/64 output Dataoutput Direct 32-bit u(n) output Name Size Direction Description o_un 32 output u(n)output o_valid 1 output Indicatesvalido_un 5
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