3 CHAPTER III DESIGN, MODELING AND CONTROL OF VSC BASED HVDC SYSTEM

Transcription

1 3 CHAPTER III DESIGN, MODELING AND CONTROL OF VSC BASED HVDC SYSTEM The voltage source converter (VSC) is the prime unit of a VSC based HVDC system, therefore, its design and performance evaluation is most important to have desired results. This chapter deals with design, modelling and control of VSC for back-to-back AC interconnection and long distanced transmission between two AC networks using HVDC system. The functionality of VSC based HVDC system depends on proper selection of switch rating, interfacing reactor, and DC-link capacitor. The voltage source converter is designed with self-commutated IGBT switch which has combined features of MOSFETs and bipolar junction transistor (BJTs) switch. It has gate, driven like MOSFETs and voltage/current characteristics like BJTs, thereby IGBTs operate at very high current (>1000A) and switched at higher frequency more that 3 to 4 times as compared to GTOs. Therefore, the IGBT switch has high current handling capability and ease of controllability. However, HVDC converters can be switched up to 2 khz frequency to make the switching loss within acceptable limit [Luth, et al., 2014]. The DC-link capacitor acts as an energy buffer to stabilize DC-link voltage under normal as well as transient condition. The large value of capacitor may create harmonic distortion in input source whereas low value may cause instability in power transmission. Hence, proper selection of DC-link capacitor is a significant part in VSC designing [Mohan, 2003; Rashid, 1990]. The DC-link capacitor is designed based on number of factors such as power rating of VSC HVDC system, magnitude of DC link voltage, and recovery time under transient 48

2 condition etc. The selection of interfacing inductor and DC-link capacitor depends on rating of point-of-common coupling (PCC) load and AC main voltage. 3.1 DESIGN OF BACK-TO-BACK VSC BASED HVDC POWER TRANSMISSION Back-to-back (BTB) HVDC interconnections are used for power transfer between two independent neighboring AC systems via DC-link. The rectifier and inverter are located in same station having practically zero meter long transmission between them. The BTB configuration is used for number of reasons such as: To connect asynchronous high-voltage power systems with different frequencies To stabilize weak AC links To transmit reliable power To control of grid power-flow within synchronous AC systems The VSC based HVDC system is composed of self-commutated switch, interfacing reactor, DC-link capacitor. The rectifier and inverter are connected back-to-back as shown in schematic diagram of Figure 3.1. VA PCC1 L PCC2 N VB Voltage source converter Cdc Voltage source converter VC Grid Figure 3.1 Schematic diagram of VSC based BTB HVDC system Selection of VSC switch rating The proposed HVDC system is designed for rated voltage for 33kV, 100MW with 0.9 pf PCC load. Therefore, Supply current = Apparent power/ (3 supply voltage) 49

3 Irms = VA/ (3 Vs) = P/ (3 pf Vs) (3.1) The RMS value of supply current is calculated as 1.94kA for 100MW load. The crest factor is usually considered 2 or 3, therefore, peak load current (Ip) is calculated for crest factor value 2, as, Ip = 3.88kA (3.2) Therefore, the current rating of IGBTs for VSC designing is considered as 4kA. The voltage rating of IGBTs switch is calculated as, Vp = 2 Vrms (3.3) Considering the isolated transformer 33/2.1kV is used in between supply and the VSC, the peak voltage is calculated as 2.96kV. Considering the safety factor 2, the switch rating come to be 5.96kV. Therefore, rating of IGBTs switch in VSC designing is selected as 6.5kV, 4kA. However, IGBT switch is available of the current rating 1.2kA [Lobsiger, et al., 2015], therefore to increase current rating of the valves, four parallel switches are connected in the designing of HVDC system Selection of Interfacing Inductor The rating of interfacing inductor (L) should be selected for limiting the 5 th harmonic current in conventional line commutated thyristor based HVDC system [Mohan, et al., 2010]. This selection criteria is also applicable in VSC based HVDC system. The calculation of interfacing inductor is given as, Base impedance Zbase = (kv) 2 / MVA = (33) 2 /100 = (3.4) XL = 0.2*Zbase, L = XL / 2πf (3.5) The interfacing inductor is estimated 0.336H value. 50

4 3.1.3 Selection of DC-link capacitor The system is designed for 100MW, 0.9pf PCC load. The total MVA rating of converter is 112MVA with 100MW active power load and 50Mvar reactive power load. By considering safety factor, MVA rating is considered as 120MVA. The VSC is rated for full reactive power of 50Mvar whereas 1.09% is used for active power rating. Extra 9% of active power (9MW) is compensated by DC-link capacitor voltage [Madhan Mohan, et al., 2009]. It is desired to settle DC-link voltage within six cycles for 5% overshoot allowed under Transient condition. By considering all factors, DC-link capacitor is calculated as follows, E = P.Δt = (1/2). Cdc. {(V*dc) 2 -(Vdc) 2 } (3.6) The capacitor, Cdc is obtained as 1250mF. 3.2 DESIGN OF VSC BASED HVDC SYSTEM WITH TRANSMISSION LINE Whenever the power has to be transmitted over long distance, HVDC transmission is the most economical option as compared to high voltage AC transmission. Two remote AC systems are coupled together via typically 300 to 3000km by overhead line or 10 to 800km by DC cable [Bahrman, et al., 2014]. The schematic diagram of VSC based HVDC system with long distance transmission line is shown in Figure 3.2. The two AC networks are connected with 75km long transmission line for power balance. The interfacing reactor and DC-link capacitor plays significant role for efficient power flow in HVDC transmission system Selection of interfacing Inductor The interfacing inductor is selected to limit 5 th harmonic current as required in conventional thyristor based HVDC system. 51

5 Base impedance Zbase = (kv) 2 / MVA (3.7) XL = 0.2*Zbase (3.8) L = XL / 2πf (3.9) Interfacing inductor (L) is obtained 6.9mH. VA PCC1 L DC cable PCC2 N VB Voltage source converter Cdc Cdc Voltage source converter VC Grid Figure 3.2 Schematic diagram of VSC based HVDC system with transmission line Selection of DC-link capacitor For 100MW, 0.9 pf load, total system rating S = P 2 +Q 2 = 112MVA with 48.42MVar reactive power, by considering safety factor, total rating is assumed 120MVA. The system is designed with full reactive power whereas 1.09% is considered for active power. Extra 9% active power (9MW) is assumed for compensation provided by DC-link capacitor [Hammad, et al., 1990]. In this system, it is desired to settle the DC-link voltage within six cycles for 5% maximum overshoot or undershoot allowed. Therefore, the value of DC-link capacitor is obtained as, E = P.Δt = (1/2). Cdc. {(V*dc) 2 -(Vdc) 2 } (3.10) Substituting the values, P = 9MW, Δt = 6*20ms, Vdc = 180.5kV, V * dc = 190kV in Eqs (3.10) the value of Cdc is estimated as 2040μF, therefore, capacitor for 2200μF is selected by considering practical value. 3.3 MODELING OF VSC BASED HVDC SYSTEM The system is controlled by pulse width modulation (PWM) technique, having constant pulse amplitude with modulating duty cycle. The duty cycle of VSC switch is decided by three variables, namely referenced DC-link voltage, 3-phase voltage and 3-phase current. 52

6 The PWM technique based current multiplier technique is used to control VSC based HVDC system. This technique has two simple proportional and integral (PI) cascaded control loops, namely voltage control loop and current control loop. The schematic diagram is shown in Figure 3.3. The controller output is influenced by controller gains and voltage error, obtained by comparing desired and measured quantity, thereby transmits controlled output in every sample time (T) to final output. The proportional controller quickly respond to change in error deviation, wherein integral controller eliminates offset error. The function of both controllers are discussed as below, Grid VA IA PCC L N VB VC IB IC Voltage source converter Cdc Current control loop Unit template VSC controller Current sensing * IA Voltage control loop Vdc* PWM Pulse Generator Sa Sb Sc Current Controller IB * Icon Ve Vdc IC * Ref. Current Generator Voltage Controller Voltage control loop Figure 3.3 Schematic diagram of current multiplier approach The voltage control loop calculates voltage error and accordingly generates modulating signal for current controller as shown in Figure 3.4-Figure 3.5. The control scheme starts with sensing DC-link voltage (Vdc) and compared with desired or reference DC-link voltage (V * dc), results voltage error (Ve). The voltage error is passed to the voltage controller. A simple proportional-integral (PI) controller is used as a voltage 53

7 controller which closely monitors voltage error and generates control signal (Icon) to reduce voltage error (Ve) as shown in Figure 3.4. At kth instant, the voltage error is measured as, Ve(k) = V * dc(k)-vdc(k) (3.11) Where V * dc and Vdc are reference and measured DC-link voltage respectively. The control signal (Icon) is calculated as, Figure 3.4 DC-link voltage error calculation At (k-1) th instant Figure 3.5 Modulating control signal generation Icon (k-1) = kpvve(k-1) + kivʃ Ve(k-1)dt (3.12) Icon (k) = kpvve(k) + kiv{ʃ Ve(k)dt+ Ve(k-1)} (3.13) Icon (k)-icon (k-1) = kpv{ve(k)-ve(k-1)} + kivve(k) (3.14) Icon (k) = Icon (k-1) + kpv{ve(k)-ve(k-1)} + kivve(k) (3.15) Equation (3.15) shows generated control signal by the voltage controller. Where kpv and kiv are proportional and integral gain of voltage controller respectively. 54

8 3.3.2 Current Control loop The current control loop composites with reference current generator, current controller and PWM pulse generator as shown in Figure 3.6-Figure The obtained modulating signal is multiplied with unit template of AC-supply voltage as calculated in Figure 3.6, generates three-phase current references. Since, objective of control scheme is to force supply current to follow supply voltage to make power factor unity value, therefore, this signal is multiplied with three-phase unit template of input AC voltage and generates reference current as shown in Figure 3.7. I * A = Icon vsa, I * B = Icon vsb, I * C = Icon vsc (3.16) where vsa = VA/VL, vsb = VB/VL, vsc = VC/VL and VL is terminal voltage and its value is {(2/3) (V 2 A+V 2 B+V 2 C)} Figure 3.6 Unit template calculation Figure 3.7 Reference current generator 55

9 Current controller The current controller is also a simple PI controller which closely observes the three phase current errors as shown in Figure 3.8 and generates modulating signals for phase A, B and C to minimize three phase current errors. Figure 3.8 Calculation of three-phase current errors Figure 3.9 Generation of modulating signal At kth instant, the current errors are sampled as, ΔIa (k) = I * A(k)-IA(k) (3.17) ΔIa (k-1) = I * A(k-1)-IA(k-1) (3.18) Sa (k-1) = kpc ΔIa (k-1)+ kicʃ ΔIa (k-1)dt (3.19) Sa (k) = kpc ΔIa (k) + kic{ʃ ΔIa (k)dt+ ΔIa (k-1)} (3.20) Sa (k)-sa (k-1) = kpc{ ΔIa (k) - ΔIa (k-1)} + kicδia (k) (3.21) Sa(k) = Sa(k-1) + kpc{ ΔIa (k) - ΔIa (k-1)} + kicδia (k) (3.22) Similarly Sb, Sc modulating signals are calculated for phase B and phase C respectively. The generated control signals are shown in Figure

10 PWM pulse generator The voltage modulating signals for phase A, B and C are compared with carrier signals. Two types of signals are used for PWM pulse generation, namely voltage modulating signal and carrier wave signal. Both signals are passed to the comparator which generates pulse for switches based on some logical operations. The carrier signal can be either triangular wave or saw tooth wave at a frequency significantly greater than the modulating signal. In contrast to the saw tooth carrier wave, the triangular carrier signal keeps in center of each PWM pulse at constant phase relative to the PWM sampling interval. This waveform is called centered aligned signal because it is symmetric in both side. This results fewer harmonics than saw tooth waveform. The control signals are further compared with triangular carrier signal m(t) of fixed frequency (fs) to generate PWM pulses for VSC converter switches as presented in Figure The duty cycle of switches controls DC-link voltage as well as AC input mains current. If Sa m(t) then Supper = 1else 0 (3.23) If Sa m(t) then Slower = 1else 0 (3.24) The nomenclatures i.e. 1 and 0 depict on and off position of the switch respectively and Supper, Slower are upper and lower switch of same lag of phase (A or B or C). Both switches (Supper, Slower) are never switched on or off simultaneously; hence phase voltage fluctuates between ±Vdc/2. VAO = +Vdc/2 for Supper = 1 (3.25) VAO = -Vdc/2 for Slower = 1 (3.26) VAO = 0 for IA = 0 (3.27) Where o is virtual mid-point in DC link voltage as shown in Figure

11 Vtri Vcontrol,A Vcontrol, B Vcontrol, C o t VAN Vdc o VBN t Vdc o t VAB = VAN-VBN Vdc o t Figure 3.10 Three-phase PWM waveform + +Vdc/2 Supper Vdc o A IA -Vdc/2 Slower - N Figure 3.11 Phase A pulse sequence 3.4 CONVENTIONAL CONTROLLER TUNING APPROACH Conventionally, Zeigler Nichols approach is used to tune proportional, integral and derivative controller gain according to transient conditions. This stochastic approach is based on rule of thumb, an intuitive judgment, stereotyping, and common sense. It mainly 58

12 concentrates on proportional gain tuning, accordingly integral and derivative gain are tuned. Initially, integral and derivative controller gain are deactivated, the proportional controller is reset by its minimum offset value and slowly increases up to that value at which system starts sustained oscillations. Further, offset error between desired and measured value is mitigated by integral and derivative gain. Figure 3.12 shows system behavior under load perturbation transient condition, the time period of oscillation is called as critical time period (1/Tcr) and the value at which system starts sustained oscillation, considered as critical proportional gain (kcr). Some specific rules are used to calculate effective proportional and integral gain [Rao, et al., 1978; Hang, et al., 1991] as mentioned in Table 3.1. Different combination of proportional, integral and derivative controller are given in Table 3.1, however, simple PI controller is used in this proposed work, therefore, effective proportional and integral gain are calculated as, Table 3.1 Tuning rules for Ziegler-Nichols approach Controller type kp Ti Td P 0.5(kcr) 0 PI 0.45(kcr) (Tcr)/12 0 PID 0.6(kcr) 0.5(Tcr) 0.125(Tcr) C(t) 1 T cr Figure 3.12 System response t kp = (0.45) (kcr) (3.28) Ti = (1/12) (Tcr) (3.29) ki = 1/Ti (3.30) Though two controller are used in the proposed current multiplier approach, initially current controller remains inactive, the system is tuned with voltage controller only as the 59

13 rule mentioned above. Then current controller is introduced and start tuning of current controller gain while keeping same value of voltage controller as calculated above. The controller gains are calculated, accordingly the transient conditions. 3.5 PERFORMANCE EVALUATION OF VSC BASED HVDC SYSTEM The designed VSC based HVDC system is controlled with current multiplier approach. In the control scheme, voltage and current controller gains are tuned with Zeigler-Nichols approach. Since the transmission system is subjected with number of transient conditions such as load perturbation, non-linear load, voltage sag, unsymmetrical line fault at input AC mains. The transient condition is a momentary burst of energy, results excessive voltage and current in the electrical system. The transient conditions are classified by sudden change in normal operating conditions [Sood, 2004]. The definitions of the different transients are explained as: Load perturbation conditions: Sudden decrease between 0.1 to 0.9 pu in rated load for one half cycle to one minute or sudden increase of load between 1.1 to 1.8pu for one half cycle to one minute is considered as load perturbation condition. Voltage sag: A voltage sag happens when RMS voltage decreases between 10 to 90 % of nominal voltage for one half cycle to one minute. Non-linear load condition: A load is considered non-linear if impedance changes with the applied voltage. The changing impedance means that the current drawn by the load will not be sinusoidal even when it is connected to a sinusoidal voltage. 60

14 Unsymmetrical fault: Those fault in the power system which gives unsymmetrical fault currents (unequal fault current in the line with unequal phase displacement) are considered as unsymmetrical fault. The performance of the designed system is demonstrated under load perturbation, voltage sag, non-linear load condition, unsymmetrical fault i.e. tapped load fault for short duration at both point-of-common coupling in VSC based HVDC system. The both configurations i.e.btb and long distance transmission are considered for performance evaluation in VSC based HVDC system. The sets of waveforms i.e. supply voltage (VA) and supply current (IA), DC link voltage (Vdc), load current (IAL) are used to show system performance under various transient conditions. The nomenclatures 1 and 2 are used for PCC1 and PCC2 respectively Performance evaluation of VSC based BTB HVDC system The performance of six pulse AC-DC converter based back-to-back high voltage direct current (HVDC) system are obtained under various transient conditions in MATLAB- Simulink environment. The system data are presented in the Table 3.2. The controller gains are calculated using Zeigler-Nichols approach under load perturbation, voltage sag, nonlinear load and tapped load fault condition as given in Table 3.3. Supply Voltage Table 3.2 Specification of VSC based BTB HVDC system 33kV Frequency 50Hz Transformer Rating 33/2.1kV DC-link Voltage 2.7kV Interfacing Inductor 0.336H DC-link capacitor 1250mF PCC load 100MW, 0.9 PF lagging DC-cable 0 km Switching frequency 1950Hz 61

15 Table 3.3 Controller gains obtained by Ziegler-Nichols approach for VSC based BTB HVDC system Voltage controller gain Current controller gain Transient conditions kpv kiv kpc kic Load perturbation Voltage sag Non-linear load Tapped load fault Performance evaluation of VSC based BTB HVDC system under load perturbation condition The system is rated for 100MW, suddenly load shedding of 40MW is occurred at t = 1.1sec and recovered again at t = 1.5sec, the overshoot and undershoot are appeared in DClink, however DC-link voltage tracks quickly within 5 cycles as shown Figure 3.13, thereby maintains constant DC power transmission. The power quality results are measured for 5 cycles under transient condition and as well as steady state condition that shows poor current harmonic results are obtained for VSC based HVDC system as shown in Figure Figure 3.13 Simulated waveforms of VSC based BTB HVDC system under load perturbation condition 62

16 Figure 3.14 Current harmonic distortion under load perturbation and rated load condition Performance evaluation of VSC based BTB HVDC under voltage sag condition The voltage sag condition is created for duration of t = 1.1 to 1.5sec at PCC1, thereby reduces supply voltage and current as appeared in Figure 3.15, however the power balance is maintained due to excessive power is stored in DC-link capacitor. The harmonic distortions i.e. THDi with 33.92% and 23.51% are measured under sag and restoration of sag condition as shown in Figure 3.16 Figure 3.15 Simulated waveforms of VSC based BTB HVDC system under voltage sag condition 63

17 Figure 3.16 Current harmonic distortion under sag and restoration of sag condition Performance evaluation of VSC based BTB HVDC under non-linear load condition The performance under nonlinear unbalanced load condition is shown in Figure The non-linear load with R = 2Ω and L=25H is applied for duration of t = 1.3sec to 1.4sec at PCC2. During Transient condition, DC-link voltage is maintained constant due to compensating power provided by VSC, however poor power quality results are obtained as presented in Figure Figure 3.17 Simulated waveforms of VSC based BTB HVDC system under non-linear load condition 64

18 Figure 3.18 Current harmonic distortion under non-linear and normal load condition Performance evaluation of VSC based BTB HVDC system under tapped load fault condition In Figure 3.19, the effectiveness of VSC based BTB HVDC system is evaluated under tapped load fault condition. The tapped load experiences unbalanced load condition i.e. one phase open condition, thereby three phase load is shifted in to two phase, under such unbalanced load condition, huge amount of reactive power is supplied by the VSC. The power quality results i.e. THDi with 37.75% and 29.36% under transient as well as steady state condition respectively as presented in Figure Figure 3.19 Simulated waveforms of VSC based BTB HVDC system under tapped load fault condition 65

19 Figure 3.20 Current harmonic distortion under tapped load fault and clearance of fault condition Performance evaluation of VSC based HVDC system with transmission line The performance of VSC based back-to-back high voltage direct current system are obtained under various transient conditions in MATLAB-Simulink environment. The system data are presented in the Table 3.4. The controller gains are calculated using Zeigler-Nichols approach under load perturbation, voltage sag, non-linear load and tapped load fault condition as presented in Table 3.5. Table 3.4 Specification of VSC based HVDC system with transmission line Supply Voltage 230kV Frequency 50Hz Transformer Rating 230/100kV DC-link Voltage 190kV Interfacing Inductor 6.9mH DC-link capacitor 2200μF PCC load 100MW, 0.9 PF lagging DC-cable 75km Switching frequency 1950Hz 66

20 Table 3.5 Controller gains obtained by Ziegler-Nichols approach for VSC based HVDC system with transmission line Voltage controller gain Current controller gain Transient conditions kpv kiv kpc kic Load perturbation Voltage sag Non-linear load Tapped load fault Performance evaluation of VSC based HVDC system with transmission line under load perturbation condition Figure 3.21 shows performance of the proposed system under load perturbation condition. The rated load is reduced to 60% for duration of t = sec at PCC1. The DC power is balanced but distortion in current are very high, having value 31.21% at input AC main as presented in Figure Figure 3.21 Simulated waveforms of VSC based HVDC system with transmission line under load perturbation condition 67

21 Figure 3.22 Current harmonic distortion under load perturbation and normal load condition Performance evaluation of VSC based HVDC system with transmission line under voltage sag condition The voltage sag is introduced at PCC2 side for duration of t = sec, thereby reduces generated power as shown in Figure Since, VSC has four quadrant power transmission capability, therefore compensating power is provided by the VSC, resulting power balance between AC interconnection. The current harmonic spectra are measured with under voltage sag condition with 23.74% and 21.72% current harmonics distortion is measured after restoration of sag condition as shown in Figure Figure 3.23 Simulated waveforms of VSC based HVDC system with transmission line under voltage sag condition 68

22 Figure 3.24 Current harmonic distortion under sag and restoration of sag condition Performance evaluation of VSC based HVDC with transmission line under non-linear load condition The non-linear load with R = 2Ω and L = 25H is connected for the duration of t = sec at PCC2. The DC-link voltage remains unaffected as shown in Figure The power quality results show poor results as presented in Figure Figure 3.25 Simulated waveforms of VSC based HVDC system with transmission line under non-linear load condition 69

23 Figure 3.26 Current harmonic distortion under non-linear and normal load condition Performance evaluation of VSC based HVDC system with transmission line under tapped load fault condition To demonstrate effectiveness of the proposed system, the tapped load fault under one phase open condition (Phase A) is created at PCC1 at t = 1.2 sec for 20 cycles as shown in Figure Under this unbalanced condition, whole three phase load is shifted to two phase. The large amount of reactive power is compensated by VSC. Figure 3.28 reveals poor results of current harmonic distortion under transient as well as steady state condition. Figure 3.27 Simulated waveforms of VSC based HVDC system with transmission line under tapped load condition 70

24 Figure 3.28 Current harmonic distortion under tapped load fault and clearance of fault condition 3.6 CONCLUSION In this chapter, VSC based HVDC system has been described to emphasize on need of power quality consideration under various transient conditions such as load perturbation, voltage sag, nonlinear load and unsymmetrical fault. A detailed investigation has been carried out in designing and control of VSC based HVDC system for two applications i.e. back-to-back as well as long distance power transmission. The choice of particular configurations depend on the utility requirements. The modelling of the control scheme has been given and simulation model has been developed in MATLAB-Simulink environment. The results of performance simulation of VSC based HVDC system have been presented with their detailed discussion. The VSC- HVDC system is found to have THDi higher than 5% under steady state as well as transient state conditions and do not meet the requirement of power quality standard IEEE 519. The system needs to feed with hybrid system such as multipulse converters for power quality improvement at points-of-common coupling. 71