Unified Power Quality Conditioner (UPQC) for Power Distribution Systems

Transcription

1 Unified Power Quality Conditioner (UPQC) for Power Distribution Systems Shyama P. Das Department of Electrical Engg. IIT Kanpur Introduction Motivation Design, Simulation and Hardware Implementation of Unified Power Quality conditioner (UPQC) (Single phase and Three phase) Optimum UPQC Conclusion and Scope of future research 1

2 Power Quality: Measure of proper utilization of power by customers Electrical Pollutant vs Clean Utility Advent of wide spread use of high power high frequency switching devices Additional System required to maintain quality Deregulation, tariff Power Supply Authority Power Quality Consumer 2

3 PCC Voltage Line Impedance Voltage L O A D Polluting Load " # # $$ %&'! )$ #*# #+, %%- + ( 3

4 Harmonic Polluting Loads Computers Computer controlled machine tools Photo-copying machines Various digital controllers Adjustable speed drives PLCs Uncontrolled or phase controlled rectifiers. Some Important Observations of Power Quality(PQ) Surveys More low r.m.s. voltage sag occur at the PCC Majority of voltage sag are 10-20% More disturbances occur above 70% of nominal line voltage The occurrence of most severe sag events are least frequent. / 4

5 " , % &, %' (09,#!:(9, 4 *(9, IEEE 519 Voltage Limits ;$$6#*# ;$$ )$ 7)- $ &<' &<' +!! +! +! 0 PCC Local Solution Load/ Equipment PCC OTHER LOADS Load/ Equipment Global Solution (Series/Shunt) = 5

6 (a) Providing ride-through capability to the equipment so that they can be protected against certain amount of voltage sag and swell (b) Equipment are provided with an arrangement so that they draw low reactive power and harmonics (c) Disadvantage of this approach is that it cannot take care of existing polluting installations and further it is not always economical to provide the above arrangement for each and every equipment (a) Here independent compensating devices are installed at PCC so that overall PQ improves at PCC. (b) Advantages of this approach are Individual equipment need not be designed according to PQ standards Existing Polluting installations can be taken care of. 6

7 # a)shunt (parallel) Active Filter (STATCOM) b) Series Active Filter (DVR) STATCOM $ $>? *?)$ 7

8 STATCOM! ( 8

9 747". 747" / 9

10 STATCOM Control Strategy 3 > 0 DVR (Dynamic Voltage Restorer) >?, %%?, %$ = 10

11 Reactive Power Transfer V s2 =V L2-2V L V dvr Sin +V dvr 2 In-Phase Compensation 11

12 Phase cum Magnitude Compensation Load harmonic and VAR compensation Voltage sag mitigation and unbalanced voltage correction Fast dynamic response, and steady state accuracy 12

13 Unified Power Quality Conditioner (UPQC)! Utility supply V inj Injection Transformer i s i_load Load Low Pass Filter Inverter- I Inverter- II i c L SLC C dc Synchronous Link Inductor Inverter-I compensates for sag through a tuned filter and voltage transformer Inverter-II (SLCVC) Synchronous Link Converter VAR Compensator provides VAR to the load, isolates load current harmonics, makes input power factor unity SLCVC maintains the charge of the dc link capacitor ( 13

14 Quadrature Compensation UPQC-Q Phasor diagram of UPQC-Q for fundamental power frequency, when θ <Φ. Quadrature Compensation UPQC-Q V inj = 2V inj V s1 m = = mv V s 2 / 2 x(2 x). V s1 Where, x is p.u. sag m = Modulation Index (max MI=1) and transformer ratio 1:1 dc 2 From power balance = Is2 Il 2 cosφ cosθ / 14

15 ,45 #% 32:2 Series VA loading of UPQC-Q 1 VA p.u p.f.=0.25 p.f.=0.5 p.f.=0.6 p.f.=0.7 p.f.=8 p.f.=0.9 p.u. Sag 0,45 #% 32:2 Shunt VA loading of UPQC-Q 1.2 VA p.u p.f.=0.9 p.f.=0.8 p.f.=0.7 p.f.=0.6 p.f.=0.5 p.f.=0.25 p.u. Sag = 15

16 $#,45 #% 32:2 Combined Loading of UPQC-Q VA p.u p.u. Sag. p.f.=0.9 p.f.=0.8 p.f.=0.7 p.f.=0.6 p.f.=0.5 p.f.=

17 Four Modules! " # $ % & " ' " (!"" "! ) # % & V inj V s Peak Detector Ckt. Filter i s N-L Load Vs_peak Gate Drive Gate Drive Hysteresis Control i s SPWM DA * 1 i s DA 0 i s * DA 1 pwm modulating signal ( m DA 3 ) 0 V dc Vs_peak v75 v90 vsec AD0 AD1 AD2 AD3 AD4 PCL-208 [ADC, DAC, Timer, DIO] Computer Fig.3.15 Block diagram of hardware implementation 17

18 Supply current ( i s ) Fig Experimental result of supply current and load current X axis : 5 ms/divy axis: 5 A/div Load current (i L ) Fig Simulation result of supply and load current corresponding to Fig X axis = 5 ms/div Y axis = 5 A/div! Relative Percentage Fig Load current (i_load) spectra (Experimental) Harmonic Number 120 Fig Supply current ( i s ) spectra (Experimental) Relative Percentage Harmonic Spectrum ( 18

19 Fig Experimental results of supply current (i s ) and supply current reference (i s* ) X axis : 5 ms/div Y axis: 10 A/div Fig Simulation results of supply current (i s ) and supply current reference (i s* ) X axis : 5 ms/div Y axis: 10 A/div. Fig Experimental result of v L, v s and vsec Trace-1: Load voltage (v L ) y axis : 50 v/div Trace-2: Supply voltage (v s ) y axis : 50 v/div Trace-3: Series injected voltage (vsec) /38. y axis : 1 v/div x axis : 20ms/div Load voltage Source voltage Injected voltage Fig Simulation result of v L, v s and vsec Trace-1: Load voltage (v L ) y axis : 50v/div Trace-2: Supply voltage(v s ) y axis : 50v/div Trace-3: Series injected voltage ( vsec) /38. y axis : 1v/div / 19

20 120 Relative Percentage THD = 3.6% Harmonic Number Fig Load voltage (v L ) spectra 0 Dc link voltage (vdc) Fig Steady state experimental results of DC link voltage (Vdc), supply ( i s ) and load current ( i L ) X axis : 50ms/div Y axis : vdc 20V/div, i s, i L 5A/div Supply current (i s ) Load current (i_load) Fig Steady state simulation results of DC link voltage (Vdc/1000), supply (i s ) and load current ( i L ) X axis : 50 ms/div Y axis : Vdc.1 V/div, i L = 2 A/div, i s = 10 A/div = 20

21 3-φ AC Source secv i s i_load 3-φ Nonlinear Load i c Low Pass Filter L SLC Vdc Series Compensator SLCVC v dc Vs_peak secv_a v90-a secv_b v90-b secv_c AD0 AD1 AD2 AD3 AD4 AD5 AD6 PCL-208 ADC,DAC, COUNTER TIMER, DIO Computer PCL ch-dac, DIO DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DA 0 DA 1 m1-a m1-b PI-outA PI-outB PI-outC (m2-a) (m2-b) (m2-c) i sa * i sb * secv_a V sa N V sb secv_b i sa secv_c i sb V sc i sc Peak Detector Ckt. Filter 3-φ N-L Load Vs_peak Gate Driver Gate Driver Hysteresis Control i sa i sb i sc 5 khz SPWM i sa * i sb * i sc * m3-( A B C) 21

22 isa Fig. 4.20a Experimental results of supply current and load current of phase-a X axis: 50 ms/div, Y axis: 5 A/div for isa, 2 A /div for i_loada i_loada Fig. 4.20b Simulated results of supply current and load current of phase-a Fig. 4.21a Experimental results of supply current and supply voltage of phase-a X axis: 50 ms/div, Y axis: 5A/div for isa, 20 V/div for vsa Fig. 4.21b Simulated results of supply current and supply voltage of phase-a 22

23 Harmonic order Load Current (A-phase) Supply current ( A-phase) Magnitude % fundamental Magnitude % fundamental 1st A A 100 5th ma ma th ma ma th ma ma th ma ma th ma ma th ma ma rd ma ma th ma ma 0.38 THD 23.28% 2.957% Displacement Factor ! sag Peak of supply voltage (A) Fig. 4.23a Experimental result of peak of supply voltage and load voltage of phase- A X axis: 100 ms/div, Y axis: 50 V/div for v_loada, V/div for Vsa_peak, Load Voltage (a) Fig. 4.23b Simulated result of peak of supply voltage and load voltage of phase-a ( 23

24 Fig. 4.24a Experimental result of peak of supply voltage and supply current of phase-a X axis: 100 ms/div, Y axis: V/div for Vsa_peak, 2 A/div for i_loada Fig. 4.24b Simulated result of peak of supply voltage and supply current phase-a. Fig. 4.25a Experimental result of peak of supply voltage and injected voltage and supply voltage of phase A, X axis: 10 ms/div, Y axis: 10 V/div for secv_a, 50 V/div for vsa, 52.4 V/div for Vsa_peak Fig. 4.25b Simulated result of injected voltage and supply voltage of phase-a / 24

25 Fig. 4.26a Experimental result of peak of supply voltage and injected voltage and supply voltage of phase- B, X axis: 10 ms/div, Y axis: 50 V/div for vsb, 10 V/div for secv_b, 52.4 V/div for Vsa_peak Fig. 4.26b Simulated result of injected voltage and supply voltage of phase-b 0 Conventional -, * % -, $* % 5 #,4 747"#-, $ * %% #!= 25

26 " #%&32:'!,45 #% 32: Series VA loading of UPQC-P VA p.u p.u. Sag p.f.=0.25 p.f.=0.5 p.f.=0.6 p.f.=0.7 p.f.=0.8 p.f.=0.9! 26

27 ,45 #% 32: Shunt VA loading of UPQC-P 1.2 VA p.u p.f.=0.9 p.f.=0.8 p.f.=0.7 p.f.=0.6 p.f.=0.5 p.f.=0.25 p.u. Sag! $#,45 #% 32: Combined Loading of UPQC-P VA p.u p.u. Sag p.f.=0.9 p.f.=0.8 p.f.=0.7 p.f.=0.6 p.f.=0.5 p.f.=0.25! 27

28 5$ 32:2 3 $%* %$%# 3 $%* % - $ * % $% * %%# $%%* %$%# 3 $%* %!!,4$A 6@%, % "$$4%!( 28

29 -, % $A#%+!. DVR Control Strategy!/ 29

30 Source voltages during normal and sag condition Sag end Sag start Simulation Results!0 Load voltages during normal and sag condition Sag end Sag start Simulation (= Results 30

31 Case Study (Optimized UPQC)!"#$ $ %& '!"($)!"(* $ * $ % $,4&32:2'B=+.++C&B(+. = ',4&32:'B=+(++C&B= = ',4&32: #'B=+/++C&B = ' ( 1. UPQC can mitigate voltage sag. 2. Hybrid (combined analog and digital) control implemented, the control scheme is applicable for both single phase and three phase. 3. No additional energy storage device required for sag compensation, long duration sags and under voltages can also be compensated. 4. Dynamic response is fast. ( 31

32 5. UPQC can supply VAR to the load. 6. It isolates the load current harmonics from flowing to the utility. 7. It maintains input unity power factor at all conditions. 8. Optimized UPQC leads to minimum VA loading of the converters. ( $$ " ( 32

33 (! 33