74LVC373A. Description. Pin Assignments NEW PRODUCT. Applications. Features OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 74LVC373A

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1 OTAL TRANSPARENT -TYPE LATH WITH 3-STATE OUTPUTS escription Pin Assignments The provides eight traparent -type latches. While the latch-enable (LE) input is high, the outputs follow the data () inputs. When LE is taken low, the outputs are latched at the logic levels set up at the inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operatio of the latches. Old data can be retained or new data can be entered while the outputs are in the highimpedance state. The device is designed for operation with a power supply range of 1.65V to 3.6V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applicatio using I OFF. The I OFF circuitry disables the output preventing damaging current backflow when the device is powered down. Features Supply Voltage Range from 1.65V to 3.6V Sinks or Sources 24mA at V = 3V MOS Low Power oumption I OFF Supports Partial Power own Operation Inputs or Outputs Accept Up to 5.5V Inputs an Be riven by 3.3V or 5V Allowing for Mixed Voltage Applicatio Schmitt Trigger Action at All Inputs Typical V OLP (uiet Output Ground Bounce) Less Than 0.8V with V = 3.3V and T A = +25 Typical V OHV (uiet Output dynamic VOH) Greater than 2.0V with V = 3.3V and T A = +25 ES Protection Tested per JES 22 Exceeds 200-V Machine Model (A115) Exceeds 2000-V Human Body Model (A114) Exceeds 1000-V harged evice Model (101) Latch-Up Exceeds 250mA per JES 78, lass II All devices are: Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2) Halogen and Antimony Free. Green evice (Note 3) Applicatio General Purpose Logic Bus riving Power own Signal Isolation Wide array of products such as: Ps, Notebooks, Netbooks, Ultrabooks Networking omputer Peripherals, Hard rives, /V ROM TV, V, VR, Set Top Box Notes: 1. No purposely added lead. Fully EU irective 2002/95/E (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See for more information about iodes Incorporated s definitio of Halogen and Antimony free, "Green" and Lead-Free. 3. Halogen and Antimony free "Green products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + l) and <1000ppm antimony compounds. 1 of 10

2 Ordering Information 74 LV 373A xxx -13 Logic evice Function Package Packing 74 : Logic Prefix 373 : Octal Traparent - Type Latch with 3-State Outputs T20 : TSSOP : FN : 13 Tape & Reel Part Number Package ode Package (Note 4 & 5) T20-13 T20 TSSOP V-FN Notes: Package Size 6.4mm X 6.5mm X 1.2mm 0.65 mm lead pitch 2.5mm X 4.5mm X 0.95mm 0.50 mm lead pitch uantity 13 Tape and Reel Part Number Suffix 2500/Tape & Reel /Tape & Reel Pad layout as shown on iodes Inc. suggested pad layout document AP02001, which can be found on our website at 5. V-FN is a JEE recognized naming convention that specifies the package thickness category as V and the number 4525 describes the package as 4.5mm X 2.5mm. Pin escriptio Logic iagram Function Table Pin Number Pin Name escription 1 OE Output Enable 2 1 Latch Output 3 1 ata Input 4 2 ata Input 5 2 Latch Output 6 3 Latch Output 7 3 ata Input 8 4 ata Input 9 4 Latch Output 10 GN Ground 11 LE Latch Enable 12 5 Latch Output 13 5 ata Input 14 6 ata Input 15 6 Latch Output 16 7 Latch Output 17 7 ata Input 18 8 ata Input 19 8 Latch Output 20 Vcc Supply Voltage 1 OE 11 LE INPUTS (Each Latch) OUTPUT OE LE L H H H L H L L L L X 0 H X X Z of 10

3 Absolute Maximum Ratings (Notes 6 & 7) Notes: Symbol escription Rating Unit ES HBM Human Body Model ES Protection 2 kv ES M harged evice Model ES Protection 1 kv ES MM Machine Model ES Protection 200 V V Supply Voltage Range -0.5 to +7.0 V V I Input Voltage Range -0.5 to +7.0 V I IK Input lamp urrent V I < 0V -20 ma I OK Output lamp urrent V O < 0V -50 ma I O ontinuous Output urrent -0.5V < V O V +0.5V ±50 ma I ontinuous urrent Through V 100 ma I GN ontinuous urrent Through GN -100 ma T J Operating Junction Temperature -40 to +150 T STG Storage Temperature -65 to +150 P TOT Total Power issipation 500 mw 6. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should be within recommend values. 7. Forcing the maximum allowed voltage could cause a condition exceeding the maximum current or conversely forcing the maximum current could cause a condition exceeding the maximum voltage. The ratings of both current and voltage must be maintained within the controlled range. Recommended Operating onditio (Note 8) Symbol Parameter onditio Min Max Unit V Supply Voltage Operating V ata Retention Only 1.5 V V I Input Voltage V V O Output Voltage 0 V V V = 1.65V -4 I OH High-Level Output urrent V = 2.3V -8 V = 2.7V -12 ma V = 3.0V -24 V = 1.65V 4 I OL Low-Level Output urrent V = 2.3V 8 V = 2.7V 12 ma V = 3.0V 24 t/ V Input Traition Rise or Fall Rate 10 /V T A Operating Free-Air Temperature Note: 8. Unused inputs should be held at V or ground. 3 of 10

4 Electrical haracteristics T A = -40 to +85 T A = +85 to +125 Symbol Parameter Test onditio V Min Max Min Max V IH V IL V OH V OL I OFF I I I OZ High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Power own Leakage urrent Input urrent ontrol Pi Z-state urrent Including Input urrent I/O Pi 1.65V to 1.95V V X 0.65 V X V to 2.7V V to 3.6V V to 1.95V V X 0.35 V X V to 2.7V V to 3.6V I OH = -50μA 1.65V to 3.6V V -0.2 V -0.3 I OH = -4mA 1.65V I OH = -8mA 2.3V I OH = -12mA 2.7V V I OH = -24mA 3.0V I OL = 100μA 1.65V to 3.6V I OL = 4mA 1.65V I OL = 8mA 2.3V I OL = 12mA 2.7V I OL = 24mA 3.0V V I or V O = 0 or 5.5V 0V ±10 20 μa V I = GN or 5.5V 0 to 3.6V ±5 ±20 μa V I = GN or 5.5V V O = 0 to 5.5V 3.6V ±5 ±20 µa I Supply urrent V I = GN or V, I O = 0 3.6V μa I i Additional Supply urrent Input apacitance One input at Vcc-0.6V Io = 0A 2.7V to 3.6V μa ontrol Pi V I = GN or 4.0 typical 4.0 typical 0V to 3.6V I/O Pi V 5.5 typical 5.5 typical Unit V V V V pf 4 of 10

5 Switching haracteristics Symbol Parameter Test T A = to to +125 V onditio cc Min Typ. Max Min Max Min Max Unit 1.8V ± 0.15V t W Pulse Width 2.5V ± 0.3V LE 2.7V V ± V ± 0.15V t SU Set-up Time N to 2.5V ± 0.3V LE 2.7V V ± V ± 0.15V t H Hold Time 2.5V ± 0.3V N to LE 2.7V V ± V ± 0.15V Propagation elay 2.5V ± 0.3V t P N to N 2.7V V ± V ± 0.15V t P Propagation elay 2.5V ± 0.3V LE to N 2.7V V ± V ± 0.15V t EN Enable Time 2.5V ± 0.3V OE to N 2.7V V ± V ± 0.15V t IS isable Time 2.5V ± 0.3V OE to N 2.7V V ± V ± 0.15V t IS isable Time 2.5V ± 0.3V OE to N 2.7V V ± 0.3V tsk(0) Output Skew Time 3.3V ± 0.3V Operating haracteristics T A = +25 Symbol Parameter Test onditio V Typ Unit pd Power dissipation capacitance per gate F = 10MHz Outputs Enabled 1.8V ± 0.15V V ± 0.3V V ± 0.3V 10.6 pf Package haracteristics Symbol Parameter Package Test onditio Min Typ Max Unit θ JA Thermal Resistance Junction-to-Ambient TSSOP-20 (Note 9) 74 /W θ J Thermal Resistance Junction-to-ase TSSOP-20 (Note 9) 15 /W θ JA Thermal Resistance Junction-to-Ambient V-FN (Note 9) 67 /W θ J Thermal Resistance Junction-to-ase V-FN (Note 9) 20 /W Note: 9. Test conditio for TSSOP-20 and V-FN : evices mounted on 4 layer FR-4 substrate P board, 2oz copper, with minimum recommended pad layout per JES of 10

6 Parameter Measurement Information TEST t PLH /t PHL t PLZ /t PZL t PHZ /t PZH S1 Open Vload GN V V I Inputs V M V LOA L R L V t r /t f 1.8V±0.15V V 2 V /2 2 x V 30pF 1KΩ 0.15V 2.5V±0.2V V 2 V /2 2 x V 30pF 500Ω 0.15V 2.7V 2.7V V 6V 50pF 500Ω 0.3V 3.3V±0.3V 2.7V V 6V 50pF 500Ω 0.3V Voltage Waveform Pulse uration Voltage Waveform Enable and isable Times Low and High Level Enabling Voltage Waveform Propagation elay Times Inverting and Non Inverting Outputs Notes: A. Includes test lead and test apparatus capacitance. B. All pulses are supplied at pulse repetition rate 10 MHz.. Inputs are measured separately one traition per measurement.. t PLZ and t PHZ are the same as t dis. E. t PZL and t PZH are the same as t EN0 F. t PLH and t PHL are the same as t P. Load ircuit and Voltage Waveforms 6 of 10

7 Marking Information (1) TSSOP20 (2) FN-20 (V-FN ) Part Number T20 Package TSSOP-20 (Top View ) Logo Part Number terminal 1 index area YY WW X X YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X X : Internal odes Part Number 20 Package V-FN of 10

8 (A3SeatingPlanePi#1I)E2b(20x)eE2L(20xZ(4x)Z1(4x)) Package Outline imeio (All imeio in mm) Please see AP02002 at for the latest version. (1) TSSOP-20 PIN 1 I MARK e E1 A2 E A 0.25 Gauge Plane θ1 L L1 Aθ3Aθ2 Seating Plane ETAIL TSSOP-20 im Min Max Typ A A A b c E E e 0.65 BS L L1 1.0 REF θ θ θ All imeio in mm n1v-fn im Min Max Typ A A A b E E e 0.50BS L Z Z All imeio in mm b A1 (2) FN-20 (V-FN ) 8 of 10

9 X4X3X1X2Y3Y1Y2YX Suggested Pad Layout Please see AP02001 at for the latest version. (1) TSSOP-20 X (20x) Y (20x) X1 Y1 Y2 imeio Value (in mm) X X Y Y Y (2) FN-20 (V-FN ) imeio Value (in mm) X X X X X Y Y Y Y of 10

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