Design Of Synchronous Up-Down Counter Using CMOS 90nm Technology

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1 Design Of Synchronous Up-Down Counter Using CMOS 90nm Technology G.Madhurya 1 T. Vijay Kumar 2 madhuryagajula@gmail.com1 vijaykumar4792@gmail.com2 1 PG Scholar, Dept of ECE, Dr. K. V. SUBBA REDDY INSTITUTE OF TECHNOLOGY, DUPADU, KALLUR, KURNOOL, ANDHRA PRADESH 2 Associate Professor, Dept of ECE, Dr. K. V. SUBBA REDDY INSTITUTE OF TECHNOLOGY, DUPADU, KALLUR, KURNOOL, ANDHRA PRADESH. Abstract: A counter is a digital sequential logic device that will go through a certain predefined states (for example counting up or down) based on the application of the input pulses. They are utilized in almost all computers and digital electronics systems [1]. The synchronous counter is one in which each flip-flop is clocked by the same clock source, thus eliminating the cumulative delay found in asynchronous counters. A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flipflops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time. The VLSI placement problem is to place the objects into a fixed die such that there are no overlaps among the objects and some cost metric such as wire length and routability is optimized. For this purpose we use new type of placement method called Noise aware placement. Using the above mentioned method we have designed synchronous up/down counter with the help of CMOS 90 nm technology. In this thesis the HPWL, TWL and are calculated for existing method and NA method. The values of these are implemented using DSCH & Micro-wind software tool. These parameters in NA method are shown better results than Existing method. I. INTRODUCTION Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. The first semiconductor chips held two transistors each. Subsequent advances added more transistors, and as a consequence, more individual functions were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. A digital circuit is often constructed from small electronic circuits called logic gates that can be used to create combinational logic. Each logic gate represents a function of boolean logic. A logic gate is an arrangement of electrically controlled switches, better known as transistors. Counting is a fundamental function of digital circuits. A digital counter consists of a collection of flip-flops that change state (set or reset) in a prescribed sequence. The primary function of a counter is to produce a specified output pattern sequence. A counter can play a vital role in several circuits ranging from a simple display to complex microcontroller circuits. Some of the apparent applications of a counter are: frequency divider in phase-locked loops, microcontrollers, digital memories and in digital clock and timing circuits. Counter is one of the simplest but essential building blocks in very large scale integration design. Counters are usually classified into synchronous counters, such as up counter, down counter,ring counters and twisted counters, and asynchronous counters, such as ripple counter, up counter down counter and Mod N counter. In synchronous counter a common clock is used which is connected to each flip flop while in asynchronous counter clock is connected to first flip-flop only and the output of one flip-flop derive the input of the next one. Synchronous counter

2 has many advantages over asynchronous counter. Asynchronous counter not useful at very high frequencies, especially for counter with large number of bits. Another problem caused by propagation delays in asynchronous counter occurs when we try to electronically detect (decode) the counter s output states. II. CONVENTIONAL SYSTEM SYNCHRONOUS COUNTERS This type of counters has each flip-flop clocked by the same clock source, thus eliminating the cumulative delay found in asynchronous counters. A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time: Let s examine the four-bit binary counting sequence again, and see if there are any other patterns that predict the toggling of a bit. Asynchronous counter circuit design is based on the fact that each bit toggle happens at the same time that the preceding bit toggles from a high to a low (from 1 to 0). Since we cannot clock the toggling of a bit based on the toggling of a previous bit in a synchronous counter circuit (to do so would create a ripple effect) we must find some other pattern in the counting sequence that can be used to trigger a bit toggle: Examining the four-bit binary count sequence, another predictive pattern can be seen. Notice that just before a bit toggles, all preceding bits are high: respective x and y coordinates of the center of the element v i, and a i be the area of the element v i. The VLSI circuit may contain some preplaced components, which have constant x and y coordinates and these are not changeable. The best locations for changing elements should be determined, therefore, the total wire length is reduced and no overlaps are developed between the elements. The placement region is divided into uniform non-overlapping bin (small region) sizes [1] [2] to equally distribute the elements. Then, the difficulty of global placement is considered as a forced minimization problem, which is given by equation (1.1). min W(x, y) Such that D b (x, y) M b, for each bin b, (1.1) where W(x,y) is the wire length of the circuit and D b (x, y) is the potential that is the total area of movable blocks in bin b, and M b is the maximum area of movable blocks in bin b. M b is computed by M b = t density (w b h b P b ), where t density is a required target density value for each bin, w b (h b ) is the width (height) of bin b and P b is the base potential that equals the preplaced block area in bin b. The wire length W(x,y) of the circuit is defined as the total half-perimeter wire length (HPWL) [112] and which is given by equation (1.2). W(x, y) ( x x +,, y yjǀ (1.2) where W(x,y) is the wire length in x and y directions. Similarly, the total wire length (TWL) for all the circuit in the bin is defined as follows: TWL = Half Perimeter Wire length (1 + density of components) This total wire length is also called as Density Half Perimeter wire length (DHPWL). The log-sum-exponential wire length model is also used [2] in this approach to calculate the wire length, which is given by equation (1.3). Fig1. Block diagram of synchronous counter. ANALYTICAL MODEL OF VLSI PLACEMENT The VLSI circuit Placement [10] [59] may be modeled by hyper graph H = (V, E). Let vertices V = {v 1, v 2,..., v n } represent elements and hyper edges E = {e 1, e 2,...,e m } represent wires. Let x i and y i be the γ (log e ( ) + log e ( ) + log e ( ) + log e ( )) (1.3) when γ 0, log-sum-exponential wire length gives a good estimation to the half perimeter wire length [2]. A quadratic technique [3] [17] is used for Equation (1.1), indicates that a sequence of free minimization problems

3 of the form as given by equation (1.4). min W(x, y) + λ (D (x, y) M ) (1.4) Instead of this equation, the λ is initialized based on the strength of wire length and gradient of number of components are given by equation (1.5). λ = (,) (,) (1.5) In this equation λ is overlap weight and this value will increase by two times for each iteration, w(x,y) is the wire length and D(x, y) density gradient. The existing core techniques in VLSI Placement are divided into following main approaches: Global Placement, Legalization, and Detailed Placement. The global placement equally distributes the blocks and arranges better location for each block to diminish wire length. Then all overlaps are removed between the blocks by legalization and make standard cells to locate into rows and further improve exact location for the standard cells by the detailed Placement. allotted to through the point of corner. The interconnection blockage at point of edge e is denoted as W e and is defined as the ratio of interconnecting demand on the edge to interconnecting sources W e = d e /R e (3.1) Where d e is interconnecting request on the edge e and R e is source of interconnection. Estimation of Noise In order to remove the crosstalk noise in the VLSI circuits, the noise must be approximate for the given resistor-capacitor circuit. To do this, there are so many techniques are presented to approximate the receiver noise. One of them is taken from the calculation of the magnitude noise and the noise duration of circuit and these are approximated from below equations: v = 1 exp ( ) (3.1) ) t = t + t l ( (3.2) ( ) Fig.2: (a) The Smoothing process of VLSI Placement (b) The base potential after Gaussian smoothing. (c) The base potential after level III. smoothing PROPOSED SYSTEM. Analysis of Routing Congestion The routing area of the chip is divided by m x n interconnection points with the help of global router. It allots each wire to connect on these points based on the Steiner tree. The result of this global router provides as a matrix representation of interconnecting source and interconnecting request at each edge of point. An interconnection source is nothing but the number of offered interconnecting tracks on a point of edge, and the interconnecting request is known as number of interconnecting tracks needed to interconnect wires Where t is the Elmore delay [85] of the coupling capacitance with closure source net, t is conversion time of the attacker wire, and t is the Elmore delay of the affected wire. Sometimes both noise magnitude and noise duration are collectively used to determine entire noise when circuit of receiver is fail. The noise magnitude and noise duration product (AW) in the receiver of the circuit can be written as: AW = (R + R )C (3.3) Where R is the resistance of the driver circuit, R s is the wire resistance of the source and C is the coupling capacitance in the circuit. This equation contains two specific factors to find out cross talk noise. The primary factor (R d + R s ) is complete resistance from the driver to the coupling position. It holds the amount of power a driver contains to get from maximum noise value to minimum constant value. The secondary factor C x is coupling capacitance of the circuit. MAPPPING OF CROSSTALK NOISE USING COUPLING CAPACITANCE Usually the crosstalk noise is interrelated with

4 coupling capacitance and which in turn linked with interconnection blockage. Naturally, VLSI circuit placement with minimum jamming shall have least value of noise. Hence, in the present placement, reduction of blockage on the hotspots may get better noise boundary in a VLSI Placement. The most packed regions are not those regions with the help of Amplitude-Width equation. Though coupling capacitance in hotspots is larger than other locations, the noise at each sink may depend on the wire and resistances of the driver circuit. The estimation of the exact value of coupling capacitance is not possible by using only wire at this stage, since numerous solutions are available for local routing problem. But it is necessary to approximate the standard value of coupling capacitance to all the nets in a global interconnecting point. Let us think that there is a relation between global interconnection blockage and the coupling capacitance, which is obtained from curve fitting. This concept may be used in any type of interconnection and VLSI design. Introduced a probabilistic model for all types of wire assignments in a point. Even though these models are giving adequate approximation of coupling capacitance from interconnection blockage and may not suitable to adjust in various global routers and CMOS technology. Due to this reason, the global router must be used to generate global blockage map W(x,y) at the initial stage. After the global router generates the blockage map, the local router should be operating and then extraction process will be used to generate coupling capacitance for every net section. The coupling capacitance on each segment of wire to global routing point may be calculated as given below: C (i, j) = C (i, j) N (i, j). (3.4) Where C n (i,j) is overall coupling capacitance among wire sections i and j, N w (i,j) is number of interconnecting points when i and j are overlapped, C g (i,j) is coupling capacitance dispersed to each one of those interconnecting points. Adding the coupling capacitance from all wires passing through the point, then the total coupling capacitance on each point can be calculated and which can be obtained as follows: C (x, y) = C (i, j), (,) (3.5) C t (x, y) is total coupling capacitance at point (x, y). E(x,y) is group or set of coupling points that cover point (x,y) and C g (i,j) is group coupling capacitance. The standard wire capacitance of a point C s (x,y) can be calculated with help of following equation: C (x, y) = C (x, y) N (x, y) (3.6) Where N g (x,y) is the total number of wire covering at point(x,y). By making use of blockage map W(x, y) and the standard wire coupling capacitance map C s (x, y), the relationship between blocking and coupling capacitance may be generated. With help of curve fitting, the following equation is used to approximate this relationship: C (w) = α1 e (3.7) Where C s (w) is the standard coupling capacitance for wires in a grid with blockage W, α and β are positive constants for each technology. From above equation, standard coupling capacitance for all wires on each point (x, y), when there is a blockage map is shown in below: C (x, y) = c W(x, y) (3.8) Initially, it is necessary to find out the areas of enhancement in blockage to create on noise, i.e., the noise amplitude-width product (AW) of all sinks. Since noise magnitude (amplitude) and noise duration (width) product depends on coupling capacitance, driver resistance and wire resistance, but coupling capacitance map only will give some data required for noise approximation. The coupling capacitance does not increase when blockage is high, so only using coupling capacitance to guide placement will not be appropriate. Therefore, a new method of noise map is used to achieve the overall noise data to help proper VLSI circuit placement. The noise of each point N(x,y) is defined as the total crosstalk within the point to the amplitudewidth of all nets. The N(x; y) may be calculated from the formula of noise amplitude-width product (AW) of wire i in a point. So that from Equation (3.3) AW(i) = R (i) + R (i)c (i) (3.9) Where R d (i) is the output resistance of the driver circuit of net i, R s (i) is wire resistance, C x (i) is the approximate coupling capacitance of net i, R s can be obtained as the product of unit wire resistance and the distance between the source and the current point as r w.. L. Using above equation, if net i is in point (x, y), the noise N(x, y) of

5 point (x, y) can be computed as follows: N(x, y) = (,) AW(i) (3.10) The above equation indicates that the noise of point (x, y) is equal to the sum of product of noise amplitudewidth product from all nets passing thorough the point (x, y). NOISE REDUCTION USING NAIP The incremental migration placement method should used subsequently to find out the noise areas by using noise map and which reduces the blockage of those areas for reduction of the coupling capacitance and noise. The condition for this is that the existing placement must not disturb too much to modify the timing characteristics. So, a two-step incremental placement improvement method is implemented to reduce the noise while protecting the global placement order. The primary step is to inflate the cells in the noise regions, which is similar to the placement density control methods. The main difference of these two methods is that the distributing the cells after the incremental placement process instead of distributing cells during the global placement. This is useful to maintain the relative order of placement. This step is called noise aware cell inflation method. The secondary step is used in a local refinement concept to improve the local jamming. This concept further improves the jamming in the noise region and this step is called local refinement. These two steps are described as follows. The blockage can be decreased by applying the whitespace in the blocked regions. This technique is also used for noise improvement as well. To utilize this concept properly, one can either add an extra cells into those regions or inflate cells in those regions. In general, most of the placement engines regularly divide the chip area into smaller bins in the form of bisect or quadrisect. This type of each bisection or quadricsection is referred as a cut. After that, the whitespace is applied between cuts and then it incrementally add whitespace to the existing placement, then rerun placement starting from a late cut to hotspots in order to remove overlaps. This method may help to protect the placement immovability in an existing placement and obtained exact assessment of wiring blockage and noise. The application of whitespace is started from existing placement and the cell inflation is used instead of an extra cell insertion to add whitespace into blockage areas. So, cells must be inflated based on the noise map and pin density. The total whitespace inserted into a bin is proportional to the noise of this bin over the average noise. A(x, y) (,) 1 A(x, y), if N(x, y) > N 0, if N(x, y) N (3.11) Where A(x,y) is the total cell area in bin (x,y), A(x, y) is the total cell inflation area in bin (x,y), and N avg i s the average noise across the chip. If the noise value is equal to or less than the average noise, no cell inflation is occurs. Within a bin, inflation of each cell is counted depends on its pin density. The pin density d(i) of a cell i is defined as the ratio of pin numbers k(i) to the cell area a(i) and which is shown in below equation: d(i) = k(i) a(i) (3.12) Then the inflation area α(i) for each cell i can be computed by the following equation: a(i) = d(i) k (x,y) d(k) A(x, y) (3.13) After the cell inflation, a new placement is started from N i cut. This placement will follow a mixed quadratic placement and partition flow. This placement step is necessary in an overlap removal procedure in order to remove the overlaps caused by inflated cells. The advantage of this method is that it can produce a legal placement while minimizing total wire length. It should be noted that by starting from a late cut, the global relative order of cells is kept unchanged as well. Conventional method. IV. Results Schematic of up-down counter

6 Layout of synchronous up-down Layout of synchronous updown Layout of synchronous updown counter of U/D counter Proposed System.(NA method). Synchronous U/D counter Timing diagram of synchronous U/D counter of synchronous U/D counter Comparision of HPWL,TWL and in NA method with Existing method. S.N O PARAMET ERS EXISTI NG METH OD NOISE AWAR E METH OD IMPROVE MENT 1 No.of cells No.of nets HPWL(µm ) 4 TWL(µm) (mw)

7 V.CONCLUSION We propose an ADDL design methodology for mitigation of DPA attacks on secure integrated chips. To consider the tradeoff in performance and power consumption, we designed and simulated two universal cells. The first design is a PADDL, which is optimized for very high operating frequencies. This design improves upon previously presented benchmarks by 76.41% for average power due to a reduced reliance of evaluation and discharge networks. The PADDL cell also improved upon the differential power of a conventional NAND gate by a factor of 112. The second design, BADDL, uses body biasing to improve the switching time and differential power. Our circuit improves the upon energy imbalance over previous work by an average of 76percent, which makes our circuit an effective mitigant of DPA attacks. The most significant tradeoff is operating frequency. The initial tradeoff in area is offset by using the reversible property of the dual-rail adiabatic circuit to allow for design reuse for both encryption and decryption, which is not physically possible in all the previous benchmarks. REFERENCES [1] N. O. Attoh-Okine and L. D. Shen, Security issues of emerging smart cards fare collection application in mass transit, in Proc. Veh. Navigat. Inf. Syst. Conf., Jul./Aug. 1995, pp [2] D. Agrawal, B. Archambeault, J. R. Rao, and P. Rohatgi, The EM side Channel(s), in Cryptographic Hardware and Embedded Systems. London, U.K.: Springer-Verlag, 2003, pp [3] P. C. Kocher, Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems, in Advances in Cryptology. London, U.K.: Springer- Verlag, Aug. 1996, pp [4] C. Clavier, J.-S. Coron, and N. Dabbous, Differential power analysis in the presence of hardware countermeasures, in Cryptographic Hardware and Embedded Systems. London, U.K.: Springer-Verlag, Aug. 2000, pp [5] P. Kocher, Differential power analysis, Advances in Cryptology (Lecture Notes in Computer Science), vol Berlin, Germany: Springer-Verlag, 1999, pp [6] L. N. Ramakrishnan, M. Chakkaravarthy, A. S. Manchanda, M. Borowczak, and R. Vemuri, SDMLp: On the use of complementary pass transistor logic for design of DPA resistant circuits, in Proc. IEEE Int. Symp. Hardw.-Oriented Security Trust (HOST), Jun. 2012, pp [7] C. H. Bennett, Logical reversibility of computation, IBM J. Res. Develop., vol. 17, no. 6, pp , [8] T. Toffoli, Reversible computing, Lab. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, USA, Tech. Rep. TM-151, [9] E. Fredkin and T. Toffoli, Conservative Logic, Int. J. Theoretical Phys., vol. 21, no. 3, pp , [10] T. Hisakado, H. Iketo, and K. Okumura, Logically reversible arithmetic circuit using passtransistor, in Proc. ISCAS, vol. 2. May 2004, pp [11] N. Pramstaller, F. K. Gurkaynak, S. Haene, H. Kaeslin, N. Felber, and W. Fichtner, Towards an AES crypto-chip resistant to differential power analysis, in Proc. ESSCIRC, Sep. 2004, pp [12] Internation Standard Organization, document ISO- IEC [13] K. Tiri, M. Akmal, and I. Verbauwhede, A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards, in Proc. ESSCIRC, Sep. 2002, pp [14] J. Daemen and V. Rijmen, Resistance against implementation attacks: A comparative study of the

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