Surface micromachined arch-shape on-chip 3-D solenoid inductors for high-frequency applications

Transcription

1 Surface micromachined arch-shape on-chip 3-D solenoid inductors for high-frequency applications Nimit Chomnawang University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science 2601 North Floyd Road Richardson, Texas and Louisiana State University Department of Electrical Engineering Baton Rouge, Louisiana and Suranaree University of Technology School of Electrical Engineering 111 University Avenue Muang District Nakon Rat Chasima Thailand Jeong-Bong Lee University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science 2601 North Floyd Road Richardson, Texas and Louisiana State University Department of Electrical Engineering Baton Rouge, Louisiana Abstract. We present the design, fabrication, and characterization of surface micromachined on-chip 3-D air-core arch-shape solenoid microinductors. Combinations of unique surface micromachining fabrication process techniques, such as deformation of polymeric sacrifical molds and conformal electrodeposition of photoresist molds on nonplanar sacrificial polymer mounds, are utilized. An air gap inserted between the inductor s body and the substrate is used to reduce the degradations of high-frequency inductor performances. Fabricated inductors are characterized and modeled at high frequencies from S-parameter measurements. ABCD parameters, derived from measured S parameters, are translated into a simplified physical model. The resulting 2-, 3-, and 5-turn arch-shape suspended air-core solenoid inductors have inductances between 0.62 to 0.79 nh, peak quality (Q) factors between to 17 at peak-q frequencies between 4.7 to 7.0 GHz, and self-resonant frequencies between 47.6 to 88.6 GHz Society of Photo-Optical Instrumentation Engineers. [DOI: / ] Subject terms: inductor; electroplating; on-chip; solenoid; deformation; conformal coating; sacrificial layer. Paper received Oct. 1, 2002; accepted for publication Apr. 22, Wendell Alan Davis University of Texas at Arlington Department of Electrical Engineering Arlington, Texas Introduction Demands for wireless communication products such as cellular phones, pagers, wireless computing, data links, and global positioning systems GPS are ever escalating. Operating multiple transmitters and receivers that are close to each other requires highly frequency-selective transmission, high dynamic range reception, and exceptional filtering at both transmitter and receiver ends to ensure noninterference with each other. Antijam operations require highly selective filters. A high quality factor Q factor oscillation circuit, which can create a very pure sinusoid, is therefore essential in wireless communication transceivers applications. Currently only hybrid tunable LC tank circuits based on off-chip discrete inductors and solid-state tunable capacitors have sufficient performance for meeting this requirement. If the tunable LC tanks can be monolithically integrated with the same or better performance as hybrid LC tanks, it is possible to lower the total system cost, shrink the overall size, decrease the packaging complexity, and give more flexibility in the wireless communication transceivers system design. There have been many investigations on realizing on-chip spiral inductors and solenoid inductors. 1 7 As a part of such an effort, we describe the development of an on-chip 3-D air-core solenoid microinductor utilizing unique combinations of surface micromachining process techniques. 2 Design One of the most important figures of merit of the inductor is its quality Q factor. To improve the Q factor of a solenoid inductor, a low resistivity of the conductor and a high resistivity of the substrate are desirable. One of the major sources contributing to high resistance in a microfabricated conductor is contact resistance that occurs at the interface of two metallic layers. As a result, resistance of a conductor line increases as the number of contact points in the conduction path increases. Conventional micromachined sole- JM 3 2(4) (October 2003) /2003/$ Society of Photo-Optical Instrumentation Engineers 275

2 Fig. 1 3-D on-chip air-core solenoid inductors: (a) conventional 3-D inductor design, (b) nonsuspended arch-shape solenoid inductor, and (c) suspended archshape solenoid inductor. noid inductors have four contact points per turn Fig. 1 a. In this work, a solenoid inductor that has flat bottom conductors and arch-shape top conductors is designed Fig. 1 b. This design has only two contact points per turn. By choosing low-resistivity material such as copper as a conductor, the series resistance can be decreased. A lowresistivity substrate is another factor that significantly limits the Q factor of an inductor. Using high-resistivity material as a substrate, removing the substrate bulk beneath the inductor, or suspending the inductor above the substrate with surface micromachining reduces this problem. In this work, a surface micromachining technique is utilized to raise the inductor s body above the substrate with metallic spacers at both ends Fig. 1 c to reduce substrate losses. Materials inside an inductor core can also degrade inductor performance. Lee et al. 7 filled an air-core solenoid inductor with a polymer and found that self-resonant frequency decreased by approximately 7%. A lossless air core is therefore the best core material for high-frequency applications. The Sonnet EM Sonnet Software electromagnetic simulation tool has been used to simulate suspended solenoid inductors with air-gap heights varying from zero to 400 m to find a relationship between the height of the air gap and the high-frequency characteristics of inductors. Due to limitations of software, inductors are simulated with conventional flat conductors instead of a true 3-D arch shape for the top conductors Fig. 2. The simulated Q factors of a 2-turn inductor with various air-gap heights are shown in Fig. 3, and Table 1 shows the model parameters given by Sonnet EM simulations. The air suspension improves the Q factor by approximately 18%. However, increasing the air-gap height from 30 up to 400 m does not improve Q factors or the self-resonant frequency significantly. The inductance value obtained from Sonnet EM simulation for the 2-turn inductor is approximately 0.28 nh. It includes self-inductances of extra straight wires, such as the substrate spacers, suspending beams, and via pads. The values of these extra self-inductances are given by 8 : 2l L Straight wire 0.002l ln w t w t 3l, 1 where l, w, and t represent the length, width, and thickness of the wire, respectively. The total extra self-inductance of the straight wires is nh. Subtracting this extra selfinductance from the values obtained from the Sonnet EM simulation gives corrected inductance of nh. 3 Fabrication Based on simulation results, 2-, 3-, and 5-turn solenoid inductors with air-gap suspension of 30 m are selected for the fabrication. To realize arch-shape 3-D solenoid inductors, a unique combination of specific surface micromachining processes are utilized. Such surface micromachin- Fig. 2 Suspended solenoid inductor used in Sonnet EM simulation. Fig. 3 Sonnet EM simulated Q factors of a 2-turn copper inductor with various air-gap heights. 276 J. Microlith., Microfab., Microsyst., Vol. 2 No. 4, October 2003

3 Table 1 Model parameters of 2-turn solenoid inductors simulated by Sonnet EM. Air gap Peak Q Peak-Q frequency (GHz) L S (nh) R S (Ω) C P (ff) Selfresonant frequency (GHz) None m m m m ing processes include deformation of the photoresist mesa by thermal reflow to create a semicylindrical sacrificial photoresist core and conformal deposition of photoresist on a nonplanar semicylindrical surface for the fabrication of top conductors. Such micromachining processes are described in detail elsewhere. 9,10 A brief fabrication sequence is shown in Fig. 4. The fabrication starts with the deposition of a plating base layer on an oxidized silicon wafer or a glass substrate. A layer of 30- m-thick SU-8 MicroChem, Incorporated is spin coated on the substrate and the sample is soft baked, exposed by UV light with a dose of 236 mj/cm 2 to create spacers for air suspension. It is postexposure baked, then developed in the Nano SU-8 developer MicroChem, Incorporated. Invisible SU-8 residues are removed by etching in 100% O 2 plasma reactive ion etch RIE with a gas pressure of 100 mtorr and incident rf power of 100 W. The spacer molds are filled to the top by copper electroplating Fig. 4 a. The next layer of plating base is coated, a layer of 30- m-thick SU-8 is spin coated and patterned on top of the copper spacers to be used as an electroplating mold for the bottom conductors. This mold is then cleaned in O 2 Fig. 4 Fabrication sequence of a 3-D suspended air-core archshape solenoid on-chip inductor. plasma RIE and it is filled to the top by copper electroplating Fig. 4 b. Next, 40- m-thick SJR-5740 photoresist Shipley, Incorporated layer is spin coated and patterned to create a rectangular photoresist mesa structure Fig. 4 c. This photoresist mesa is thermally reflowed to obtain an arch-shape cross-sectional profile sacrificial photoresist core. The sacrificial photoresist core is coated with a plating base and a 15- m-thick Eagle-2100 ED photoresist Fig. 5 SEM photomicrographs: (a) cross sectional profile of sacrificial photoresist core before reflow, (b) after reflow, (c) top-view of 5-turn inductor before the removal of sacrificial photoresist core, and (d) completed 5-turn inductor (in this SEM, a nickel-electroplated inductor without any spacer is shown). J. Microlith., Microfab., Microsyst., Vol. 2 No. 4, October

4 Fig. 6 Measured S parameters of a 5-turn arch-shape solenoid inductor: (a) DUT, (b) PAD, and (c) parasitic de-embedded. Shipley, Incorporated layer is conformally electroplated on the sacrificial photoresist core Fig. 4 d. This conformally deposited photoresist layer is then patterned to obtain a photoresist mold for the formation of the arch-shape top conductors. This photoresist mold is cleaned by O 2 plasma RIE and filled to the top by copper electroplating Fig. 4 e. Finally, all sacrificial photoresist layers are etched away by O 2 plasma RIE with 10% CF 4, and all plating bases are removed by wet etching Fig. 4 f. Figure 5 shows a series of scanning electron microscope SEM photomicrographs that show a 5-turn inductor under fabrication and after the completion of the fabrication. The width of the core is 135 m, the size of the via is 50 m, the linewidth of the bottom conductor is 25 m, and the height of the core at the center is approximately 40 m. Since a contact printing is used, the linewidth of the top conductor varies from 25 m at the bottom edge of the sacrificial polymeric core to 30 m at the top of the sacrificial polymeric core due to diffraction. 4 Characterization High-frequency measurements are carried out to characterize fabricated 2-, 3-, and 5-turn arch-shape solenoid inductors. Probe pads and a ground plane with an inductor device under test DUT, and probe pads and a ground plane without an inductor PAD are measured with an Agilent 8510C automatic vector network analyzer from 500 MHz to 26 GHz using a pair of ground-signal-ground G-S-G type on-wafer microprobes. Before measurements, the equipment is calibrated with a standard impedance substrate by an open-short-load-through method. The parasitic effect of the probe pads and the ground plane is de-embedded from the measured data by converting S parameters of the DUT and the PAD into Y parameters and subtracting Y parameters of the PAD from those of the DUT. Figure 6 shows Smith charts of S parameters of the DUT, PAD, and de-embedded DUT for a 5-turn inductor. From the Smith charts, we note that the trace of S 11 is almost identical to S 22, and S 21 is almost identical to S 12. This implies a good symmetry between ports 1 and 2. In the Smith chart for S parameters of the PAD, the reflection coefficients S 11 and S 22 are in the capacitive region negative reactance. Therefore, the dominant parasitic effect of the probe pads and the ground plane is due to their stray capacitance to the substrate. In addition, the curly tails at high-frequency regions of S 11 and S 22 in the Smith chart for PAD pointed to by an arrow inside a circle in Fig. 6 b suggests that the probe pads and ground plane dummy patterns create parasitic capacitance. Three different modeling techniques are studied to characterize arch-shape on-chip solenoid inductors. They are traditional -network modeling, physical -network modeling, and simplified physical -network modeling. The traditional -network model translates two-port ABCD parameters into a particular circuit representation, with a -network at each frequency. Hence, the model specifies circuits valid at a single frequency. A physical -network model is the second modeling method, and it uses curve fitting. A simplified physical -network model is similar to a traditional model. It translates the two-port ABCD parameters into a particular narrowband circuit representation with a network. In this work, the simplified physical -network modeling result is presented. Other modeling methods and results for arch-shape solenoid inductors are presented in Ref. 10. Figure 7 shows the simplified physical -network model parameters of 2-, 3-, and 5-turn arch-shape solenoid induc- 278 J. Microlith., Microfab., Microsyst., Vol. 2 No. 4, October 2003

5 Fig. 7 Simplified physical -model parameters of arch-shape solenoid inductors: L S and R S. Fig. 9 Substrate loss and self-resonance factors of arch-shape solenoid inductors obtained from a simplified physical model. tors as a function of frequency. In this model, inductance values decrease slowly as the frequency increases. For the shunt capacitance and resistance, the capacitance value decreases exponentially with frequency and become less than 10 ff at frequencies above 5 GHz, while the shunt resistance values are in the range of 350 to1k. Since the series branch of the network does not have self-resonant frequency below 26 GHz, its measured value of selfresonant frequency and stray interturn capacitance C S cannot be determined from the measurement data. The value of C S is then determined by the guess value that gives Q-factor values from the model close to the Q-factor values from the measurements. Inductance values obtained from measurements and simplified physical models for the 2-, 3-, and 5-turn arch-shape solenoid inductors at their peak-q frequencies are 0.616, 0.666, and nh, respectively. Figure 8 shows the measured Q-factor values and the results of simplified physical -network models of 2-, 3-, and 5-turn arch-shape solenoid inductors. The Q factor for this model consists of three parts: L S /R S, the substrate loss factor, and self-resonant factor. If substrate loss and self-resonant factors can be eliminated, Q factors of archshape solenoid inductors can be represented only by Fig. 10 Simplified physical model Q factors of arch-shape solenoid inductors with and without the substrate loss and resonance factors. Fig. 8 Measured and simplified physical -network model Q-factor values of arch-shape solenoid inductors. Fig. 11 Comparison of Q factors for a 2-turn arch-shape solenoid inductor: Sonnet simulation results, measurement results, and the simplified physical model. J. Microlith., Microfab., Microsyst., Vol. 2 No. 4, October

6 Table 2 Parameters of 2-, 3-, and 5-turn arch-shape solenoid inductors with simplified physical models. Number of turns Peak Q f Q max (GHz) L S (nh) R S ( ) C S (ff) C P (ff) R P (k ) f self-resonant (GHz) L S /R S. Figure 9 shows the substrate loss and selfresonance factors as a function of frequency. It can be seen that the substrate loss factor is the major degradation factor of the Q factor, since it drops quickly as frequency increases. Since the series resistance R S values turn negative at frequencies approximately above 18 GHz, the substrate loss factor values also turn negative. Figure 10 shows the Q-factor values with and without the substrate loss and self-resonant factors. Figure 11 shows a comparison of Q factors resulting from the Sonnet simulation, measurements, and the simplified physical model of a 2-turn archshape solenoid inductor. Model and measurement data are in good agreement, while simulation results show a slight deviation from the other two data. Since we did not use a true 3-D simulation version of Sonnet EM, such deviation is expected. Simplified physical model parameters at peak-q frequencies are summarized in Table 2 and depicted in Fig. 12. Fig. 12 Simplified physical models of 2-, 3-, and 5-turn archshape solenoid inductors at their peak-q frequencies: (a) 2-turn inductor at 4.70 GHz, (b) 3-turn inductor at 6.49 GHz, and (c) 5-turn inductor at 7.00 GHz. 5 Conclusions Novel suspended and nonsuspended on-chip 3-D air-core arch-shape solenoid inductors are designed, fabricated, and characterized for high-frequency 1 GHz applications. The Sonnet EM electromagnetic commercial microwave simulation tool is used to quantify the effect of the substrate and find the necessary air-gap height to enhance highfrequency performance of the inductor. A combination of photoresist deformation and conformal deposition of photoresist by electroplating is studied to realize such 3-D onchip inductors. Fabricated inductors are characterized and modeled at high frequencies. The 2-, 3-, and 5-turn archshape suspended inductors have inductances between 0.62 to 0.79 nh and peak-q factors between to 17 at peak-q frequencies between 4.7 to 7.0 GHz. The selfresonant frequency values estimated from the simplified physical models are between 47.6 to 88.6 GHz. Acknowledgment This work was supported in part by the National Science Foundation under the grant ECS and the State of Louisiana Board of Regents under the grant LEQSF RD-A-07. The supports of University of Texas at Dallas UTD cleanroom staffs Mr. K. Bradshaw and Mr. J. Goodnight and Louisiana State University cleanroom staff Mr. G. Hwang are acknowledged. The support of Dr. S. Villareal of UTD for the fabrication of devices is greatly appreciated. Valuable technical discussions with students at UTD Micro/Nano Devices and Systems Laboratory are appreciated. References 1. N. Nguyen and R. Meyer, Si IC-compatible inductors and LC passive filters, IEEE J. Solid-State Circuits 25 4, C. Nam and Y. Kwon, High-performance planar inductor on thick oxidized porous silicon OPS substrate, IEEE Microw. Guid. Wave Lett. 7 8, C. Chen, Y. Fang, C. Yang, and C. Tang, A deep submicron CMOS process compatible suspending high-q inductor, IEEE Electron Device Lett , D. Young, V. Malba, J. Ou, A. Bernhardt, and B. Boser, A low-noise RF voltage-controlled oscillator using on-chip high-q threedimensional coil inductor and micromachined variable capacitor, Solid-State Sensor Actuator Workshop, Dig. Tech. Papers, pp , Hilton Head Island, S.C Y. Kim and M. Allen, Surface micromachined solenoid inductors for high frequency applications, IEEE Trans. Components, Packag. Manufactur. Tech., Part C 21 1, J. Yoon, B. Kim, C. Han, E. Yoon, and C. Kim, Surface micromachined solenoid on-si and on-glass inductors for RF applications, IEEE Electron Device Lett. 20 9, H. Lee, Y. Lee, S. Kim, and S. Yun, Novel high-q solenoid inductor using bondwires for GaAs monolithic microwave integrated circuits MMICs, Jpn. J. Appl. Phys., Part B, L1523 L H. M. Greenhouse, Design of planar rectangular microelectronic inductors, IEEE Tran. Parts, Hybrids, Packag. PHP-10 2, N. Chomnawang and J. Lee, On-chip 3-D air core micro-inductor for high-frequency applications using deformation of sacrificial polymer, Proc. SPIE 4334, N. Chomnawang, Three-dimensional micromachined on-chip inductors for high frequency applications, PhD Dissertation, Louisiana State University J. Microlith., Microfab., Microsyst., Vol. 2 No. 4, October 2003

7 Nimit Chomnawang received the BEng degree in instrumentation engineering from King Mongkut s Institute of Technology, Ladkrabang, Thailand, in 1993, the MS degree in biomedical engineering from Virginia Commonwealth University in 1999, and MS and PhD degrees in electrical engineering from Louisiana State University in 2001 and 2002, respectively. Since 2002, he has been a lecturer at the School of Electrical Engineering, Suranaree University of Technology, Thailand. His research interests include microfabrication, MEMS, biomedical instrumentation, and embedded automation. Jeong-Bong Lee received the BS degree in electronics engineering from Hanyang University, Seoul, Korea, in 1986, and the MS and the PhD degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1993 and 1997, respectively. He worked for Georgia Tech as a research engineer after his graduation. In January 1999, he joined the Louisiana State University, Baton Rouge, as an assistant professor. Since May 2001, he has been with the University of Texas at Dallas as an assistant professor in the Department of Electrical Engineering. His current research interests are in the areas of rf/microwave MEMS, MEMS packaging techniques, nanophotonic devices, micro/nanoassemblers, and chemical/biological sensors. He is a recipient of the National Science Foundation s Faculty Early Career Development Award. Wendell Alan Davis graduated in 1971 from the University of Michigan, and after was employed at McMaster University, where we worked on p-i-n diode phase shifters and simulation studies for the Canadian Satellite Communication System. From 1973 to 1977, he was employed by General Electric (GE) at their research and development center in Schenectady, New York. At GE he worked on design of IM- PATT amplifiers in both alumina and ferrite substrates, hybrid coupler power combiners, and a microwave proximity detector. In 1977, he joined Raytheon in Bedford, Massachusetts, where he worked on design of IMPATT power combiners, which involved their thermal response, broadband directional couplers, Schiffman phase shifters, and various microwave filter designs. He was involved in computer optimization techniques and in the software design for an automated test station for antennas. In 1983 he joined the University of Texas at Arlington, where he has continued in research and teaching in the area of high-frequency analog electronics. He has published two texts in the area of microwave and radio frequency engineering. J. Microlith., Microfab., Microsyst., Vol. 2 No. 4, October