AN-4164 Design Guideline for 3-Channel Interleaved CCM PFC Using the FAN kw CCM PFC Controller

Transcription

1 Driver ircuit Driver ircuit Driver ircuit AN-6 Design Guideline or -hannel nterleaved M F Using the FAN967.5 kw M F ontroller ntroduction The interleaved boost ower Factor orrection (F) converter has become the topology o choice or highpower applications due to the improved eiciency that can be achieved through load current sharing. By sharing the load current in more than one balanced phase, the MS current stress, current ripple, and boost inductor size per phase can be signiicantly reduced. Thereore, the heavy load eiciency can be signiicantly improved, which allows or the selection o cost eective power MOSFET and boost diode as well as improved longevity o the power supply. The FAN967 advanced F controller can be an optimal solution or implementing high-power F (above several kilowatts). The FAN967 is a ontinuous onduction Mode (M) F controller or a three-channel interleaved boost-type pre-regulator. ncorporating circuits or the implementation o leading edge, average current mode, boost-type power actor correction; the FAN967 enables the design o a power supply that ully complies with the E000-- speciication. The FAN967 also eatures an innovative channel management unction, which allows the power level o the slave channels to be loaded / unloaded smoothly according to the voltage on M pin, thereby improving the F converter s load transient response. This application note presents practical design considerations or a -channel interleaved M boost F employing the FAN967. t includes the procedure or designing the boost inductor and output ilter, selecting the components, and implementing average current mode control. The design procedure is then veriied through an experimental.5 kw prototype converter. Figure shows the typical application circuit o the F converter. * DB B N F DF F F DF A ine n EM Filter B+ F DF FB FB B A SF SF SF SEN SEN SEN FB FB B A F F F B OF S+ S- OF S+ S- OF S+ S- A FBF B B B SS BBO SS EA MT MT MU MU signal (D) S MT DY O S FAN967 EA EA EA G G DD G K M M M GND K MT DD Standby ower MU K K MT K hannel Enable K MT * About DB please reerence System Design recautions Figure. Typical Application ircuit o FAN967 0 Fairchild Semiconductor orporation ev..

2 AN-6 Design rocedure n this section, a design procedure is presented using the schematic o Figure as the reerence. A.5 kw rated output power, three-channel M interleaved F with universal input range is selected as a design example. The design speciications are as ollows: Table. Design Speciications ine oltage ange 80~6 A F Output oltage ipple 5% ine Frequency 50 Hz Switching Frequency SW = 0 khz Nominal F Output oltage F = 9 F Eiciency η > 0.95 Minimum F Output oltage F = 50 Brownout ine oltage 60 A Output ower O =.5 kw Brown-n ine oltage 70 A Number o hannel hannel Management Method External Signal rom MU [STE-] Estimate nput ated ower and Output urrent The overall system is comprised o three parallel boost F stages, as shown in Figure, so the input power o the F stage is given as: TOT N () where is the combined eiciency o the F stages. The output current o F stage is given by: -TOT TOT () F The output current o each boost stage is given by: N F Figure. (Design Example) N TOT hannel Number Boost F Boost F Boost F 500 -TOT 6W 0.95 F Stage oniguration 500 -TOT 8W hannel Number 500 -TOT -TOT F 9 6.7A 6.7 -TOT.A hannel Number -TOT () -TOT F [STE-] Frequency Setting The internal oscillator requency o the FAN967 is determined by the external resistor on the pin. The switching requency is determined by the timing resistor, calculated as: 8 80 SW () The guaranteed switching requency ranges are 8 khz~0 khz and 55 khz~75 khz. (Design Example) o 0 k is selected to obtain 0 khz switching requency k 00 SW [STE-] N ange & A Setting The FAN967 senses the peak value o line voltage using the A pin, as shown in Figure. The peak value o the line voltage is obtained by a peak detect circuit using a sample-and-hold method. Meanwhile, the instantaneous line voltage inormation is obtained by sensing the current that lows into the A pin through A. A should be selected according to the input voltage range. For universal A input (85 ~6 ), should be set <.5 and A should chosen as 6 MΩ. the input is high-voltage single-a input (80 ~6 ), should be set >.5 (maximum is 5 ) and A should be chosen as MΩ. determines the application based on A input range. The change o inluences gain o gain modulator and brown-in/out hysteresis. 85 ~ 65 6 M,.5 A A 80 ~ 65 M,.5 A A The controller needs to set or the dierent input range as: (6) (5) 0 Fairchild Semiconductor orporation ev..

3 AN-6 N F The maximum current o boost inductor is: A FB FBF KF KF ( ) ( ) K AG NE MN () A (A) A A A S urrent ommand (. omd.) FB (Design Example) The average o the boost inductor current over one switching cycle at the peak o the minimum A line (assume it s brownout o F) is obtained as: (K) K B (EA) eak Detector B Gain Modulator AG A NE MN The boost inductor is obtained as: FBF EA Figure..5 ine Sensing ircuits (Design Example) The F is designed or high-voltage single-a input (80 ~6 ). A should be chosen as MΩ and is: 0 A70k.7 >.5 70 k is selected as or the A input range o 80 ~6. [STE-] F nductor Design The duty cycle o the boost switch at the peak o line voltage is given as: D F NE (7) F Then, the maximum current ripple o the boost inductor at the peak o minimum A line voltage is given as: NE MN F NE MN (8) F F SW The average o boost inductor current over one switching cycle at the peak o the line voltage or minimum A input is given by: F NEMN F NEMN K F AG F SW H The maximum current o the boost inductor is given as: K KF ( ) NEMN 8. ( ).7A [STE-5] F Output apacitor Selection D AG D ( cos( t)) DAG TOT NE FE TOT NE TOT AG NE MN (9) F K F. AG. AG. AG Figure.. K nductor urrent For a given current ripple actor (K F = / AG ), the boost inductor value can be obtained as: F NE MN F NE MN K F AG F SW (0) Figure 5. F Output oltage ipple The output voltage ripple should be considered when selecting the F output capacitor. Figure 5 shows the line requency ripple on the output voltage. With a given speciication o output ripple, the value or the output capacitor can be obtained rom: -TOT NE F E () where is nominal output current o the boost F stage and F-E is the peak-to-peak output voltage ripple. 0 Fairchild Semiconductor orporation ev..

4 AN-6 The hold-up time should also be considered when determining the output capacitor value: - TOT t HOD F F MN () where -TOT is nominal output power o boost F stage; t HOD is the required holdup time; and F-MN is the allowable minimum F output voltage during the hold-up time. (Design Example) With peak-to-peak voltage ripple speciication o 5% o F, the capacitor should be: NE -TOT F 50 (95%) [STE-6] Output Sensing & O Setting To improve system eiciency, the FAN967 incorporates the programmable F output voltage unction (O). As shown in Figure 6, when the F output voltage is much higher than the peak voltage o the A input, the user can input a D level rom the MU to the O pin to decrease the F output voltage. (t is recommended that the F output voltage is set at least 5 higher than the peak voltage o A input. Otherwise, it is necessary to consider other actors closely related to the F output voltage regulation, such as hold-up time, F, and THD standard o input current.) The relationship between the eedback voltage level or the F output voltage and O is given as: O FBF EF () Once the desired F output voltage, F, or low A input is determined; the required D voltage level O is given by: FE Since the minimum allowable output voltage during one cycle (5 ms) drop-out is 00, the capacitor value should be: -TOT HOD F F MN 9 00 FB O EF F ( ) FB FB FB t F n this case, three parallel connected capacitors o 90 F are selected or the F output capacitor. n this design example, the target application or the three-channel F is a home appliance power supply, so there is no hold-up time requirement. (5) gmv.5 S oltage rotection Figure 6. F External Signal (MU) O FBF FB FB FBF FB O 9 5 FBF.5.5 O 0 Two-evel F Output Block (Design Example) Set the F output level at 9, FB =.7 k: FB FB.70 (9.5) [STE-7] urrent-sensing & urrent-imit A FB ( F EF ).7M.5 N S M A K EA EF Set F =50 or low input A 00, the required O is then: FB O EF F ( ) FB FB FB ( ) The O unction is used to change the output voltage o F, F, which should be kept at least 5 higher than N. S+ M eak Detecter gmv T M S S- MO.5 gmi O Drive ogic OS F EA OF FBF FB+FB FB Figure 7. F ompensation ircuits 0 Fairchild Semiconductor orporation ev..

5 AN-6 Figure 7 shows the F compensation circuits. The irst step in compensation network design is to select the current-sensing resistor o the F converter, considering the control window o voltage loop. Since line eedorward is used in FAN967, the output power is proportional to the output o voltage control error ampliier, EA, as shown below: EA 0.6 ( EA ) MAX EA SAT 0.6 The maximum power limit o F is: MAX G NE MN MAX M A S (6) (7) The M is the output resistor o or multiplier to transer the current command to a voltage type signal. G MAX is a coeicient o the internal control loop. (Design Example) Setting the maximum power limit o each F stage as.08 kw (0% o ull load per channel), the current sensing resistor is obtained rom: S G S F ommand Gmi+ NE MN MAX M 6 A MAX 0.8 A 0 m resistor is selected. ase: Max. ower (Normal), EA-MAX B = 6 ight design, max power limited by EA Figure 8. Non-Saturation ase: >Max. ower (Abnormal), A cycle drop EA = 6, but abnormal short time, clamp by MT ight design at abnormal test, command rom Multiplier clamp by MT S.K MT = Saturation rotection MT/ ase: >Max. ower (Abnormal), A cycle drop, as let case, but user uses wrong choke can not aord current at Max. command. Wrong design at abnormal test, but protect by MT MT and MT Function MT The FAN967 has three cases o current limit protections via the EA, MT, and MT to protect O and inductor saturation. The user can program the current limit threshold MT and MT by resistor. ase, power (normal state): n the normal case, current / power should be controlled by a command, M, rom the gain modulator. When EA rises to 6, the output power and current o the system are at peak. The power and current can t increase urther. ase, current limit (abnormal state): The current command rom the gain modulator is k* A * EA / K. When the system works in abnormal state, such as when the A cycle is missed and returns in a short period, the K has a delay beore returning to the original level. This delay signiicantly increases the current command. the command is greater than the MT clamp level MT, it is limited as in ase, shown in Figure 8. the inductor current is not saturated, the peak current o this state can be the maximum current design or each channel. ase, current limit (saturation state): n case, use the level 80%~90% o maximum current o the switch device to be the saturation protection. This current protection is cycle by-cycle limited. A B Gain Modulator / * MT X Figure MT nternal Block o MT MT MT should be triggered beore MT, because MT is used to prevent saturation o the inductor rom damaging switches. MT signal limits the maximum power /current by clamping level MT. MT is set by the external resistor MT. t is typical to set the maximum power limit o the F stage to around 0%~50% o ull load, such that the EA is around ~.5. esistor MT can be calculated rom: MT.8 ( N / ) S (8) NE MN MT egarding the choice or MT level, the user can use 50% o maximum power as the setting. t s used to protect the switching devices. User can also use the maximum current rating o the semiconductor device with 0% to 0% de-rating as the limit level. MT setting is obtained as: MT 50% S K (9) MT (Design Example) S K S K SW =0 khz, is selected, MT and MT is: MT A A MT 00 50% k S K MT -5 MT 6.90 A 0 kω resistor is selected or MT. The setting o MT is obtained as: MT.8 ( N / ) S NEMN MT k A 7 kω resistor is selected or MT. 0 Fairchild Semiconductor orporation ev.. 5

6 AN-6 [STE-8] S & G Design Figure 0. t ON t OFF T Function or nductor urrent at t OFF The inear redict (T) unction, shown in Figure 0, is used to anticipate the behavior o inductor current in the switch turn-o region. The Gain hange (G) pin and S pin are used to adjust the parameters o T unction. The resistance can be determined by the ollowing equation. S S F FB FB FB FB (0) Gain change is to use to adjust the output o the gain modulation. The resistor value is given by: G FB A FB FB FB () (Design Example) nductance o 0 μh is selected. S and G are obtained as: S G -9 FB FB FB.50 S FB k k 6 FB FB FB FB.70 S and G are kω and 8. kω used. The transer unction o the compensation circuit is given as: s v v s S s where: EA Z G, and M Z The procedure to design the eedback loop is as ollows: () (5) (a) Determine the crossover requency ( ) around /0 th ~/6 th o the switching requency. Then calculate the gain o the transer unction o Equation (6) at crossover requency as: v v S S F AM F (6) (b) alculate such that it makes the closed loop gain unity at crossover requency: G M v v S (7) (c) Since the control-to-output transer unction o the power stage has -0 db/dec slope and -90 o phase at the crossover requency o 0 db, as shown in Figure, it is necessary to place the zero o the compensation network ( Z ) around on third (/) o the crossover requency so that more than 5 phase margin is obtained. Then the capacitor is determined as: ontrol-to-output 60dB / losed oop Gain (8) [STE-9] F urrent oop Design The transer unction that relates the duty cycle to the inductor current o boost power stage is given as: i F d s () F The transer unction relating the output o the current control error ampliier to the inductor current-sensing voltage is obtained by: v v s S S F EA AM F () where AM is the peak-to-peak voltage o the ramp signal or the current-control WM comparator, which is.8. 0 Fairchild Semiconductor orporation ev.. 6 0dB 0dB 0dB -0dB -0dB ompensation Figure. Z 0Hz 00Hz khz 0kHz 00kHz MHz urrent oop ompensation (d) lace compensator high-requency pole ( ) at least a decade higher than to ensure that it does not interere with the phase margin o the current loop at its crossover requency. (9)

7 AN-6 (Design Example) Set crossover requency as khz: vs S F v AM F [STE-0] F oltage oop Design Since FAN967 employs line eed-orward, the power stage transer unction becomes independent o the line voltage. Then, the low-requency, small-signal, control-tooutput transer unction is obtained as: vˆ F TOT KMAX (0) vˆ 5 s EA MAX where KMAX / and 5 is the control window o error ampliier ( =5 ) 60dB 0dB 0dB 0dB -0dB -0dB 0.09 (6.5-.5) 0 00 losed-oop Gain Figure. ontrol-to-output c ompensation 6 Hz 0Hz 00Hz khz k 6 v S GM v / nf / 0.5nF Modiy the D gain and BW o current loop, use 7. kω or,. nf or, and 00 pf or. oltage oop ompensation 0kHz roportional and integration () control with highrequency pole typically used or compensation. The compensation zero ( Z ) introduces phase boost, while the high-requency compensation pole S( ) attenuates the switching ripple, as shown in Figure. The transer unction o the compensation network is obtained as: s vˆ vˆ s F s OM Z where:.5 GM, Z and The procedure to design the eedback loop is as ollows: () () (a) Determine the crossover requency ( ) around /0~/5 o the line requency. Since the control-tooutput transer unction o power stage has -0 db/dec slope and -90 o phase at the crossover requency, shown in Figure as 0 db; it is necessary to place the zero o the compensation network ( Z ) around the crossover requency so that 5 phase margin is obtained. Then, the capacitor is determined as: G K M TOT MAX 5 ( ).5 F () To place the compensation zero at the crossover requency, the compensation resistor is obtained as: () (b) lace compensator high-requency pole ( ) at least a decade higher than to ensure that it does not interere with the phase margin o the voltage regulation loop at its crossover requency. t should also be suiciently lower than the switching requency o the converter so noise can be eectively attenuated. Then, the capacitor is determined as: (Design Example) Set the crossover requency as 0 Hz: G K M -TOT MAX 5 ( ).5 F nF ( 0) 9 96k nF (5) Modiy the D gain and BW o voltage loop; using 75 kω or, F or, and 0. F or. 0 Fairchild Semiconductor orporation ev.. 7

8 AN-6 [STE-] hannel Management ontrol Figure shows the M pin control with an external voltage signal. The EA control voltage is generated by regulation error ampliier and is proportional to average current o input. When M is pulled OW to 0, the F channel is enabled. When the M is pulled HGH and over, the channel is disabled. Figure shows that channel is disabled by an external signal when the system is operating at hal-load condition. Direct O S M A () O 6 M-MT () ndirect M M A EA A 0 00 O Figure 6. hannel Management by MU Figure. hannel Management by MU Full load, all channel operation [STE-] Sot Start Figure 7 shows the sot start (SS) waveorm. FAN967 uses sot-start voltage, SS, to clamp the F power command o voltage loop EA. To increase the sot-start time, the value o the sot-start capacitance SS can be increased. t SS SS SS (6) SS Mid. load, disable channel by external signal 0 à 80 (Design Example) Assuming that EA is out o clamping by SS at 5, the design sot-start time t SS is 50 ms and SS is 0 μa. The required sot-start capacitor value is: Figure. hase hange o External Signal ontrol The Figure 6 shows an external circuit used to change the slope o M/. When M/ is between ~ 0, changing the slope o M/ can increase / decrease the loading o the channel and decrease the overshoot/undershoot o the F output voltage, as the Figure 5 shows. This method signiicantly improves the dynamic load perormance o the F converter. SS 6 SS tss F 5 SS 0.7 F is selected or SS. A EF M / FBF F Sot Start =5k~0kΩ SS EA =70pF Figure 7. Sot-Start Waveorm M / Figure 5. hannel Management by MU 0 Fairchild Semiconductor orporation ev.. 8

9 AN-6 [STE-] K Setting The relationship o N.K to K is shown in Figure 8. The peak-detection circuits identiy the N inormation rom the A current through a ratio (the relationship shown in Equation (). aution: the maximum K can t be over.8 when system operation at maximum A input. As with the below design example, assume the maximum N.K at 7 (A6). The relationship o N.K / K is 00, then calculate the K =.7 <.8. N. K K K (7) 00.k Figure 8. N A K K A K K atio eak Detector elationship o N.K to K (Design Example) Assuming the K is.7 when N.K is 7, (A6) : 00 K.k K.k [STE-] ine Sensing or Brown-n / Out The FAN967 has an internal A U comparator that monitors the A input voltage and disables F stage when the BBO is less than.05 or 50 ms. the BBO voltage is over.9 /.75, the F stage enables. The pin is used to set the A input range, as shown in Table. B B B+ N B B F Action F Stop Figure 9. N. K. k is selected or K. BBO MS N p Brown-n / Out ircuits p 0/00Hz Table. A nput ange with ontroller Setting nput ange A () Setting A Setting Brown-n/Out evel Full-ange 85~ 6 0 kω 6 MΩ A 85 /75 H-Single 80~6 70 kω MΩ A 70 /60 The FAN967 senses the MS value and the instantaneous value o the line voltage using the BBO pins as shown in Figure 9. The MS value o the line voltage is obtained by an averaging circuit using a low-pass ilter with two poles. The MS sensing circuit should be designed considering the nominal operation range o line voltage and brownout protection trip point as: BO NE. BO B B B B B (8) B NE. MN (9) B B B where BO and B are brownout/in thresholds o MS. When A is ull range input (universal input), the brownout / in thresholds BO and B are.05 ( BBO-F ) and.9 ( BBO-F + BBO-F ). But i the A is high voltage single range input (A 80 ~6 ), the brownout/in thresholds o BO and B should be.05 ( BBO-H ) and.75 ( BBO-H + BBO-H ). t is typical to set B as 0% o B+. The poles o the low-pass ilter are given as: B B B B (0) () To properly attenuate the twice line requency ripple in MS, it is typical to set the poles around 0~0 Hz. (Design Example) The brownout protection thresholds are.05 ( BBO-H ) and.75 ( BBO- H+ BBO-H ) respectively. The scaling down actor o the voltage divider is: B BBO H B B B NE. BO m 60 The startup o the F controller at the minimum line voltage is checked as: NE. MN B B B B m The resistors o the voltage divider network are selected as B = B = M, B =00 k, and B =6. k. To place the poles o the low-pass ilter at 5 Hz and Hz, the capacitors are obtained as: 5nF B B nF B B Fairchild Semiconductor orporation ev.. 9

10 AN-6 Design Summary Application Output ower nput oltage Output oltage / Output urrent Single-Stage Three-hannel F 500 W 80~6 A 9 /6.6 A Features A80~6, Three-hannel F Using FAN967 Switch-harge Technique o Gain Modulator or Better F and ower THD 0 khz ow Switching Frequency Operation with GBT rotections: Over-oltage rotection (O), Under-oltage rotection (U), and Over-urrent rotection ( MT ), nductor Saturation rotection ( MT ) * DB N506 B F 0µH DF FFH5S60STU F F 0µH DF FFH5S60STU B FB F DF µf 0µH.MΩ 70μF FFH5S60STU SF~ FGH0N60UFD FB.5MΩ B MΩ A 6MΩ DD DD DD B MΩ A 6MΩ sen 0mΩ sen 0mΩ sen 0mΩ FB 70pF FB.7kΩ F~ 70Ω F nf B 00kΩ F.nF OF S- S+ OF S- S+ OF S- S+ B 7nF B 0.7μF B 6.kΩ SS 0.7µF A BBO SS FBF EA 00nF 75kΩ µf K 0nF K S S G.kΩ 0pF kω 0pF K S G FAN967 EA EA EA 00pF 7.kΩ.nF 00pF 7.kΩ.nF 00pF 7.kΩ.nF G 8.kΩ MT 0nF MT 0kΩ MT K DD DD μf nf Standby ower K 0.µF K.7kΩ M M M O GND DY MT 70kΩ D Setting evel MU signal (D) 0kΩ MU/ Sec. Stage (F eady) MT MT 0nF 7kΩ Figure 0. Final Schematic o Design Example 0 Fairchild Semiconductor orporation ev.. 0

11 AN-6 Appendix A Table. arameters o FAN967 Evaluation Board DD Maximum ating 0 DD O UO 0. /.8 O 0 ~ F Sot-Start SS = 0.7 µf Brown-n/Out 70 /60 Gate lamp. /.55 (96%/6%) DD Maximum ating 0 Table. MOSFET and Diode eerence Speciication GBTs oltage ating 600 (GBT) FGH0N60UFD Boost Diodes 600 FFH5S60STU System Design recautions ay attention to the inrush current when A input is irst connected to the boost F convertor. t is recommended to use NT and a parallel connected relay circuit to reduce inrush current. Add bypass diode D B to provide a path or inrush current when F starts up. The F stage is normally used to provide power to a downstream D-D or inverter. t s recommend that downstream power stage is enabled to operate at ull load once the F output voltage has reaches a level close to the speciied steady-state value. The O unction is used to change the output voltage o F, F. The F should be kept at least 5 higher than N. 0 Fairchild Semiconductor orporation ev..

12 AN-6 ayout Guide The current-sense resistor and current-sense ilter ( F, F ) should be as close to the S+/S- pins as possible. Similar to other power management devices, when laying out the B, it is important to use star grounding techniques and to keep the ilter capacitor and control components as close to the controller and its GND pin as possible. Keep high-current output and power ground paths separate rom the signal ground path. Make a singlepoint connection rom signal ground to the power ground. onnect the FAN967 s GND to the power ground at the negative terminal o. The ground o power stage and controller stage only meet at the negative terminal o the output capacitor,. The return path or the gate drive current should be connected to the power ground. Minimize the ground loops between the driver outputs, totem-pole buer transistors, power switches, and power ground. Keep the controller as close to the switching devices as possible to minimize the length and loop inductance o the high-current gate driving traces. To minimize the possibility o intererence caused by magnetic coupling rom the boost inductor, the device should be located at least.5 cm ( inch) away rom the boost inductor. t is also recommended that the device not be placed underneath magnetic components. Keep the width o B track handling the gate drive current to the switching devices wide to handle the high peak current level. DB B F DF F F DF B F DF FB SF~ FB B A 5 DD DD DD FB FB B A sen sen sen F F B OF S- S+ OF S- S+ OF S- S+ A FBF B B B MU (nput normation) BBO EA K K K K EA K SS FAN967 EA SS S S EA S G DD G G MT DD DD MT MT M M M O GND DY O O D Setting evel MU signal (D) MU/ Sec. Stage (F eady) Figure. ayout Diagram 0 Fairchild Semiconductor orporation ev..

13 AN-6 elated Datasheets FAN967 Three hannels nterleaved M F ontroller FEBFAN967_B0H5000A User Guide or FEBFAN967_B0H5000A FAN96 nterleaved Dual BM F ontroller AN-6086 Design onsideration or nterleaved Boundary onduction Mode (BM) F Using FAN96 FAN698 M ower Factor orrection ontroller AN-807 FAN80X F+WM ombo ontroller Application DSAME FAHD SEMONDUTO ESEES THE GHT TO MAKE HANGES WTH FUTHE NOTE TO ANY ODUTS HEEN TO MOE EABTY, FUNTON, O DESGN. FAHD DOES NOT ASSUME ANY ABTY ASNG OF THE AATON O USE OF ANY ODUT O UT DESBED HEEN; NETHE DOES T ONEY ANY ENSE UNDE TS ATENT GHTS, NO THE GHTS OF OTHES. FE SUOT OY FAHD S ODUTS AE NOT AUTHOZED FO USE AS TA OMONENTS N FE SUOT DEES O SYSTEMS WTH THE EXESS WTTEN AOA OF THE ESDENT OF FAHD SEMONDUTO OOATON. As used herein:. ie support devices or systems are devices or systems which, (a) are intended or surgical implant into the body, or (b) support or sustain lie, or (c) whose ailure to perorm when properly used in accordance with instructions or use provided in the labeling, can be reasonably expected to result in signiicant injury to the user.. A critical component is any component o a lie support device or system whose ailure to perorm can be reasonably expected to cause the ailure o the lie support device or system, or to aect its saety or eectiveness. 0 Fairchild Semiconductor orporation ev..