BCM Bus Converter. Not Recommended for New Designs PRELIMINARY DATASHEET L O A D

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1 BCM Bus Converter C US C S NRTL US FEATURES 48 Vdc 4 Vdc 200 W Bus Converter High efficienc (>94%) reduces sstem power consumption High power densit (>681 W/in 3 ) reduces power sstem footprint b >40% Contains built-in protection features: - Undervoltage - Overvoltage Lockout - Overcurrent Protection - Short circuit Protection - Overtemperature Protection Provides enable/disable control, internal temperature monitoring Can be paralleled to create multi-kw arras TYPICAL APPLICATIONS High End Computing Sstems Automated Test Equipment High Densit Power Supplies Communications Sstems DESCRIPTION The V I Chip bus converter is a high efficienc (>94%) Sine Amplitude Converter (SAC ) operating from a 38 to 55 Vdc primar bus to deliver an isolated, unregulated 3.2 to 4.6 output. The Sine Amplitude Converter offers a low AC impedance beond the bandwidth of most downstream regulators; therefore capacitance normall at the load can be located at the input to the Sine Amplitude Converter. Since the transformation ratio of the F040T is 1/12, the capacitance value can be reduced b a factor of 144x, resulting in savings of board area, materials and total sstem cost. The F040T is provided in a V I Chip package compatible with standard pick-and-place and surface mount assembl processes. The co-molded V I Chip package provides enhanced thermal management due to a large thermal interface area and superior thermal conductivit. The high conversion efficienc of the F040T increases overall sstem efficienc and lowers operating costs compared to conventional approaches. PART NUMBERING PART NUMBER PACKAGE STYLE PRODUCT GRADE F = J-Lead T = -40 to 125 C T = Through hole M = -55 to 125 C For Storage and Operating Temperatures see Section 6.0 General Characteristics TYPICAL APPLICATION enable / disable switch V IN F1 SW1 PC TM BCM TM Bus Converter +In -In +Out -Out L O A D Page 1 of 18

2 1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS The absolute maximum ratings below are stress ratings onl. Operation at or beond these maximum ratings can cause permanent damage to the device. MIN MAX UNIT MIN MAX UNIT +IN to IN V Output current average A VIN slew rate (operational) V/µs PC to IN V Isolation voltage, input to output V TM to IN V +OUT to OUT V Operating IC junction temperature C Output current transient Storage temperature C (< = 10 ms, < = 10% DC) A 2.0 ELECTRICAL CHARACTERISTICS Specifications appl over all line and load conditions unless otherwise noted; Boldface specifications appl over the temperature range of -40 C < T C < 100 C (T-Grade); All other specifications are at T C = 25ºC unless otherwise noted. POWERTRAIN ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT Input voltage range, continuous V IN_DC V Input voltage range, transient V IN_TRANS Full current or power supported, 50 ms max, 38 10% dut ccle max 55 V Quiescent current I Q Disabled, PC Low ma V IN to V OUT time T ON1 V IN = 48 V, PC floating ms No load power dissipation Inrush current peak P NL I INR_P V IN = 48 V, T C = 25ºC V IN = 48 V V IN = 38 V to 55 V, T C = 25ºC 8 V IN = 38 V to 55 V 12 Worse case of: V IN = 55 V, C OUT = 9100 µf, R LOAD = 73 mω W A DC input current I IN_DC At P OUT = 200 W 5 A Transformation ratio K K = V OUT /V IN, at no load 1/12 V/V Output power (average) P OUT_AVG 200 W Output power (peak) POUT_PK 10 ms max, POUT_AVG 200 W 300 W Output current (average) I OUT_AVG 53 A Output current (peak) I OUT_PK 10 ms max, I OUT_AVG 53 A 75 A V IN = 48 V, I OUT = 50 A; T c = 25 C Efficienc (ambient) η AMB V IN = 38 V to 55 V, I OUT = 50 A; T c = 25 C 90.5 % V IN = 48 V, I OUT = 25 A; T c = 25 C Efficienc (hot) η HOT V IN = 48 V, I OUT = 50 A; T c = 100 C % Efficienc (over load range) η 20% 10 A < I OUT < 50 A 80.5 % R OUT_COLD I OUT = 50 A, T c = -40 C mω Output resistance R OUT_AMB I OUT = 50 A, T c = 25 C mω R OUT_HOT I OUT = 50 A, T C = 100 C mω Switching frequenc F SW MHz Output voltage ripple Output inductance (parasitic) V OUT_PP L OUT_PAR C OUT = 0 F, I OUT = 50 A, V IN = 48 V, 20 MHz BW, Section 10 Frequenc up to 30 MHz, Simulated J-lead model mv 600 ph Output capacitance (internal) C OUT_INT Effective value at 4 V OUT 200 µf Output capacitance (external) C OUT_EXT µf Page 2 of 18

3 2.0 ELECTRICAL CHARACTERISTICS (CONT.) ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT PROTECTION Input overvoltage lockout threshold V IN_OVLO V Input overvoltage recover threshold V IN_OVLO V Input overvoltage lockout hsteresis V IN_OVLO_HYST 1.2 V Overvoltage lockout response time T OVLO 8 µs Fault recover time T AUTO_RESTART ms Input undervoltage lockout threshold V IN_UVLO V Input undervoltage recover threshold V IN_UVLO V Input undervoltage lockout hsteresis V IN_UVLO_HYST 1.6 V Undervoltage lockout response time T UVLO 8 µs Output overcurrent trip threshold I OCP A Output overcurrent response time constant T OCP Effective internal RC filter 6.2 ms Short circuit protection trip threshold I SCP 100 A Short circuit protection response time T SCP 1 µs Thermal shutdown threshold T J_OTP 125 ºC Safe Operating Area Average & Peak Output Power (W) Output Current (A) Output Voltage (V) P (ave) P (pk), < 10 ms I (ave) I (pk), < 10 ms Figure 1 Safe operating area Page 3 of 18

4 3.0 SIGNAL CHARACTERISTICS Specifications appl over all line and load conditions unless otherwise noted; Boldface specifications appl over the temperature range of -40 C < T C < 100 C (T-Grade); All other specifications are at T C = 25 C unless otherwise noted. The PC pin enables and disables the BCM. When held low, the BCM is disabled. In an arra of BCM modules, PC pins should be interconnected to snchronize start up and permit start up into full load conditions. PRIMARY CONTROL : PC PC pin outputs 5 V during normal operation. PC pin internal bias level drops to 2.5 V during fault mode, provided V IN remains in the valid range. SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT Regular PC voltage V PC V Operation PC available current I PC_OP ma ANALOG PC source (current) I PC_EN µa Standb OUTPUT PC resistance (internal) R PC_INT Internal pull down resistor kω Transition PC capacitance (internal) C PC_INT Section pf Start Up PC load resistance R PC_S To permit regular operation 60 kω Start Up PC time to start T ON ms Regular Operation PC enable threshold V PC_EN V DIGITAL Standb PC disable duration T PC_DIS_T Minimum time before attempting re-enable 1 s INPUT / OUPUT PC threshold hsteresis V PC_HYSTER 50 mv Transition PC enable to V OUT time T ON2 V IN = 48 V for at least T ON1 ms µs PC disable to standb time T PC-DIS 4 10 µs PC fault response time T FR_PC From fault to PC = 2 V 100 µs The TM pin monitors the internal temperature of the controller IC within an accurac of ±5 C. TEMPERATURE MONITOR : TM Can be used as a "Power Good" flag to verif that the BCM module is operating. Is used to drive the internal comparator for Overtemperature Shutdown. SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT ANALOG OUTPUT DIGITAL OUTPUT (FAULT FLAG) Regular Operation Transition Standb TM voltage range V TM V TM voltage reference V TM_AMB T J controller = 27 C V TM available current I TM 100 µa TM gain A TM 10 mv/ C TM voltage ripple V TM_PP C TM = 0 pf, V IN = 48 V, I OUT = 50 A mv TM capacitance (external) C TM_EXT 50 pf TM fault response time T FR_TM From fault to TM = 1.5 V 10 µs TM voltage V TM_DIS 0 V TM pull down (internal) R TM_INT Internal pull down resistor kω RESERVED : RSV Reserved for factor use. No connection should be made to this pin. Page 4 of 18

5 4.0 TIMING DIAGRAM VOVLO+ VOVLO NL VIN VUVLO+ VUVLO PC 5 V 3 V 5 V 3 V 2.5 V C C 500mS before retrial Vout B G D LL K A E F IOUT ISSP IOCP H TM 3 27 C 0.4 V A: TON1 B: TOVLO* C: TAUTO_RESTART D:TUVLO E: TON2 F: TOCP G: TPC DIS H: TSCP** 1: Controller start 2: Controller turn off 3: PC release 4: PC pulled low 5: PC released on output SC 6: SC removed Notes: Timing and signal amplitudes are not to scale Error pulse width is load dependent *Min value switching off **From detection of error to power train shutdown Page 5 of 18

6 5.0 APPLICATION CHARACTERISTICS The following values, tpical of an application environment, are collected at T C = 25ºC unless otherwise noted. See associated figures for general trend data. No Load Power Dissipation (W) No Load Power Dissipation vs. Line Input Voltage (V) T CASE: -40 C 25 C 100 C Figure 2 No load power dissipation vs. V IN Full Load Efficienc (%) Full Load Efficienc vs. T CASE V : IN Case Temperature ( C) 38 V 48 V 55 V Figure 3 Full load efficienc vs. temperature; V IN 95 Efficienc & Power Dissipation -40 C Case Efficienc & Power Dissipation 25 C Case 35 Efficienc (%) η P D Power Dissipation (W) Efficienc (%) η P D Power Dissipation (W) Load Current (A) V : IN 38 V 48 V 55 V 38 V 48 V 55 V Figure 4 Efficienc and power dissipation at T C = -40 C Load Current (A) V : IN 38 V 48 V 55 V 38 V 48 V 55 V Figure 5 Efficienc and power dissipation at T C = 25 C 0 Efficienc (%) Efficienc & Power Dissipation 100 C Case η P D Power Dissipation (W) Rout (mω) R OUT vs. T CASE at V IN = 48 V Load Current (A) V : IN 38 V 48 V 55 V 38 V 48 V 55 V Figure 6 Efficienc and power dissipation at T C = 100 C Figure 7 R OUT vs. temperature Case Temperature ( C) I : OUT 25 A 50 A Page 6 of 18

7 Ripple (mv pk-pk) Output Voltage Ripple vs. Load Load Current (A) V : IN 48 V Figure 8 V RIPPLE vs. I OUT ; No external C OUT. Board mounted module, scope setting : 20 MHz analog BW Figure 9 Full load ripple, 330 µf C IN ; No external C OUT. Board mounted module, scope setting : 20 MHz analog BW Figure 10 Start up from application of PC; V IN pre-applied C OUT = 9100 µf Figure 11 0 A 50 A transient response: C IN = 330 µf, I IN measured prior to C IN, no external C OUT Figure A 0 A transient response: C IN = 330 µf, I IN measured prior to C IN, no external C OUT Page 7 of 18

8 6.0 GENERAL CHARACTERISTICS Specifications appl over all line and load conditions unless otherwise noted; Boldface specifications appl over the temperature range of -40ºC < T J < 100ºC (T-Grade); All other specifications are at T J = 25 C unless otherwise noted. MECHANICAL ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT Length L / [1.270] / [1.280] / [1.289] mm/[in] Width W / [0.856] / [0.866] / [0.876] mm/[in] Height H 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm/[in] Volume Vol No heat sink 4.81 / [0.294] cm 3 /[in 3 ] Weight W 14.5 / [0.512] g/[oz] Nickel Lead finish Palladium µm THERMAL Gold F040T (T-Grade) C Operating temperature T J F040M (M-Grade) C Isothermal heatsink and Thermal resistance φ JC isothermal internal PCB 1 C/W Thermal capacit 5 Ws/ C ASSEMBLY Peak compressive force applied to case (Z-axis) Supported b J-lead onl 6 lbs 5.41 lbs / in 2 F040T (T-Grade) C Storage temperature T ST F040M (M-Grade) C Moisture sensitivit level ESD withstand SOLDERING Peak temperature during reflow MSL ESD HBM ESD CDM MSL 6, 4 hours out of bag maximum MSL 5 Human Bod Model, "JEDEC JESD 22-A114D.01"Class 1D Charge Device Model, "JEDEC JESD 22-C101-D" MSL 6, 4 hours out of bag maximum 245 C MSL C Peak time above 217 C s Peak heating rate during reflow C/s Peak cooling rate post reflow C/s SAFETY Working voltage (IN OUT) V IN_OUT 60 VDC Isolation voltage (hipot) V HIPOT 2,250 VDC Isolation capacitance C IN_OUT Unpowered unit pf Isolation resistance R IN_OUT At 500 Vdc 10 MΩ MIL-HDBK-217Plus Parts Count - 25 C Ground Benign, Stationar, 5.01 MHrs MTBF Indoors / Computer Profile Telcordia Issue 2 - Method I Case III; 25 C Ground Benign, Controlled 6.55 MHrs Agenc approvals / standards ctuvus curus CE Mark RoHS 6 of 6 V Page 8 of 18

9 7.0 USING THE CONTROL SIGNALS PC, TM Primar Control (PC) pin can be used to accomplish the following functions: Logic enable and disable for module: Once Ton1 time has been satisfied, a PC voltage greater than Vpc_en will cause the module to start. Bringing PC lower than Vpc_dis will cause the module to enter standb. Auxiliar voltage source: Once enabled in regular operational conditions (no fault), each BCM module PC provides a regulated 5 V, 3.5 ma voltage source. Snchronized start up: In an arra of parallel modules, PC pins should be connected to snchronize start up across units. This permits the maximum load and capacitance to scale b the number of paralleled modules. Output disable: PC pin can be activel pulled down in order to disable the module. Pull down impedance shall be lower than 60 Ω. Fault detection flag: The PC 5 V voltage source is internall turned off as soon as a fault is detected. Note that PC can not sink significant current during a fault condition. The PC pin of a faulted module will not cause interconnected PC pins of other modules to be disabled. Temperature Monitor (TM) pin provides a voltage proportional to the absolute temperature of the converter control IC. It can be used to accomplish the following functions: Monitor the control IC temperature: The temperature in Kelvin is equal to the voltage on the TM pin scaled b 100. (i.e. 3.0 V = 300 K = 27ºC). If a heat sink is applied, TM can be used to protect the sstem thermall. Fault detection flag: The TM voltage source is internall turned off as soon as a fault is detected. For sstem monitoring purposes microcontroller interface faults are detected on falling edges of TM signal. Page 9 of 18

10 8.0 F040T BLOCK DIAGRAM +Vin -Vin PC 3.1 V 1000 pf Vcc Wake-Up Power And Logic 18.5 V One shot dela Ton1 100 ua PC Pull-Up & Source 5 V, 2 ma min 150 K 2.5 V Vcc V2 Gate Drive suppl Adaptive Soft Start Modulator Enable Vin UVLO OVLO Start up & Fault logic Q1 Primar Gate Drive Q2 Primar current sensing Overtemperature Protection Q3 Primar Stage & Resonant Tank Lr Cr Q4 Vref Temp_Vref Temperature dependent voltage source Fast current Limit Slow current limit Power Transformer Q6 Secondar Gate Drive Overcurrent Protection 40 K Q5 1 K Snchronous Rectification 0.01 F +Vout COUT -Vout TM Page 10 of 18

11 9.0 SINE AMPLITUDE CONVERTER POINT OF LOAD CONVERSION 286 ph L IN IN = = 5.75 nh II OUT R OUT L OUT = 600 ph + V IN IN C IN RC CIN IN 0.57 mω 2µF IIQ Q 108 ma V I 0.35 Ω 1/12 I OUT + + 1/12 V IN K 2.2 mω C OUT C OUT R RC COUT 130 OUT µω 200 µf + V V OUT OUT Figure 13 V I Chip TM module AC model The Sine Amplitude Converter (SAC ) uses a high frequenc resonant tank to move energ from input to output. (The resonant tank is formed b Cr and leakage inductance Lr in the power transformer windings as shown in the BCM module Block Diagram. See Section 8). The resonant LC tank, operated at high frequenc, is amplitude modulated as a function of input voltage and output current. A small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionalit and is ke to achieving power densit. The F040T SAC can be simplified into the preceeding model. R OUT represents the impedance of the SAC, and is a function of the R DSON of the input and output MOSFETs and the winding resistance of the power transformer. I Q represents the quiescent current of the SAC control, gate drive circuitr, and core losses. The use of DC voltage transformation provides additional interesting attributes. Assuming that R OUT = 0 Ω and I Q = 0 A, Eq. (3) now becomes Eq. (1) and is essentiall load independent, resistor R is now placed in series with V IN. At no load: V OUT = V IN K (1) V IN Vin + R SAC SAC K = 1/32 1/12 Vout V OUT K represents the turns ratio of the SAC. Rearranging Eq (1): K= V OUT (2) V IN Figure 14 K = 1/12 Sine Amplitude Converter with series input resistor The relationship between V IN and V OUT becomes: In the presence of load, V OUT is represented b: V OUT = V IN K I OUT R OUT (3) and I OUT is represented b: V OUT = (V IN I IN R) K (5) Substituting the simplified version of Eq. (4) (I Q is assumed = 0 A) into Eq. (5) ields: V OUT = V IN K I OUT R K 2 (6) I OUT = I IN I Q (4) K Page 11 of 18

12 This is similar in form to Eq. (3), where R OUT is used to represent the characteristic impedance of the SAC. However, in this case a real R on the input side of the SAC is effectivel scaled b K 2 with respect to the output. Assuming that R = 1 Ω, the effective R as seen from the secondar side is 6.9 mω, with K = 1/12. A similar exercise should be performed with the additon of a capacitor or shunt impedance at the input to the SAC. A switch in series with V IN is added to the circuit. This is depicted in Figure 15. V IN Vin + S C SAC SAC K = 1/12 1/32 A change in V IN with the switch closed would result in a change in capacitor current according to the following equation: V OUT Figure 15 Sine Amplitude Converter with input capacitor Vout I C (t) = C dv IN (7) dt Assume that with the capacitor charged to V IN, the switch is opened and the capacitor is discharged through the idealized SAC. In this case, I C =I OUT K (8) Low impedance is a ke requirement for powering a highcurrent, low-voltage load efficientl. A switching regulation stage should have minimal impedance while simultaneousl providing appropriate filtering for an switched current. The use of a SAC between the regulation stage and the point of load provides a dual benefit of scaling down series impedance leading back to the source and scaling up shunt capacitance or energ storage as a function of its K factor squared. However, the benefits are not useful if the series impedance of the SAC is too high. The impedance of the SAC must be low, i.e. well beond the crossover frequenc of the sstem. A solution for keeping the impedance of the SAC low involves switching at a high frequenc. This enables small magnetic components because magnetizing currents remain low. Small magnetics mean small path lengths for turns. Use of low loss core material at high frequencies also reduces core losses. The two main terms of power loss in the BCM module are: - No load power dissipation (P NL ): defined as the power used to power up the module with an enabled powertrain at no load. - Resistive loss (R OUT ): refers to the power loss across the BCM module modeled as pure resistive impedance. P DISSIPATED = P NL + P ROUT (10) Therefore, P OUT = P IN P DISSIPATED = P IN P NL P ROUT (11) The above relations can be combined to calculate the overall module efficienc: η = POUT = P IN P NL P ROUT (12) P IN P IN substituting Eq. (1) and (8) into Eq. (7) reveals: I OUT = C dv OUT (9) K 2 dt The equation in terms of the output has ielded a K 2 scaling factor for C, specified in the denominator of the equation. A K factor less than unit results in an effectivel larger capacitance on the output when expressed in terms of the input. With a K = 1/12 as shown in Figure 15, C=1 µf would appear as C=144 µf when viewed from the output. = V IN I IN P NL (I OUT ) 2 R OUT V IN I IN = 1 ( P NL + (I OUT ) 2 R OUT ) V IN I IN Page 12 of 18

13 10.0 INPUT AND OUTPUT FILTER DESIGN A major advantage of SAC sstems versus conventional PWM converters is that the transformers do not require large functional filters. The resonant LC tank, operated at extreme high frequenc, is amplitude modulated as a function of input voltage and output current and efficientl transfers charge through the isolation transformer. A small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionalit and is ke to achieve power densit. This paradigm shift requires sstem design to carefull evaluate external filters in order to: 1.Guarantee low source impedance: To take full advantage of the BCM module s dnamic response, the impedance presented to its input terminals must be low from DC to approximatel 5 MHz. The connection of the bus converter module to its power source should be implemented with minimal distribution inductance. If the interconnect inductance exceeds 100 nh, the input should be bpassed with a RC damper to retain low source impedance and stable operation. With an interconnect inductance of 200 nh, the RC damper ma be as high as 1 µf in series with 0.3 Ω. A single electroltic or equivalent low-q capacitor ma be used in place of the series RC bpass. 2.Further reduce input and/or output voltage ripple without sacrificing dnamic response: Given the wide bandwidth of the module, the source response is generall the limiting factor in the overall sstem response. Anomalies in the response of the source will appear at the output of the module multiplied b its K factor. This is illustrated in Figures 11 and 12. storage ma be more densel and efficientl provided b adding capacitance at the input of the module. At frequencies <500 khz the module appears as an impedance of ROUT between the source and load. Within this frequenc range, capacitance at the input appears as effective capacitance on the output per the relationship defined in Eq. 5. C OUT = C IN K 2 Eq. 6 This enables a reduction in the size and number of capacitors used in a tpical sstem THERMAL CONSIDERATIONS V I Chip products are multi-chip modules whose temperature distribution varies greatl for each part number as well as with the input / output conditions, thermal management and environmental conditions. Maintaining the top of the F040T case to less than 100ºC will keep all junctions within the V I Chip module below 125ºC for most applications. The percent of total heat dissipated through the top surface versus through the J-lead is entirel dependent on the particular mechanical and thermal environment. The heat dissipated through the top surface is tpicall 60%. The heat dissipated through the J-lead onto the PCB surface is tpicall 40%. Use 100% top surface dissipation when designing for a conservative cooling solution. It is not recommended to use a V I Chip module for an extended period of time at full load without proper heat sinking. 3.Protect the module from overvoltage transients imposed b the sstem that would exceed maximum ratings and cause failures: The module input/output voltage ranges shall not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it. A criterion for protection is the maximum amount of energ that the input or output switches can tolerate if avalanched. Total load capacitance at the output of the BCM module shall not exceed the specified maximum. Owing to the wide bandwidth and low output impedance of the module, low-frequenc bpass capacitance and significant energ Page 13 of 18

14 12.0 CURRENT SHARING The performance of the SAC topolog is based on efficient transfer of energ through a transformer without the need of closed loop control. For this reason, the transfer characteristic can be approximated b an ideal transformer with a positive temperature coefficient series resistance. This tpe of characteristic is close to the impedance characteristic of a DC power distribution sstem both in dnamic (AC) behavior and for stead state (DC) operation. When multiple BCM modules of a given part number are connected in an arra the will inherentl share the load current according to the equivalent impedance divider that the sstem implements from the power source to the point of load. Some general recommendations to achieve matched arra impedances include: Dedicate common copper planes within the PCB to deliver and return the current to the modules. Provide as smmetric a PCB laout as possible among modules Appl same input / output filters (if present) to each unit. For further details see AN:016 Using BCM Bus Converters in High Power Arras. + Vin DC Z IN_EQ1 Z IN_EQ2 BCM1 R 0_1 BCM2 R 0_2 Z OUT_EQ1 Z OUT_EQ2 Vout Load 13.0 FUSE SELECTION In order to provide flexibilit in configuring power sstems V I Chip modules are not internall fused. Input line fusing of V I Chip products is recommended at sstem level to provide thermal protection in case of catastrophic failure. The fuse shall be selected b closel matching sstem requirements with the following characteristics: Current rating (usuall greater than maximum current of BCM module) Maximum voltage rating (usuall greater than the maximum possible input voltage) Ambient temperature Nominal melting I 2 t Recommend fuse: <= 10A Littlefuse Nano 2 Fuse REVERSE OPERATION BCM modules are capable of reverse power operation. Once the unit is started, energ will be transferred from secondar back to the primar whenever the secondar voltage exceeds VIN K. The module will continue operation in this fashion for as long as no faults occur. The F040T has not been qualified for continuous operation in a reverse power condition. Furthermore fault protections which help protect the module in forward operation will not full protect the module in reverse operation. Transient operation in reverse is expected in cases where there is significant energ storage on the output and transient voltages appear on the input. Transient reverse power operation of less than 10 ms, 10% dut ccle is permitted and has been qualified to cover these cases. Z IN_EQn BCMn R 0_n Z OUT_EQn Figure 16 BCM module arra Page 14 of 18

15 15.1 J-LEAD PACKAGE MECHANICAL DRAWING Click here to view original mechanical drawings on the Vicor website. mm (inch) NOTES: mm 1. DIMENSIONS ARE inch. 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:.X / [.XX] = +/-0.25 / [.01];.XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on 15.2 J-LEAD PACKAGE RECOMMENDED LAND PATTERN NOTES: mm 1. DIMENSIONS ARE inch. 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:.X / [.XX] = +/-0.25 / [.01];.XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on Page 15 of 18

16 15.3 THROUGH-HOLE PACKAGE MECHANICAL DRAWING Click here to view original mechanical drawings on the Vicor website. mm (inch) TOP VIEW ( COMPONENT SIDE ) NOTES: BOTTOM VIEW (mm) 1. DIMENSIONS ARE inch. 2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE: X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005] 3. RoHS COMPLIANT PER CST-0001 LATEST REVISION DXF and PDF files are available on 15.4 THROUGH-HOLE PACKAGE RECOMMENDED LAND PATTERN NOTES: (mm) 1. DIMENSIONS ARE inch. 2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE: X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005] 3. RoHS COMPLIANT PER CST-0001 LATEST REVISION RECOMMENDED HOLE PATTERN ( COMPONENT SIDE SHOWN ) DXF and PDF files are available on Page 16 of 18

17 15.5 RECOMMENDED HEAT SINK PUSH PIN LOCATION Click here to view original mechanical drawings on the Vicor website. (NO GROUNDING CLIPS) (WITH GROUNDING CLIPS) Notes: 1. Maintain 3.50 (0.138) Dia. keep-out zone free of copper, all PCB laers. 2. (A) Minimum recommended pitch is (1.555). This provides 7.00 (0.275) component edge-to-edge spacing, and 0.50 (0.020) clearance between Vicor heat sinks. (B) Minimum recommended pitch is (1.614). This provides 8.50 (0.334) component edge-to-edge spacing, and 2.00 (0.079) clearance between Vicor heat sinks. 3. V I Chip TM module land pattern shown for reference onl; actual land pattern ma differ. Dimensions from edges of land pattern to push pin holes will be the same for all full-size V I Chip products. 4. RoHS compliant per CST 0001 latest revision. 5. Unless otherwise specified: Dimensions are mm (inches) tolerances are: x.x (x.xx) = ±0.3 (0.01) x.xx (x.xxx) = ±0.13 (0.005) 6. Plated through holes for grounding clips (33855) shown for reference, heat sink orientation and device pitch will dictate final grounding solution BCM TM MODULE PIN CONFIGURATION Out -Out +Out -Out A B C D E F G H J K L M N P R T A B C D E H J K L M N P R T +In TM RSV PC -In Signal Name +In In TM RSV PC +Out Out Designation A1-E1, A2-E2 L1-T1, L2-T2 H1, H2 J1, J2 K1, K2 A3-D3, A4-D4, J3-M3, J4-M4 E3-H3, E4-H4, N3-T3, N4-T4 Bottom View Page 17 of 18

18 Warrant Vicor products are guaranteed for two ears from date of shipment against defects in material or workmanship when in normal use and service. This warrant does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warrant is extended to the original purchaser onl. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warrant, the buer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buer. The buer will pa all charges incurred in returning the product to the factor. Vicor will pa all reshipment charges if the product was defective within the terms of this warrant. Information published b Vicor has been carefull checked and is believed to be accurate; however, no responsibilit is assumed for inaccuracies. Vicor reserves the right to make changes to an products without further notice to improve reliabilit, function, or design. Vicor does not assume an liabilit arising out of the application or use of an product or circuit; neither does it conve an license under its patent rights nor the rights of others. Vicor general polic does not recommend the use of its components in life support applications wherein a failure or malfunction ma directl threaten life or injur. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor s comprehensive line of power solutions includes high densit AC-DC and DC-DC modules and accessor components, full configurable AC-DC and DC-DC power supplies, and complete custom power sstems. Information furnished b Vicor is believed to be accurate and reliable. However, no responsibilit is assumed b Vicor for its use. Vicor components are not designed to be used in applications, such as life support sstems, wherein a failure or malfunction could result in injur or death. All sales are subject to Vicor s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Intellectual Propert Notice Vicor and its subsidiaries own Intellectual Propert (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Propert Department. The products described on this data sheet are protected b the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA Tel: Fax: Customer Service: custserv@ Technical Support: apps@ Page 18 of 18