AP7363. Pin Assignments. Description. Features. Applications 1.5A LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR AP7363

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1 .5A LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROP LEAR REGULATOR Description The is a.5a adjustable-output voltage linear regulator with ultra-low dropout. The device includes pass element, error amplifier, band-gap, current limit, and thermal shutdown circuitry. The characteristics of low dropout voltage and fast transient response to step changes in load make the device suitable for low-voltage microprocessor applications. The typical quiescent current is approximately.5ma and changes little with load current. The built-in current-limit and thermal-shutdown functions prevent IC damage in fault conditions. This device is available in U-DFN23-8, SO-8EP, SOT223 and TO252 packages. Features Pin Assignments ADJ/ NC GND (Top View) U-DFN23-8 (Top View).5A Ultra-Low Dropout Linear Regulator Ultra-Low Dropout: 9mV at.5a Stable With µf Input/Output Capacitor, Any Types Wide Input Voltage Range: 2.2V to 5.5V Adjustable Output Voltage:.6V to 5.V Fixed Output Options: V,.2V,.5V,.8V, 2.5V, 3.3V Low Ground Pin Current 25nA Quiescent Current in Shutdown Mode Excellent Load/Line Transient Response Current Limit and Thermal Shutdown Protection Ambient Temperature Range: -4 C to +85 C U-DFN23-8, SO-8EP, SOT223 and TO252: Available in Green Molding Compound (No Br, Sb) Totally Lead-Free & Fully RoHS Compliant (Notes & 2) Halogen and Antimony Free. Green Device (Note 3) Applications ASIC Power Supplies In Printers, Graphics Cards, DVD Players, STBs, Routers, and so on FPGA and DSP Core or I/O Power Supplies SMPS Regulator Conversion From 3.3V or 5V Rail GND SO-8EP (Top View) 3 2 SOT223 (Fixed Output) (Top View) TO GND (TAB) GND ADJ/NC Notes:. No purposely added lead. Fully EU Directive 22/95/EC (RoHS), 2/65/EU (RoHS 2) & 25/863/EU (RoHS 3) compliant. 2. See for more information about Diodes Incorporated s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green products are defined as those which contain <9ppm bromine, <9ppm chlorine (<5ppm total Br + Cl) and <ppm antimony compounds. of 5

2 Typical Applications Circuit V V V V µf µf µf ADJ R µf GND GND R2 Fixed Output Adjustable Output R V VREF where R2 R 2 kω Pin Descriptions Pin Name SOT223 TO252 Pin Number U-DFN23-8 SO-8EP GND 2 Ground Function 2, 3, 4 Voltage Input Pin 3 5, 6, 7 Voltage Output Pin ADJ NA 8 Output feedback pin for adjustable version only a resistor divider from this pin to the pin and ground sets the output voltage. NC NA 8 No connection for fixed output version. EP/TAB The exposed pad (EP) removes heat from the package, and it is recommended that the EP is connected to a copper area. The die is electrically connected to the exposed pad. It is recommended to connect the EP externally to GND, but it should not be the only ground connection. Functional Block Diagram EN Gate Driver Current Limit and Thermal Shutdown R EN Gate Driver Current Limit and Thermal Shutdown ADJ.65V.65V R GND GND Fixed Version Adjustable Version 2 of 5

3 Absolute Maximum Ratings A = +25 C, unless otherwise specified.) Symbol Parameter Ratings Unit ESD HBM Human Body Model ESD Protection 2 V ESD MM Machine Model ESD Protection 2 V V Input Voltage -.3 to +6. V V Voltage -.3 to V +.3 V I Continuous Load Current Internal Limited T ST Storage Temperature Range -65 to +5 C T J Maximum Junction Temperature 5 C Recommended Operating Conditions (@T A = +25 C, unless otherwise specified.) Symbol Parameter Min Max Unit V Input Voltage V I Output Current.5 A T A Operating Ambient Temperature C T J Operating Junction Temperature (Note 5) C Notes: 4. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated are not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. 5. Operating junction temperature must be evaluated and derated as needed, based on ambient temperature (T A), power dissipation (P D), maximum allowable operating junction temperature (T J-MAX), and package thermal resistance (θ JA). 3 of 5

4 Electrical Characteristics A = +25 C, V = 3.3V, I = ma, C = µf, C = µf, unless otherwise specified.) Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T A = +25 C, and are provided for reference purposes only. Symbol Parameter Test Conditions Min Typ Max Unit V ADJ ADJ Pin Voltage V = V -M to V -MAX, I = ma to.5a I ADJ ADJ Pin Bias Current V = V -M to V -MAX V DROP Dropout Voltage (Note 6) I =.5A, V = 2.5V V / V Line Regulation (Note 7) V = V -M to V -MAX V / I Load Regulation (Note 7) I = ma to.5a I GND Ground Pin Current in Normal Operation Mode I = ma to.5a T A = +25 C Over temp T A = +25 C 5 Over temp 75 T A = +25 C 9 24 Over temp 28 T A = +25 C.4 Over temp.5 T A = +25 C.8 Over temp.33 T A = +25 C..2 Over temp.3 I -PK Peak Output Current V V - NOM -5% A I SC Short Circuit Current Grounded T A = +25 C 3.7 Over temp 2 t d(off) Turn-Off Delay From V EN < V IL to V = OFF, I =.5A 25 μs t d(on) Turn-On Delay From V EN > V IH to V = ON, I =.5A 25 μs PSRR Ripple Rejection V = 3.V, I =.5A, f = 2Hz 65 V = 3.V, I =.5A, f = khz 6 n(l/f) Output Noise Density F = 2Hz, C = μf Ceramic. µv/ Hz e n Output Noise Voltage BW = Hz khz, C = μf Ceramic T SHDN Thermal Shutdown Threshold T J Rising 7 T HYS Thermal Shutdown Hysteresis T J Falling From T SHDN ϴ JA ϴ JC Thermal Resistance Junction-to- Ambient Thermal Resistance Junction-to-Case U-DFN23-8 (Note 8) 74. SO-8EP (Note 8) 52.8 SOT223 (Note 8) 5.7 TO252 (Note 8) 87.8 U-DFN23-8 (Note 8) 28.2 SO-8EP (Note 8). SOT223 (Note 8) 8.5 TO252 (Note 8) 7.3 V na mv %/V %/A ma A db µv(rms) C C/W C/W Notes: 6. Dropout voltage is the minimum voltage difference between the input and the output at which the output voltage drops 2% below its nominal value. For any output voltage less than 2.5V, the minimum V operating voltage is the limiting factor. 7. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the adjust voltage tolerance specification. 8. Device mounted on 2 2 FR-4 substrate PCB, 2oz copper with minimum recommended pad layout. 4 of 5

5 V ADJ (V) DROP VOLTAGE (V) I GND (ma) V (V) NOISE (nv/ Hz) NOISE (nv/ Hz) Typical Performance Characteristics (@T J = +25 C, V = 2.7V, C = µf, C = µf, I = ma, V =.8V) k C = µf CER k C = µf k k k k FREQUENCY (Hz) Noise Density 3 k k FREQUENCY (Hz) Noise Density C 25 C.5-4 C.5.5 I LOAD (A) I GND vs. Load Current 2 3 V (V) Turn-On Characteristics C C C TEMPERATURE ( C) V vs. Temperature ADJ.5.5 LOAD CURRENT (A) Dropout Voltage vs. Load Current 5 of 5

6 REJECTION RATIO (db) Typical Performance Characteristics (continued) J = +25 C, V = 2.7V, C = µf, C = µf, I = ma, V =.8V) Turn-On Time Turn-On Time V =.2V (5mV/div) I L = A, C = μf CER V =.2V (5mV/div) I L =.5A, C = μf CER V = 3.V (2V/div) V = 3.V (2V/div) Time (μs/div) Time (μs/div) V = 3.3V C =μf CER Load Transient Response V =.8V (5mV/div) I LOAD = ma to.5a (A/div) Time (4μs/div) 3 2 V = 3.3V V =.8V I = A C = µf CER C = µf CER k k k M FREQUENCY (khz) PSRR 6 of 5

7 Application Note Input Capacitor A minimum 2.2μF ceramic capacitor is recommended between and GND pins to decouple input power supply glitch and noise. The amount of the capacitance can be increased without limit. A larger input capacitor, like μf, provides better load transient response. This input capacitor must be located as close as possible to the device to assure input stability and to reduce noise. For PCB layout, a wide copper trace is required for both and GND pins. A lower ESR capacitor type allows the use of less capacitance, while a higher ESR type requires more capacitance. Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The is stable with any type of capacitor with no limitations on minimum or maximum ESR. The device is designed to have excellent transient response for most applications with a small amount of output capacitance. The device is also stable with multiple capacitors in parallel, which can be of any type of value. Additional capacitance helps reduce undershoot and overshoot during transient loads. This capacitor must be placed as close as possible to and GND pins for optimum performance. Adjustable Operation The provides output voltage from.6v to 5.V through external resistor divider as shown below. The output voltage is calculated by the following equation: Where V REF =.6V (the internal reference voltage) V R V REF R 2 Rearranging the previous equation gives the following equation that is used for adjusting the output to a particular voltage: V R 2 V REF To maintain the stability of the internal reference voltage, R 2 must be kept smaller than kω. No Load Stability R Other than external resistor divider, no minimum load is required to keep the device stable. The device will remain stable and regulated in no load condition. 7 of 5

8 LOOP GA (db) PHASE MARG ( ) LOOP GA (db) PHASE MARG ( ) Application Note (continued) Stability and Phase Margin Any regulator that operates using a feedback loop must be compensated in such a way as to ensure adequate phase margin, which is defined as the difference between the phase shift and -8 degrees at the frequency where the loop gain crosses unity ( db). For most LDO regulators, the ESR of the output capacitor is required to create a zero to add enough phase lead to ensure stable operation. The has an internal compensation circuit that maintains phase margin regardless of the ESR of the output capacitor any type of capacitors can be used. The following charts show the gain/phase plot of the with an output of.2v, μf ceramic output capacitor, and delivering.5a load current and no load. The phase margin is about 9, which is very stable PHASE GA V = 2.7V V =.2V I L =.5A C = µf CER FREQUENCY(Hz) Gain-Bandwidth Plot for.5a Load k k k M PHASE GA V = 2.7V V =.2V I L = A C = µf CER -2-8 k k k M FREQUENCY(Hz) Gain-Bandwidth Plot for no Load Short-Circuit Protection When the output current at the pin is higher than the current limit threshold, the current limit protection triggers and clamps the output current to prevent overcurrent and to protect the regulator from damage due to overheating. Thermal Shutdown Protection Thermal protection disables the output when the junction temperature rises to approximately +7 C, which allows the device to cool down. When the junction temperature reduces to approximately +6 C, the output circuitry is enabled again. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the heat dissipation of the regulator and protects it from damage due to overheating. Low Quiescent Current The, consuming only around.5ma for all input range, provides great power saving in portable and low-power applications. Output Noise This is the integrated value of the output noise over a specified frequency range. Input voltage and output load current are kept constant during the measurement. Results are expressed in µvrms or µv Hz. The is a low-noise regulator and requires no external noise reduction capacitor. Output voltage noise is typically μvrms, and overall noise level is between Hz and khz. Noise is specified in two ways: Output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Output noise voltage is the RMS sum of spot noise over a specified bandwidth. Spot noise is measured in units µv/ Hz or nv/ Hz, and total output noise is measured in µv(rms). The primary source of noise in low-dropout regulators is the internal reference. 8 of 5

9 Application Note (cont.) Power Dissipation The device power dissipation and proper sizing of the thermal plane connected to the thermal pad is critical to avoid thermal shutdown and ensure reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated by: P D = (V - V ) I The maximum power dissipation, handled by the device, depends on the junction-to-ambient thermal resistance and maximum ambient temperature, which can be calculated by the following equation: P D _ max ( 5 C - T A ) R JA Ordering Information - XX XX- XX Output BLANK : ADJ :.V 2 :.2V 5 :.5V 8 :.8V 25 : 2.5V 33 : 3.3V Package HA : U-DFN23 SP : SO-8EP E : SOT223-3L D : TO252-3L Packing 7/3 : Tape & Reel Note: Part Number Package Code Packaging (Note 9) Quantity 7 /3 Tape and Reel Part Number Suffix -XXHA-7 HA U-DFN23-8 3/Tape & Reel -7 -XXSP-3 SP SO-8EP 25/Tape & Reel -3 -XXE-3 E SOT223-3L 25/Tape & Reel -3 -XXD-3 D TO252-3L 25/Tape & Reel TO252 and SOT223 are only available with fixed output version. Marking Information () U-DFN23-8 ( Top View ) XX Y W X XX : Identification Code Y : Year : ~9 W : Week : A~Z : ~26 week; a~z : 27~52 week; z represents 52 and 53 week X : Internal Code Device Package Identification Code ADJ U-DFN23-8 SA - U-DFN23-8 SB -2 U-DFN23-8 SC -5 U-DFN23-8 SD -8 U-DFN23-8 SE -25 U-DFN23-8 SF -33 U-DFN23-8 SG 9 of 5

10 Marking Information (continued) (2) SO-8EP ( Top View ) Logo Part Number for ADJ - for.v -2 for.2v -5 for.5v -8 for.8v -25 for 2.5V -33 for 3.3V 8 5 -VV YY WW X X E 4 YY : Year : 8, 9,~ WW : Week : ~52; 52 represents 52 and 53 week X X : Internal Code SO-8-EP (3) SOT223 ( Top View ) Logo Part Number 63 for ADJ 63-VV: for.v 2 for.2v 5 for.5v 8 for.8v 25 for 2.5V 33 for 3.3V 6 3-VV Y W X Y : Year : ~9 W : Week : A~Z : ~26 week; a~z : 27~52 week; z repersents 52 and 53 week X : Internal Code (4) TO252 ( Top View ) Logo Part Number 63-VV : for.v 2 for.2v 5 for.5v 8 for.8v 25 for 2.5V 33 for 3.3V 63-VV YY WW Xx YY : Year : ~9 WW : Week : ~52, 52 represents 52 and 53 week Xx : Internal Code of 5

11 A A C Q E H Package Outline Dimensions (All dimensions in mm.) Please see for the latest version. ) U-DFN23-8 A A A3 (Pin # ID) E C'.25*45 D2 D e E2 Seating Plane L U-DFN23-8 Dim Min Max Typ A A.5.2 A b D D e E E L Z All Dimensions in mm z b 2) SO-8EP R. 9 (All side) e D b EXPOSED PAD 4 ±3 7 N 45 F E E L Gauge Plane Seating Plane SO-8EP Dim Min Max Typ A A..3 - b C D E E E e F H L N Q All Dimensions in mm of 5

12 Package Outline Dimensions (continued) (All dimensions in mm.) Please see for the latest version. 3) SOT223 D b Q C A A e e b 7 Gauge Plane Seating Plane.25 L E - E SOT223 Dim Min Max Typ A A..5.5 b b C D E E e e L Q All Dimensions in mm 7 4) TO252 (Standard) L3 L4 Option A (Top View) e E b3 b2(2x) D b(3x) Option B (Top View) E D 7 ± A2 c A Option A (Bottom View) H Gauge Plane a.58 L Option B (Bottom View) 2.74REF A Seating Plane TO252 (Standard) Dim Min Max Typ A A..3.8 A b b b c D D e E E H L L L a - All Dimensions in mm 2 of 5

13 Suggested Pad Layout Please see for the latest version. ) U-DFN23-8 X2 C Y Y2 X Y Value Dimensions (in mm) C.5 G.25 X.35 X.5 X2.85 Y.6 Y.6 Y2 3.3 Pin X G 2) SO-8EP X2 Y2 X Y Y Dimensions Value (in mm) C.27 X.82 X 3.52 X Y.55 Y 2.63 Y2 6.5 C X 3 of 5

14 Suggested Pad Layout (continued) Please see for the latest version. 3) SOT223 X Y Y C Y2 Dimensions Value (in mm) C 2.3 C 6.4 X.2 X 3.3 Y.6 Y.6 Y2 8. X C 4) TO252 (Standard) X Y2 Y C Dimensions Value (in mm) C X.6 X Y 2.6 Y 5.7 Y2.7 Y X 4 of 5

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