SG1526B/SG2526B/SG3526B

Transcription

1 SG156B/SG56B/SG356B REGULATING PULSE WIDTH MODULATOR DESCRIPTION The SG156B is a high-performance pulse width modulator for switching power supplies which offers improved functional and electrical characteristics over the industrystandard SG156. A direct pin-for-pin replacement for the earlier device with all its features, it incorporates the following enhancements: a bandgap reference circuit for improved regulation and drift characteristics, improved undervoltage lockout, lower temperature coefficients on oscillator frequency and current-sense threshold, tighter tolerance on softstart time, much faster SHUTDOWN response, improved double-pulse supperession logic for higher speed operation, and an improved output driver design with low shoot-through current, and faster rise and fall times. This versatile device can be used to implement single-ended or push-pull switching regulators of either polarity, both transformerless and transformer-coupled. The SG156B is specified for operation over the full military ambient temperature range of -55 C to 1 C. The SG56B is characterized for the industrial range of -5 C to 1 C, and the SG356B is designed for the commercial range of 0 C to 15 C. BLOCK DIAGRAM FEATURES HIGH RELIABILITY FEATURES 8 to 35 Operation 5 Low drift 1% Bandgap Reference 1Hz to 0kHz Oscillator Range Dual 0mA Source/Sink Digital Current Limiting Double Pulse Suppression Programmable Deadtime Improved Undervoltage Lockout Single Pulse Metering Programmable Soft-start Wide current Limit Common Mode Range TTL/CMOS Compatible Logic Ports Symmetry Correction Capability Guaranteed 6 Unit Synchronization Shoot-through Currents Less than 0mA Improved Shutdown Delay Improved Rise and Fall Time Available To MIL-STD-883, 1..1 Available to DSCC - Standard Microcircuit Drawing (SMD) MIL-M385/1603BA - SG156BJ-JAN Radiation data available MSC-AMS Level "S" Processing Available REF + IN Reference Regulator Undervoltage Lockout + C GROUND R D To Internal Circuitry SYNC R T Oscillator OUTPUT A C T RESET C SOFTSTART COMPENSATION + ERROR ERROR + C.S. Soft Start + IN Amp S Q D Q METERING F/F S R Q MEMORY F/F T Q Q TOGGLE F/F OUTPUT B C.S. SHUTDOWN December 014 Rev Microsemi Corporation

2 ABSOLUTE MAXIMUM RATINGS (Note 1) Input oltage ( IN ) Collector Supply oltage ( C ) Logic Inputs to 5.5 Analog Inputs to IN Source/Sink Load Current (each output)... 00mA Reference Load Current... ma Note 1. Exceeding these ratings could cause damage to the device. Logic Sink Current... 15mA Operating Junction Temperature Hermetic (J, L Packages)... 1 C Plastic (N, DW Packages)... 1 C Storage Temperature Range C to 1 C Lead Temperature (Soldering, Seconds) C RoHS Peak Package Solder Reflow Temp. (40 sec. max. exp.) C (+0, -5) THERMAL DATA J Package: Thermal Resistance-Junction to Case, θ JC... 5 C/W Thermal Resistance-Junction to Ambient, θ JA C/W N Package: Thermal Resistance-Junction to Case, θ JC C/W Thermal Resistance-Junction to Ambient, θ JA C/W DW Package: Thermal Resistance-Junction to Case, θ JC C/W Thermal Resistance-Junction to Ambient, θ JA C/W L Package: Thermal Resistance-Junction to Case, θ JC C/W Thermal Resistance-Junction to Ambient, θ JA C/W Note A. Junction Temperature Calculation: T J = T A + (P D x θ JA ). Note B. The above numbers for θ JC are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The θ JA numbers are meant to be guidelines for the thermal performance of the device/pcboard system. All of the above assume no ambient airflow. RECOMMENDED OPERATING CONDITIONS (Note ) Input oltage... 8 to 35 Collector Supply oltage to 35 Sink/Source Load Current (each output)... 0 to 0mA Reference Load Current... 0 to 0mA Oscillator Frequency Range... 1Hz to 0kHz Oscillator Timing Resistor... kω to 1kΩ Note. Range over which the device is functional. Oscillator Timing Capacitor pF to 0µF Available Deadtime Range at 40kHz... 5% to % Operating Junction Temperature Range: SG156B C to 15 C SG56B C to 85 C SG356B... 0 C to 70 C ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG156B with -55 C T A 15 C, SG56B with -5 C T A 85 C, SG356B with 0 C T A 70 C, and IN = 15. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.) Parameter Test Conditions SG156B/56B SG356B Min. Typ. Max. Min. Typ. Max. Units Reference Section (Note 3) Output oltage Line Regulation Load Regulation Temperature Stability (Note 9) Total Output oltage Range (Note 9) Short Circuit Current Undervoltage Lockout Section RESET Output oltage RESET Output oltage T J = 5 C IN = 8 to 35 I L = 0 to 0mA Over Operating T J REF = 0 REF = 3.8 REF = m m m ma 0.4

3 ELECTRICAL CHARACTERISTICS (continued) Parameter Oscillator Section (Note 4) Initial Accuracy oltage Stability Temperature Stability (Note 9) Minimum Frequency (Note 9) Maximum Frequency Sawtooth Peak oltage Sawtooth alley oltage SYNC Pulse Width Error Amplifier Section (Note 5) Input Offset oltage Input Bias Current Input Offset Current DC Open Loop Gain High Output oltage Low Output oltage Common Mode Rejection Supply oltage Rejection PWM Comparator Section (Note 4) Minimum Duty Cycle Maximum Duty Cycle T J = 5 C IN = 8 to 35 Over Operating T J R T = 1kΩ, C T = 0µF R T = kω, C T = 470pF IN = 35 IN = 8 R L =.0kΩ to REF R S kω Digital Ports (SYNC, SHUTDOWN, and RESET) HIGH Output oltage I SOURCE = 40µA LOW Output oltage I SINK = 3.6mA HIGH Input Current IH =.4 LOW Input Current IL = 0.4 SHUTDOWN Delay to Output (Note9) Current Limit Comparator Section (Note 6) Sense oltage R S Ω Input Bias Current Delay to Output (Note 9) Soft-Start Section Error Clamp oltage RESET = 0.4 C S Charging Current RESET =.4 Output Drivers (each output) (Note 7) HIGH Output oltage I SOURCE = 0mA I SOURCE = 0mA LOW Output oltage I SINK = 0mA I SINK = 0mA Collector Leakage C = 40 Rise Time C L = 00pF Fall Time C L = 00pF Power Consumption Section (Note 8) Standby Current Test Conditions R L MΩ PIN1 - PIN 1m, I SOURCE = 0µA PIN - PIN1 1m, I SINK = 0µA R S kω IN = 8 to 35 Note 3. I L = 0mA Note 4. F OSC = 40kHz (R T = 4.1kΩ ±1%, C T =.01µF ±1%, R D = 0Ω) Note 5. CM = 0 to 5. Note 6. CM = 0 to 1 COMPENSATION = 0.4 COMPENSATION = SG156B/56B SG356B Min. Typ. Max. Min. Typ. Max ± ± ± ± % % Units % % % Hz khz µs m na na db db db µa µa ns m µa ns Note 7. C = 15 Note 8. IN = 35 Note 9. These parameters, although guaranteed over the recommended operating conditions, are not tested in production SHUTDOWN = ma µa µa µs µs 3

4 CHARACTERISTIC CURES FIGURE 1. REFERENCE OLTAGE S. SUPPLY OLTAGE FIGURE. REFERENCE TEMPERATURE STABILITY FIGURE 3. REFERENCE SHORT CIRCUIT 1k k 0k 1k k 0k FIGURE 4. REFERENCE RIPPLE REJECTION FIGURE 5. UNDER OLTAGE LOCKOUT FIGURE 6. ERROR AMPLIFIER OPEN LOOP GAIN S. FREQUENCY FIGURE 7. FIGURE 8. FIGURE 9. SOFTSTART TIME CONSTANT S. C S CURRENT LIMIT TRANSFER FUNCTION COMPARATOR INPUT TO DRIER OUTPUT DELAY 4

5 CHARACTERISTIC CURES (continued) Rt =.7k RD = 0Ω FOSC = 40kHz CT = 0.01µF FIGURE. STANDBY CURRENT S. SUPPLY OLTAGE FIGURE 11. OUTPUT DRIER DEADTIME S. C T ALUE FIGURE 1. OUTPUT DRIER DEADTIME S. R D ALUE Rt =.k - 155k Rt =.k - 155k Rt =.k - 155k (khz) (khz) khz FIGURE 13. SUPPLY CURRENT S. OUTPUT FREQUENCY FIGURE 14. SUPPLY CURRENT S. OUTPUT FREQUENCY FIGURE 15. SUPPLY CURRENT S. OUTPUT FREQUENCY FOSC = 40kHz Rt = 4.1k FIGURE 16. OSCILLATOR FREQUENCY TEMPERATURE STABILITY FIGURE 17. OUTPUT DRIER SATURATION OLTAGE FIGURE 18. SHUTDOWN INPUT TO DRIER OUTPUT DELAY 5

6 CHARACTERISTIC CURES (continued) RT - (kω) FIGURE 19. OSCILLATOR PERIOD S. R T AND C T APPLICATION INFORMATION OLTAGE REFERENCE The reference regulator of the SG156B is a band-gap type; that is, the precision +5 volt output is derived from the very predictable base-emitter voltage of an NPN transistor. Since this is a sub-surface phenomenon, the resulting output exhibits excellent stability compared to earlier surface-breakdown Zener designs. The reference output is stabilized at input voltages as low as +8 volts, and can provide up to 0mA of load current to external circuitry. An external PNP transistor can be used to boost the available current to many hundreds of ma. A rugged low-frequency audiotype transistor should be used, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of oscillation. FIGURE 0. EXTENDING REFERENCE OUTPUT CURRENT UNDEROLTAGE LOCKOUT The undervoltage lockout circuit protects the SG156B and the power devices it controls from inadequate supply voltage. If + IN is too low, the circuit disables the output drivers and holds the RESET pin LOW. This prevents spurious output pulses while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state. The circuit consists of a merged bandgap reference and comparator circuit which is active when the reference voltage has risen to BE or 1. volts at 5 o C. When the reference voltage rises to approximately +4.4 volts, the circuit enables the output drivers and releases the RESET pin, allowing a normal softstart. The comparator has 00m of hysteresis to minimize oscillation at the trip point. When + IN to the PWM is removed and the reference drops to +4. volts, the undervoltage circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle. The SG156B can operate from a +5 volt supply regulated to within ±4% by connecting the REF pin to the + IN pin. FIGURE 1. SIMPLIFIED UNDEROLTAGE LOCKOUT SOFT-START CIRCUIT The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the SG156B, the undervoltage lockout circuit holds RESET LOW with Q3. Q1 is turned on, which holds the soft-start capacitor voltage at zero. The second collector of Q1 clamps the output of the error amplifier to ground, guaranteeing zero duty cycle at the driver outputs. When the supply voltage reaches normal operating range, RESET will go HIGH. Q1 turns off, allowing the internal 0µA current source to charge C S. Q clamps the error amplifier output to BE above the voltage on C S. As the soft-start voltage ramps up to +5 volts, the duty cycle of the PWM linearly increases to whatever value the voltage regulation loop requires for an error null. Figure 7 gives the timing relationship between C S ramp time to 0% duty cycle. FIGURE. SOFT-START CIRCUIT SCHEMATIC 6

7 APPLICATION INFORMATION (continued) DIGITAL CONTROL PORTS The three digital control ports of the SG156B are bidirectional. Each pin can drive TTL and 5 volt CMOS logic directly, up to a fan-out of low-power Schottky gates. Each pin can also be directly driven by open-collector TTL, open-drain CMOS, and open-collector voltage comparators, fan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC LOW initiates a discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits all PWM output pulses. Holding RESET LOW discharges the soft-start capacitor. The logic threshold is +1.1 volts at +5 o C. Noise immunity can be gained at the expense of fan-out with an external k pull-up resistor to +5. TO INTERNAL LOGIC 40k FIGURE 3 DIGITAL CONTROL PORT SCHEMATIC 0k OSCILLATOR The oscillator is programmed for frequency and dead time with three components: R T C T, and R D. Two waveforms are generated: a sawtooth waveform at pin for pulse width modulation, and a logic clock at pin 1. The following procedure is recommended for choosing timing values: 1. With R D = 0Ω (pin 11 shorted to ground) select values for R T and C T from Figure 19 to give the desired oscillator period. Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the + C terminal is the same as the oscillator frequency.. If more dead time is required, select a larger value of R D using Figure 1 as a guide. At 40 khz dead time increases by 300 ns/ω. 3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of R T slightly to bring the frequency back to the nominal design value. The SG156B can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency % slower than the sync frequency. A periodic LOW logic pulse approximately 0.5 µsec wide at the SYNC pin will then lock the oscillator to the external frequency. Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing its sawtooth and clock waveforms with the slave units. All C T terminals are connected to the C T pin of the master, and all SYNC terminals are likewise connected to the SYNC pin of the master. Slave R T terminals should not be left open; at least k should be connected from each pin to ground. Slave R D terminals may be either left open or grounded. FIGURE 4. OSCILLATOR CONNECTIONS AND WAEFORMS ERROR AMPLIFIER The error amplifier is a transconductance design, with an output impedance of megohms. Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated for unity-gain stability with 0 pf, the amplifier has an open-loop pole at 400 Hz. The input connections to the error amplifier and determined by the polarity of the switching supply output voltage. For positive supplies, the common-mode voltage is +5.0 volts and the feedback connections in Figure 5A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0 volt reference voltage, as shown in Figure 5B. (A) FIGURE 5. ERROR AMPLIFIER CONNECTIONS (B) 7

8 APPLICATION INFORMATION (continued) OUTPUT DRIERS The totem-pole output drivers of the SG156B are designed to source and sink 0mA continuously and 00mA peak. Loads can be driven either from the output pins 13 and 16, or from the + C pin, as required. Curves for the saturation voltage at these outputs as a function of load current are found in Figure 17. FIGURE 6. PUSH-PULL CONFIGURATION FIGURE 7. SINGLE-ENDED CONFIGURATION FIGURE 8. DRIING N-CHANNEL POWER MOSFETS SG156B LAB TEST FIXTURE 1k 4.1k k k k 33k k 7Ω 1k 665k 1k -IB 1k k +IB k 8

9 CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below) Package Part No. Ambient Temperature Range Connection Diagram 18-PIN CERAMIC DIP J - PACKAGE 18-PIN PLASTIC DIP N - PACKAGE SG156BJ-883B SG156BJ-JAN SG156BJ-DESC SG156BJ SG56BJ SG356BJ -55 C to 15 C -55 C to 15 C -55 C to 15 C -55 C to 15 C -5 C to 85 C 0 C to 70 C SG56BN -5 C to 85 C SG356BN 0 C to 70 C + ERROR - ERROR COMPENSATION C SOFTSTART RESET - CURRENT SENSE + CURRENT SENSE SHUTDOWN R T REF + IN OUTPUT B GROUND COLLECTOR OUTPUT A SYNC R DEADTIME N Package: RoHS Compliant / Pb-free Transition DC: 03 N Package: RoHS / Pb-free 0% Matte Tin Lead Finish C T 18-PIN WIDE BODY PLASTIC SOIC DW - PACKAGE SG56BDW -5 C to 85 C SG356BDW 0 C to 70 C +ERROR -ERROR COMPENSATION C SOFTSTART RESET - CURRENT SENSE + CURRENT SENSE SHUTDOWN R T REF + IN OUTPUT B GROUND + COLLECTOR OUTPUT A SYNC R DEADTIME DW Package: RoHS Compliant / Pb-free Transition DC: 0516 DW Package: RoHS / Pb-free 0% Matte Tin Lead Finish C T 0-PIN CERAMIC SG156BL-883B -55 C to 15 C 1. N.C. LEADLESS CHIP CARRIER SG156BL -55 C to 15 C. +ERROR L- PACKAGE 3. -ERROR 4. COMP 5. C SOFTSTART 6. RESET 7. - C.S C.S SHUTDOWN. R T C T 1. R DEADTIME 13. SYNC 14. OUTPUT A COLLECTOR 16. N.C. 17. GROUND 18. OUTPUT B IN 0. REF Note 1. Contact factory for JAN and DESC product availability. Note. All parts are viewed from the top. Note 3. Hermetic Packages J and L use Pb37/SN63 hot solder lead finish, contact factory for availability of RoHS versions. 9

10 PACKAGE OUTLINE DIMENSIONS Controlling dimensions are in inches, metric equivalents are shown for general information. B Seating Plane H 18 1 F G A D 9 K C J L M DIM MILLIMETERS INCHES MIN MAX MIN MAX A B C D F G.54 BSC 0.0 BSC H J K L M Note: Dimensions do not include protrusions; these shall not exceed 0.155mm (0.006 ) on any side. Lead dimension shall not include solder coverage. Figure 9 J 18-Pin CERDIP Package Dimensions E3 A A1 3 L D 8 E L Dim MILLIMETERS INCHES MIN MAX MIN MAX D/E E e 1.70 BSC 0.0 BSC B TYP 0.05 TYP L A h 16 TYP TYP A A L B3 0.03R 0.008R 1 Note: All exposed metalized area shall be gold plated 60 µ-inch minimum thickness over nickel plated unless otherwise specified in purchase order. 13 A h 18 B1 e B3 Figure 30 L 0-Pin Ceramic LCC Package Dimensions

11 PACKAGE OUTLINE DIMENSIONS (continued) H A D e B Seating Plane E L A A 1 c DIM MILLIMETERS INCHES MIN MAX MIN MAX A A A B c D E e 1.7 BSC 0.05 BSC H L θ * LC * Lead Coplanarity Note: Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm (0.006 ) on any side. Lead dimension shall not include solder coverage. Figure 31 DW 18-Pin Plastic Wide-body SOIC (SOWB) Package Dimensions Dim MILLIMETERS INCHES MIN MAX MIN MAX D A E1 A A 3.30 Typ Typ 1 b b1 b E c A A A1 c D e.54 BSC 0.0 BSC L E e b SEATING PLANE M E L M Note: Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm (0.006 ) on any side. Lead dimension shall not include solder coverage. Figure 3 N 18-Pin Plastic Dual Inline Package Dimensions 11

12 Microsemi Corporate Headquarters One Enterprise, Aliso iejo CA 9656 USA Within the USA: +1 (800) Outside the USA: +1 (949) Sales: +1 (949) Fax: +1 (949) Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso iejo, Calif. and has approximately 3,400 employees globally. Learn more at Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. SG156B.04/1.14