A LOW TO HIGH VOLTAGE TOLERANT LEVEL SHIFTER FOR POWER MINIMIZATION

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1 International Journal of VLSI Design, 2(2), 2011, pp A LOW TO HIGH VOLTAGE TOLERANT LEVEL SHIFTER FOR POWER MINIMIZATION Harpreet Kaur 1, & Arvind Rajput 2 UIET, Panjab University, Chandigarh, harpreet.banwait6@gmail.com Abstract: A Level shifter used in multiple voltage digital circuits is presented. Level shifter allow for effective interfacing between voltage domains supplied by different voltage level.usually conventional level shifter which can shift any voltage level signal to a desired higher level with low leakage current.in this level shifter we used multi VDD design techniques which give more design flexibility for low power system. In this paper we used high voltage tolerant level shifter for power minimization. Many application of this level shifter used in memory card, LCD, TV & mobile phones etc. This circuit is designed in 180nm technology and simulated on Tanner Tool Eda. Keywords: Level shifter, conventional level shifter, high voltage tolerant circuit. 1. INTRODUCTION To achieve high performance and high integration density, the transistor dimensions are aggressively scaled down in ultra deep submicron process while low power dissipation is achieved by scaling down the supply voltage. With the wide applications of battery supplying devices, such as portable PC, cellar phones and PDA, power consumption has become a critical design concern in today s VLSI circuit and system designs. In addition, approximately millions of transistors have been packed into a single chip in nanometer technologies. So the heat dissipation caused by huge power consumption becomes a problem that can adversely affect reliability and packaging cost of a design. These factors have attracted much attention on low power design of CMOS circuits and driven numerous research efforts to address various kinds of power reduction techniques[13]. Multiple supply voltages techniques have been proposed for low power design. With the use of two different supply voltages, it is possible that a low-voltage gate is made to drive a high-voltage one. This leads to the high output of the low-voltage gate cannot fully turn off the PMOS part of the high-voltage gate, so it forms a DC leakage path from the power source to ground. The DC leakage can lead to substantial power loss. To solve this problem, a level shifter is used at the interface of a low-voltage and high-voltage gates. The level shifter is a key circuit component in multi-voltage circuits and has important implementation[15]. For a chip-level DVS system, level shifters are required between core circuits and I/O circuits interface where low voltage logic signals from chip core are shifted to high voltage level at which pad ring is working. Since the level shifter circuit consumes power and has a considerable delay, how to optimize the performance to gain low power and small delay and how to minimize the number of level shifters are important in the voltage scaling technique. In this paper, we study different types of level shifter and also high voltage tolerant circuit Conventional Level Shifter A conventional level shifter where inputs low supply voltage VddL and the output high supply voltage VddH are used. The two pmos transistors p 11 act as a cross-coupled load. Thick gate oxide transistor was used for n 11, n 12, p 11, to overcome high voltage stress. Assuming that when the input signals (in) is at vss, n 11 turns O N turns O FF. Because of the positive feedback action of cross-coupled p 11, node T 1 is pulled down to vss and node T 2 goes to V ddh. No leakage current path exists between V ddh and vss. Similarly, the operation reverses if input signal (in) switches to V ddl, the following procedure is take place. N 11 turns O FF turns O N. N 11 pulls down

2 160 International Journal of VLSI Design T 1 to V ddh and T 2 goes to vss. Finally the transition time from low voltage to high voltage is decided by the current driving capability of p 11. Pull down nmos has to overcome the pmos latch action before the output change state, so the size of n 11 are much larger than p 11 [11] the feedback transistor p4 turns O N so that charges node v to VddH to compensate the threshold drop. Hence the supply voltage of inverter ( p 2 -n 2 ) is dynamically switched between V ddh -v tn and V ddh depending upon the input state.[11] Figure 1: Conventional Level Shifter The convention level shifter has two disadvantages in actual implementation. First, because of the thick gate oxide transistor s ( n 11, n 12 ) high threshold voltage, it can not operate at the core voltage V ddl under 1 V. Second, current driving capability of n 11 are decided by core voltage V ddl, but those of p 11 are controlled by the I/O voltage V ddh. So when I/O voltage V ddh changes, it will make different current driving capability result in delay variation in level shifter. Therefore, it is not adequate for wide range voltage application in a given core voltage Single Supply Level Shifter The needs for two voltage supply limit the physical placement of such level shifter to the boundary of high and low voltage designs which restricts the physical design flexibility. To address this, a novel level shifter which requires only one supply V ddh to convert the low Voltage signal to the higher voltage has been proposed. It makes the placement much more flexible in the entire high voltage regions. Figure 2 shows the schematic diagram of single supply level shifter. The threshold drop (vtn) across the nmos n 1 provides a virtual V ddl to the input inverter ( p 2, n 2 ). The output stage is a half latch which pulls up the input of the inverter ( p 3, n 3 ) to V ddh in order to avoid leakage. When input signal (in) is HIGH, the voltage at node v is (V ddh -vtn) with the purpose of reducing gate to source voltage of p 2 to turn it OFF. When the input signal (in) is LOW, Figure 2: Single Supply Level Shifter The biggest advantage of this level shifter is its flexible placement which enables efficient physical design of voltage islands. But, the single supply level shifter can suffer from higher leakage currents if input signal supply level is lower or lower or VddH is higher than input supply level by more than vtn. So it is limited with wide range of input and output supplies. Also the diode connected transistor n 1 limits the operating speed of the circuit High Voltage Tolerant Circuit using Conventional Level Shifter Level A low to high voltage level shifter is required along with the some mechanism of preventing the MOSFET leakages. A high voltage tolerant level shifter is one of the configurations which solve these issues. The main approach used in this work is a high voltage tolerant level shifter[27] On-chip voltage converters are becoming increasingly important for ultra-low voltage nanoscale memories. They include the reference voltage generator, the voltage down-converters, the voltage up-converter and negative voltage generator with charge pump circuits, and level shifters to adjust resultant voltage differences between internal blocks and between the internal core and I/O circuits. In the past, DRAMs and flash memories have required such voltage converters to ensure stable operations and retention characteristics of memory cells, and they will continue to need such converters. Even

3 A Low to High Voltage Tolerant Level Shifter for Power Minimization 161 future SRAM cells may need such converters for ensuring low sub threshold current and stable operation,. For example, the raised voltage necessary for such memory cells must be kept high, independent of device scaling, to ensure data-retention characteristics, although the operating voltage for peripheral logic circuits can be scaled down with device scaling. Consequently, the voltage difference between memory cells and peripheral circuits will grow with device scaling. In addition, interface circuits of chips must operate at quite a high external voltage, although some internal circuits using scaled devices can operate at another low external voltage. Moreover, in the near future, even some logic gates will have to operate at high voltages using raised (boosted) supply voltages and/or negative supply voltages, to manage sub threshold currents. These circumstances unavoidably call for stress voltageimmune circuits for the memory cell and its related circuits, interface-related circuits, and sub threshold-current sensitive circuits. In this paper we discuss the high-voltage tolerant circuit techniques for such circuits with using of conventional level shifter and single supply levels shifter[8] field, and punch through. Thus, releasing the stress-voltage is indispensable for MOSTs in circuits operating at high stress voltages. The following circuit techniques are proposed for the above problems. This circuit has a protection device only for an NMOST because of the above reasons. Here, MN2 is the protection device. The series connection of two NMOSTs halves the drain- source voltage of each NMOST and reduces hot-carrier injection. Figure 4: High Tolerant with Single Supply Level Shifter A level shifter circuit using the high-voltage tolerant technique this circuit converts the input signal with a voltage swing of V DD1 into the output signal with a larger swing of V DD2. This circuit consists of two sets of the inverters shown in Fig. 3 The PMOSTs M P1 and M P3 are cross-coupled, while NMOSTs M N1 and M N3 receive complementary input signals. The differences include that thick gate-oxide MOSTs are used except for the input NMOSTs M N1, M N3 and that the gates of M P2, M P4, M N2 and M N4 are supplied with the input signal instead of dc voltage. 2. SIMULATION RESULTS A logic swinging between 1.8V and 0 is applied at input signal (in) and the level shifted signals swinging between 3.6V and 0 are obtained at output signal (out).at the end of the paper comparing all level shifter. 3. SIMULATION RESULTS PRM CLS CMLS HTCLS HTSLS Figure 3: High Voltage Tolerant Circuit Device scaling causes the reliability problem, such as device-parameter degradation due to hot carrier, breakdown of gate oxide due to high electric Power 10mW 7mW 2.0mW 1.3mW Current 2.5mA 1.5mA 600uA 500uA Rise time 5.32ns ps 2.0ns 2.57ns Fall time 115ps ps 2.67ns ps Delay 45.44ps 5.74ps 4.52ns 5.2ns

4 162 International Journal of VLSI Design 4. CONCLUSION AND FUTURE WORK In this paper, several level shifters have been evaluated to traditional CMOS levels. One single supply circuit with high voltage tolerant circuit was included in the evaluation as well as three level shifters discussed in this paper. All these circuits were evaluated in terms of power and speed performance. Simulation results show proper shifting of a lower supply logic signal to higher supply logic without consuming any steady state current. Low power techniques such as VTCMOS and MTCMOS can be used to minimize power dissipation the future scope of this project.so, we can use some other techniques to reduce leakage, for example-multiple threshold CMOS technique, variable threshold CMOS technique. New circuit families which are more efficient and power saving can also be used to reduce the power. The configuration used in this thesis can be implemented and analyzed at nanometer technology nodes such as 130nm, 90nm REFERENCES [1] Sven Lutkemeier and Ulrich Ruckert, A Sub Threshold to Above Threshold Level Shifter Comprising Wilson Current Mirror, in Proc. IEEE Transaction on Circuit and System, 57, No. 9, Sep [2] Jianhua Ying, Fenghu Wang, Chuan Ding, An Improved Negative Level Shifter for High Speed ana Low Application, in Proc. IEEE Transaction on Circuit and System, pp. 1-5 Jun [3] Yan -Mang Li, Chang-Bao and Bing Yuan, A High Speed and Power Efficient Level Shifter for Shifter for High Voltage Buck Converter Driver, in Proc IEEE, Aug [4] Philippe O. Pouloquen, A Ratioless and Biasless Static CMOS Level Shifter, in Proc in IEEE, Aug [5] A Hasanbegovic and S. Auneet, Low Power Sub Threshold to Above Threshold Level Shifter in 90nnm Process, in Proc. NORCHIP Conf, pp. 1-4, Nov [6] S Maruyama, K Takahashi, H Fujita, A Mems Digital Mirror Array Integrated with High Voltage Level Shifter, in Proc in IEEE [7] A. Chavan and E. MacDonald, Ultra Low Voltage Level Shifters to Interface Sub and Upper Threshold Reconfigurable Logic Cells, in Proc. IEEE Aerosp. Conf, 8, pp. 1-6, Mar [8] J. Rocha, M. Santos, J. M. Dores Costa, and F. Lima, High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies, in Proc. IEEE Int. Symp. Ind. Electron, pp , Jun [9] T-H. Chen, J Chen and L.t. Clark, Sub Threshold to Above Threshold Level Shifter, J. Low Power Electronics, 2, No. 2, pp , Aug [10] E J. Mentze, H.L Hess, K.M. Buck and D.F Cox, Low Voltage to High Voltage Level Shifter and Related Methods, U.S Pantent, Sep [11] Bo Zhang, Liping Liang, A New Level Shifter with Low Power in Multi Voltage System, 19th International Conference on VLSI Design [12] J.C. Garcia, J.A Montiel-Nelson and S Nooshabadi, Bootstrapped Power Efficient CMOS Driver, IEEE Int Conf on Microelectronics, pp , Dec [13] Kyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim, A New Level-up Shifter for High Speed and Wide Range Interface in Ultra Deep Sub-Micron, IEEE International Symposium, pp , May [14] C. Q. Tran, H. Kawaguchi, and T. Sakurai, Low- Power High-Speed Level Shifter Design for Block- Level Dynamic Voltage Scaling Environment, International. Conference. on Integrated. Circuit, pp , May [15] Kyoung-Hoi Koo; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim; A New Level-up Shifter for High Speed and Wide Range Interface in Ultra Deep Sub-Micron, IEEE International Symposium on Circuits and Systems, 2, pp , May [16] C Q.Tran, Hiroshi Kawaguchi and Takayasu Sakurai, Low-Power High-Speed Level Shifter Design Dynamic Voltage Scaling Environment in Proc. International Conference on Integrated Circuit Design and Technology, pp , May [17] Abdulkadir Utku Diril, Yuvraj Singh Dhillion Abhijit Chatterjee and Adit D. Singh, Level -Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuit Using Dual Threshold Voltage IEEE Transaction VlSI, 13, No. 9, Sep [18] Shigeki IMAI, Noboru Nakanishi, Low Power Consumption Level Shifter used Clamping Circuit Technique LTPS Technology for TFT-LCD, IEEE Electronics Letter, [19] S.C Tan and X.W Sun, Low Power CMOS Level Shifters by Bootstrapping Technique, IEEE Electronics Letters, 38, No 16, Aug 2. [20] Liqiong Wei; Roy, K; De, V.K., Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs, VLSI Design Thirteenth International Conference, pp , 3-7, Jan [21] Y. Kanno, H. Mizuno, K.Tanaka and T.Watanave, Level Shifter Converter with High Immunity to Power Supply Bouncing for High-Speed, pp , Jun 2000.

5 A Low to High Voltage Tolerant Level Shifter for Power Minimization 163 [22] J. Doutreloigne, H. De Smet, J. Van Den Steen, G. Van Doorselaer, Low Power High-Voltage CMOS Level-Shifters for Liquid Crystal Display Drivers The Eleventh International Conference on Microelectronics, pp , Nov [23] D.R.H Crater and R.A. McMahon, An Integrated Level Shifter use in High Frequency Half Bridge, IEEE Electronics Letter Sep [24] D.R.H. Carter and R.A.McMahon, Electronic Level Shifter for use in Half-Bridges Operating at 13.56Mhz, IEEE Electronics letter, 31, No. 16, Aug [25] H. Gautier, P.ledu, C.Maerfeld, Low to High Voltage-Level Shifter and Waveform Synthesizer, IEEE Electronics Letter, 15, No. 6, Mar [26] Y. P. Tsividis, Operation and Modeling of the MOS Transistor. [27] Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka, Ultra Low Voltage Nano Scale Memories. [28] [29]