Illumitex. Patent Portfolio Overview. LED Extraction Efficiency & Chip Shaping Technology

Transcription

1 Patent Portfolio Overview Illumitex LED Extraction Efficiency & Chip Shaping Technology Rob Aronoff (415) ext. 101 Mitch Rosenfeld (415) ext. 103 Myron Kassaraba (415) ext California Street, Suite 650, San Francisco, California 94111

2 Opportunity Overview Illumitex was founded in 2005 by imaging and optics industry veterans. The Company s current business is vibrant and focused on LED total solutions including fixtures and optics. The IP being offered for sale is being divested since LED chip manufacturing is a business that is no longer being pursued. The Illumitex chip-level IP incorporates fundamental physics principles to maximize light extraction from the source. By extracting and directing photons at the die level, Illumitex delivers more usable light to the intended target while consuming less energy. This sale represents a unique opportunity for a strategic buyer to acquire lab-tested technology with very solid patent protection in a critical area of the rapidly growing LED market. 2

3 Portfolio Summary Illumitex Assets For Sale 6 issued US patents 1 US provisional application 5 patent families total Foreign equivalents from Europe, China, Japan, Taiwan, and South Korea Forward References from: Hon Hai Precision Industry Co., Ltd. Osram Opto Semiconductors Samsung Electronics No encumbrances Patent Portfolio Details US 7,789,531 (Priority: 10/2/2006) US 7,829,358 (Priority: 2/8/2008) US 8,087,960 (Priority: 10/2/2006) US 8,115,217 (Priority: 12/11/2008) US 8,217,399 (Priority: 8/1/2008) US 8,263,993 (Priority: 2/8/2008) US 61/587,552 (Provisional) Foreign equivalents Market Application and Strategic Opportunity The worldwide LED chips market is expected to reach $8.5 billion by 2014 ( Leading exemplary vendors: Nichia, Samsung, Osram, LG, Seoul Opto, Cree, Philips/Lumileds, Sharp, Toyoda Gosei, Everlight, GE, Micron, BridgeLux, SemiLEDs, Epistar, 3M, Rambus, Panasonic/Matsushita, TSMC, Rohm & Haas, Showa Denko, Toshiba, etc. (Representative market participants. Not an opinion, claim, or representation as to infringement.) 3

4 Sorted by Patent Family (1 of 2) Illumitex s IP Portfolio Pat/Pub Number US 7,829,358 Patent Family A Tech Cluster LED Emitter Layer Shaping Title System and method for emitter layer shaping Priority Date 2/8/2008 US Patent Family Members US 8,263,993 (Divisional) Ex US Patent Family Members EP A1 WO A1 KR A CN A TW A JP A US 8,263,993 A LED Emitter Layer Shaping System and method for emitter layer shaping 2/8/2008 US 7,829,358 (Parent) See 358 Patent US 61/587,552 (Provisional) B LED Micro Mirrors Hybrid mirror for higher extraction efficiency from bottom emitting LEDs 1/17/2012 None None US 7,789,531 US 8,087,960 C C LED Substrate Shaping (Exit Face & Sidewalls) LED Substrate Shaping (Exit Face & Sidewalls) LED system and method 10/2/2006 LED system and method 10/2/2006 US 8,087,960 US A1 (Abandoned) US A1 (Abandoned) US 7,789,531 US A1 (Abandoned) US A1 (Abandoned) EP A2 WO A1 WO A1 WO B1 KR A CN B TW A TW A TW A JP A See 531 Patent 4

5 Sorted by Patent Family (2 of 2) Illumitex s IP Portfolio Pat/Pub Number Patent Family Tech Cluster Title Priority Date US Patent Family Members Ex US Patent Family Members US 8,115,217 D LED Packaging Systems and methods for packaging light emitting diode devices 12/11/2008 None WO A1 TW A US 8,217,399 E LED Emitter & Submount Structure Photon Tunneling Photon tunneling light emitting diodes and methods 8/1/2008 None EP A1 WO A1 KR A CN A TW A JP A 5

6 Comprehensive IP Illumitex s IP includes proprietary technology covering different parts of an LED: Sapphire or SiC Flip-Chip LED Patent Family C LED Substrate Shaping (Exit Face & Sidewalls): US 7,789,531 US 8,087,960 Patent Family D LED Packaging: US 8,115,217 GaN Submount Patent Family B LED Micro- Mirrors: US Prov. 61/587,552 Patent Family E LED Emitter & Submount Structure Photon Tunneling: US 8,217,399 Patent Family A LED Emitter Layer Shaping: US 7,829,358 US 8,263,993 Image Source: Illumitex, Fig. 4 of US 8,115,217. Image Source: Illumitex. 6

7 Technology Overview Light extraction from an LED chip depends on: Minimizing the number of reflections (N) in the LED structure Maximizing reflectivity of all surfaces Minimizing absorption losses of all materials Rough estimate of Losses: Absorption Losses Compound! #Reflections Absorption 1 R Optimized structures does all of this: Sidewall TIR: R = 100% Sidewall shape directs light into escape cone: N = 1 All rays strike exit face and exit! light LED Emitter Lossless reflection at sidewalls 7

8 LED Emitter Layer Shaping US 7,829,358 & US 8,263,993 LED Emitter Layer Shaping (Patent Family A) Shaped emitters achieve highest possible light extraction efficiencies (LEE) Minimize internal reflections Control beam shape into substrate or encapsulant Key Achievements Light extraction improvements up to 50% demonstrated Fabrication process developed Performance matches advanced optical modeling Comparable test data from prototype test wafers available 8

9 LED Micro-Mirrors US Prov. 61/587,552 LED Micro-Mirrors (Patent Family B) Replace conventional Ag mirror with combination of Ag & dielectric mirrors Higher reflectivity = higher extraction efficiency Key Achievements Dielectric stacks can give 99+% reflectance Absorption Losses Compound! #Reflections Absorption 1 R P GaN MQW active n GaN Potential add-on process to improve conventional vertical or flipchip device designs Demonstrated 10-15% higher extraction efficiency than PSS Production-ready Comparative performance data available Ag pcon. TiO2 SiO2 ncontact 9

10 LED Substrate Shaping (Exit Face & Sidewalls) US 7,789,531 & US 8,087,960 LED Substrate Shaping (Patent Family C) Shaped substrates achieve greater efficiency than previous LEDs The height of the substrate can be selected to limit the critical angle of rays incident on the exit surface The exit face has at least 70% of a minimum area needed to conserve radiance for a desired half-angle of light projected from the shaped substrate Key Achievements Theoretical efficiency of up to 89% (89% of the light entering the substrate is emitted in the desired half-angle with 11% Fresnel loss) 10

11 LED Packaging US 8,115,217 LED Packaging (Patent Family D) Improved LED Packaging of Patent Family C achieves overall brightness The size of a packaged LED defines the LED s brightness (lumens) A phospor plate is on top or within the housing The rays of light exit the exit face with negligible side emission through the side walls of the substrate Key Achievements LED does not need secondary optics 11

12 LED Emitter & Submount Structure Photon Tunneling US 8,217,399 Photon Tunneling (Patent Family E) Photon Tunneling increases light that makes it into air Photons do not become trapped in the substrate The LED layer structure has a thickness that is less than the wavelength of the light produced Key Achievements Geometric modification of the GaN and/or substrate is not needed to extract light 12

13 Illumitex In The News 13 Sources (left to right):

14 Applicable Market Representative Market Participants 1 1 Representative market participants. Not an opinion, claim, or representation as to infringement. 14

15 Market Trends Illumitex IP Applies to Two Large Related Growing Markets Packaged LED Market: The worldwide packaged LED market (does not include LED chips) grew nearly 10% from $11 billion in 2010 to $12.5 billion in 2011 (the packaged LED market sorted by commercial application is shown on the immediate right) Chip LED Market: The worldwide LED chips market was roughly $3 billion in 2009 and is estimated to grow to $8.5 billion by 2014 (see lower right) this is the applicable market for Illumitex s IP Worldwide Chip LED Market (in $ mil) $9,000 $8,000 $7,000 $6,000 $5,000 $4,000 $3,000 $2,000 $1,000 $ Source: LEDs Magazine, and 15

16 Patent Landscape Analysis The following four slides represent analysis performed on patents in the LED technology space to illustrate the relationship of the Illumitex IP to those of major market participants. Methodology Pluritas first performed keyword and semantic searches to identify top relevant vendors within the Illumitex IP space as illustrated in Slide 17. Pluritas then worked with IP Checkups, a research firm that provides technical analysis, to graphically map the patent landscape of top vendors by tech area as illustrated in Slide 18. Next, by accessing IP Checkups LED database, Pluritas identified the vendors with gaps as illustrated in Slide 19 as these companies could find this Illumitex IP useful in enhancing their patent portfolios. 16

17 Patent Landscape Leading LED Vendors 1 1 Representative market participants. Not an opinion, claim, or representation as to infringement. Pluritas performed keyword and semantic searches to identify top vendors with patents relevant to Illumitex s IP. Using this data and collaborating with IP Checkups, the following pie chart was built illustrating the leading patent holders: Efficient LED Technology: Patent Landscape (United States) Showa Denko 5% Seoul Opto 3% SemiLEDs 1% Sharp 10% Toshiba 10% Samsung 11% Toyoda Gosei 5% Rohm & Haas 4% 3M Acuity 1% 0% Cree 6% Philips/Lumileds 9% BridgeLux 1% Epistar 2% Panasonic 11% Everlight 1% GE 2% Goldeneye 0% LG 8% Nichia 4% Osram 5% Illumitex 3M Acuity BridgeLux Cree Epistar Everlight GE Goldeneye LG Nichia Osram Panasonic Philips/Lumileds Rohm & Haas Samsung SemiLEDs Sharp Seoul Opto Showa Denko Toshiba Toyoda Gosei 17 Source: 7,494 patents from IP Checkups LED Database.

18 Patent Landscape Tech Breakdown 1 1 Representative market participants. Not an opinion, claim, or representation as to infringement. The LED IP landscape for 10 Assignees is mapped by tech area below. Philips/Lumileds and LG have IP similar to the 993, 358, 960, and 531 Illumitex patents. Cree, LG, and Panasonic have IP similar to the 217 and 399 Illumitex patents. Patent Family A US 8,263,993 US 7,829,358 Patent Family C US 8,087,960 US 7,789,531 Note: In the patent map, patents (dots) are clustered based on thematic similarity. Dense areas of similar patents, are represented as snow-capped peaks, while relatively sparse areas are represented as blue lakes or oceans. The absolute positioning of each peak and valley is not important, only relative location the closer together the peaks are located on the map, the more closely the corresponding patents are related. Patent Family D US 8,115,217 Patent Family E US 8,217, Source: IP Checkups LED Database.

19 Patent Landscape Tech Breakdown 1 1 Representative market participants. Not an opinion, claim, or representation as to infringement. The table below illustrates Illumitex s IP alongside the leading LED vendors (sorted by tech area). Cells highlighted in yellow indicate areas where vendors have fewer than 20 patents in a relevant Illumitex tech area. For example, Nichia, Sharp, Toyoda Gosei, Everlight, GE, Acuity, BridgeLux, SemiLEDs, Epistar, 3M, Goldeneye, and Rohm & Haas fewer patents than their competitors in areas relevant to the Illumitex patents. Within LED Space From IP Checkups (PatentCam) Pats Pubs Pats Pubs Pats Pubs Pats Pubs Solid State Lighting > LED Solid State Lighting > LED Solid State Lighting > LED Company US Pats US Pubs Total Control > Power Technology > Chemistry & Technology > Chemistry & Solid State Lighting > Fixtures Management > Distribution Materials > Epitaxy Materials > Substrates Illumitex Nichia Samsung Osram LG Seoul Opto Cree Philips/Lumileds Sharp Toyoda Gosei Everlight GE Acuity BridgeLux SemiLEDs Epistar M Goldeneye Panasonic/Matsushita Rohm & Haas Showa Denko Toshiba Total Source: 8,809 patents and 7,964 applications from IP Checkups LED Database.

20 Patent Landscape Conclusion Conclusion 1 Philips/Lumileds and LG have IP similar to Illumitex Patent Families A and C. Cree, LG, and Panasonic have IP similar to the Illumitex Patent Familities D and E. Nichia, Sharp, Toyoda Gosei, Everlight, GE, Acuity, BridgeLux, SemiLEDs, Epistar, 3M, Goldeneye, and Rohm & Haas fewer patents than their competitors in areas relevant to the Illumitex patents. 1 Representative market participants. Not an opinion, claim, or representation as to infringement. 20

21 Transaction Parameters and Objectives Illumitex is seeking the sale of these assets No Encumbrances Seller requires a Grant Back license The identity of all inquiries and bidders is confidential except as modified by a transaction between the parties 21

22 Diligence Resources Available Technical and IP Diligence calls are available with Pluritas experts who have completed reviews of the IP assets and are knowledgeable about the markets to which they apply 22

23 For More Information For more information and/or execution of an inquiry- and identity-protecting NDA, please contact: Rob Aronoff Managing Partner (415) x101 Mitch Rosenfeld Partner (415) x103 Myron Kassaraba Partner (415) x104 Craig Carothers General Counsel (415) x102 23

24 Pluritas Profile Pluritas is a transaction advisory firm specializing in divestitures, acquisitions, and mergers where Intellectual Property (IP) is a major component of the transaction. We provide arms-length sell side transaction services to all owners of IP assets. We provide arms-length buy side transaction services to a select group of Corporate Clients. We expertly navigate the risks and nuances for all parties involved with transacting IP, yielding a 'safer' and more comfortable transaction climate for all participants. We also strongly differentiate ourselves by our track record of success, as well as by integrating seasoned professionals with deep industry, technical and IP expertise into every engagement. 24

25 NOTICE THIS PRESENTATION DOES NOT CONSTITUTE AN OFFER FOR SALE OF ASSETS OR SECURITIES FOR ILLUMITEX OR AN OFFER FOR, OR SOLICITATION OF, A LICENSE OF ANY KIND. IN MAKING A DECISION REGARDING THE ILLUMITEX OPPORTUNITY, POTENTIAL PURCHASERS MUST RELY ON THEIR OWN EXAMINATION OF THE INTELLECTUAL PROPERTY RIGHTS AND OTHER ASSETS INCLUDING BUT NOT LIMITED TO THE TITLE, VALUE, MERITS AND RISKS INVOLVED. THERE IS NO ASSURANCE THAT THESE INTELLECTUAL PROPERTY RIGHTS WILL BE UPHELD. PLURITAS MAKES NO REPRESENTATION CONCERNING THE VALIDITY OF THE INTELLECTUAL PROPERTY HEREIN. ADDITIONALLY, THESE MATERIALS ARE SOLELY ATTRIBUTABLE TO PLURITAS AND DO NOT NECESSARILY REPRESENT THE VIEWS OR OPINIONS OF ILLUMITEX. NOTHING IN THIS DOCUMENT SHALL CONSTITUTE OR BE INTERPRETED AS LEGAL ANALYSIS REGARDING THE SCOPE OF THE PATENTS OR OTHER INTELLECTUAL PROPERTY RIGHTS. SIMILARLY, NOTHING INCLUDED IN THIS DOCUMENT SHALL BE USED TO INTERPRET, DEFINE, OR OTHERWISE LIMIT THE SCOPE AFFORDED THE ASSOCIATED INTELLECTUAL PROPERTY RIGHTS. 25

26 Appendix: Exemplary Claims 26

27 U.S. Patent No. 7,789,531 Representative Claim Representative Claim 531 Patent, Claim 1 An LED comprising: a quantum well region operable to generate light; and a shaped substrate having an interface to receive light generated by the quantum well region, wherein light generated by the quantum well region traverses the interface, the shaped substrate comprising: an exit face opposite from and a distance from the interface, wherein the substrate is shaped so that a portion of the light entering the shaped substrate through the interface will exit the shaped substrate through the exit face and wherein the exit face has at least 70% of a minimum area necessary to conserve radiance for a desired half-angle of light projected from the shaped substrate; and a set of sidewalls, wherein each sidewall is positioned and shaped so that at least a majority of rays having a straight transmission path from the interface to that sidewall can reflect through total internal reflection to the exit face with an angle of incidence at the exit face at less than or equal to a critical angle at the exit face. 27

28 U.S. Patent No. 7,829,358 Representative Claim Representative Claim 358 Patent, Claim 1 A method of shaping an emitter layer of the LED, comprising: determining an exit area (b) and an emitter area (a) of a miniature emitter, wherein the exit area (b) has an exit face in a first geometric configuration and wherein the emitter area (a) has a quantum well region in a second geometric configuration; determining a minimum height (h) of the miniature emitter utilizing the exit area (b) and the emitter area (a); removing matter from an emitting material or growing the emitting material according to the first geometric configuration, the second geometric configuration, and the minimum height (h) to form a shaped portion having one or more miniature emitters meeting the minimum height (h); and shaping sidewalls of the miniature emitters, wherein each sidewall is positioned and shaped to cause at least a majority of rays having a straight transmission path from the emitter area to that sidewall to reflect to the exit face with an angle of incidence at the exit face at less than or equal to a critical angle at the exit face. 28

29 U.S. Patent No. 8,087,960 Representative Claim Representative Claim 960 Patent, Claim 11 A method of shaping an LED comprising: providing a wafer comprising a substrate and one or more layers for a quantum well region of the LED; grinding the substrate to form a shaped substrate portion of the LED; wherein the shaped substrate portion is shaped to comprise: an exit face opposite from and a distance from an interface with the to receive light generated by a quantum well region of the LED, the exit face having a size being at least 70% of a minimum area necessary to conserve radiance for a desired half-angle of light projected from the shaped substrate; and a set of sidewalls, wherein each sidewall is positioned and shaped so that at least a majority of rays having a straight transmission path from the interface to that sidewall reflect through total internal reflection to the exit face with an angle of incidence at the exit face of less than or equal to a critical angle at the exit face; wherein the method is performed by performing steps in the order of: (a) determining boundary conditions for the shaped substrate portion of the LED, wherein the boundary conditions comprise the size of the exit face of the shaped substrate portion of the LED and the distance between the exit face and the interface between the shaped substrate portion and the quantum well region of the LED; (b) determining the shapes and positions of the set of sidewalls of the shaped substrate portion of the LED; and (c) shaping the shaped substrate portion of the LED. 29

30 U.S. Patent No. 8,115,217 Representative Claim Representative Claim 217 Patent, Claim 1 A packaged light-emitting diode (LED) device, comprising: a housing having a cavity; a phosphor plate on top or within the housing; a submount attached to the housing, wherein the submount comprises metal traces, vias, or a combination thereof; and at least one LED chip residing in the cavity of the housing between the phosphor plate and the submount and comprising a substrate and a light emitting region, wherein the substrate comprises a side wall and an exit face on top of the side wall, wherein all or substantially all rays of light emitting from the light emitting region exit the exit face with negligible or substantially negligible side emission through the side wall of the substrate, and wherein the light emitting region is connected to the metal traces of the submount inside the housing through an electrically conductive contact area. 30

31 U.S. Patent No. 8,217,399 Representative Claim Representative Claim 399 Patent, Claim 1 A light-emitting diode (LED) device comprising: an LED layer structure comprising a quantum well layer adapted to generate light having a wavelength, a p-doped alloy layer on a first side of the quantum well layer, an n- doped alloy layer on a second side of the quantum well layer obverse from the first side and between the quantum well layer and a medium; an electrode electrically connected to the p-doped alloy layer; and an electrode electrically connected to the n-doped alloy layer; wherein the combined thickness of the LED layer structure on the second side of the quantum well layer including the n-doped alloy layer is thinner than the wavelength of light that the quantum well layer is adapted to generate to allow light generated by the quantum well layer to photon tunnel to the medium. 31

32 U.S. Patent No. 8,263,993 Representative Claim Representative Claim 993 Patent, Claim 1 An LED, comprising: a base substrate; and an emitter layer on a surface of the substrate configured to emit light in an emission half angle, wherein the emitter layer has a shaped portion comprising: an emitter area; an exit area a height from the emitter area; sidewalls running from the emitter area to the exit area, wherein each of the sidewalls comprises a plurality of areas at different angles relative to the emitter area and wherein each sidewall is positioned and shaped to cause at least a majority of rays having a straight transmission path from the emitter area to that sidewall to reflect to the exit area with an angle of incidence at the exit area at less than or equal to a critical angle at an emitter layer to substrate boundary; and wherein the size of the exit area and shapes of the sidewalls are configured so that at least 60% of the light generated in the emitter layer exits the emitter layer into the substrate in the emission half angle. 32