efficient operation at 100kHz, although other inductors and other frequencies may be easily used. Figure 1. Half-bridge evaluation board

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1 User Guide TDHBG500P00:.5kW Half-bridge Evaluation Board Introduction The TDHBG500P00 half-bridge evaluation board provides the elements of a simple buck or boost converter for basic study of switching characteristics and efficiency achievable with Transphorm s 650V GaN FETs. In either buck or boost mode the circuit can be configured for synchronous rectification. Jumpers allow use of a single logic input or separate hi/lo inputs. The highvoltage input and output can operate at up to 400Vdc, with a power output of up to.5kw. The inductor provided is intended for efficient operation at 00kHz, although other inductors and other frequencies may be easily used. Figure. Half-bridge evaluation board February, 07 evk Transphorm Inc. Subject to change without notice.

2 TDHBG500P00 User Guide TDHGB500P00 input/output specifications High-voltage input/output: 400Vdc max Auxiliary supply (J): 0V min, 8V max Logic inputs: nominal 0V-5V Pulse-generation circuit: Vlo <.5V, Vhi > 3.0V Direct connection to gate driver: Vlo < 0.8V, Vhi >.0V SMA coaxial connectors Switching frequency: configuration-dependent Lower limit determined by peak inductor current Upper limit determined by desired dead-time and power dissipation Power dissipation in the GaN FET is limited by the maximum junction temperature. Refer to the TPH3PS datasheet. Circuit description The circuit comprises a simple half-bridge featuring two TPH3PS GaN FETs, as indicated in the block diagram of Figure. Two high-voltage ports are provided which can serve as either input or output, depending on the configuration boost or buck. In either case one FET acts as the active power switch while the other carries the freewheeling current. The latter device may be enhanced, as a synchronous rectifier, or not. With GaN FETs the reverse recovery charge is low and there is no need for additional freewheeling diodes. Two input connectors are provided which can be connected to sources of logic-level command signals for the hi/lo gate driver. Both inputs may be driven by off-board signal sources; or alternatively, a single signal source may be connected to an on-board pulse-generator circuit which generates the two non-overlapping pulses. Jumpers determine how the input signals are used. An inductor is provided as a starting point for investigation. This is a 440µH toroid intended to demonstrate a reasonable compromise between size and efficiency for power up to.5kw at a switching frequency of 00kHz. February, 07 evk005.

3 TDHBG500P00 User Guide TPH3PS TPH3PS Figure. Functional block diagram Using the board The board can be used for evaluation of basic switching functionality in a variety of circuit configurations. It is not a complete circuit, but rather a building block. It can be used in steady-state DC/DC converter mode with output power up to.5kw. Configurations Figure 3 shows the basic power connections for buck and boost modes. For buck mode, the HVdc input (terminals J, J3) is connected to the high-voltage supply and the output is taken from terminals J5 and J7. For boost mode, the connections are reversed. Note that in boost mode a load must be connected. The load current affects the output voltage up to the transition from DCM to CCM. In buck mode the load may be an open circuit. TPH3PS TPH3PS (a) Buck mode February, 07 evk005. 3

4 TDHBG500P00 User Guide TPH3PS TPH3PS (b) Boost mode Figure 3. Supply and load connections for buck (a) and boost (b) configurations Figure 4 shows possible configurations for the gate-drive signals. In Figure 4(a), a single input from an external signal source is used together with the on-board pulse generation circuit. J4 is used, J6 is left open circuit. Jumpers JP and JP are in the top position, as shown. If the high-side transistor is to be the active switch (e.g. buck mode), then the duty cycle of the input source should simply be set to the desired duty cycle (D). If the low-side transistor is to be the active switch (e.g. boost mode) the duty cycle of the input source should be set to (-D), where D is the desired duty cycle of the low-side switch. This configuration results in synchronous rectification. If it is desired to let the device carrying the freewheeling current act as a diode, then the appropriate jumper should be placed so that the pull-down resistor is connected to the driver. Figure 4(b) shows a buck-mode configuration where the low-side device is not enhanced. Finally, Figure 4(c) shows use of two external signal sources as inputs to the gate driver. For any configuration, an auxiliary supply voltage of 0V-8V must be supplied at connector J. Pull-down resistors R5 and R6 have a value of 4.99k. If a 50Ω signal source is used and 50Ω termination is desired, then R5 and R6 may be replaced (or paralleled) with 06 size 50Ω resistors. Boost mode/buck mode operation For buck mode operation, with input voltage of 400V and output voltage of 48V; 50A max output current is achievable at 500W with duty cycle of %. A typical 400Vin - 00Vout buck operation with 50% duty cycle, 6.5A max output current is seen at 500W. On the other hand, for 00Vin - 400Vout boost mode operation at.5kw,.5a max output current can be reached with a duty cycle of 50%. Thermal cooling must be enforced for high current switching at all times. February, 07 evk005. 4

5 TDHBG500P00 User Guide TPH3PS TPH3PS (a) TPH3PS TPH3PS (b) TPH3PS TPH3PS (c) Figure 4. Input configurations (a) using a single source for either buck or boost mode (b) buck mode without synchronous rectification (c) using two signal sources February, 07 evk005. 5

6 TDHBG500P00 User Guide Dead time control The required form of the gate-drive signals is shown in Figure 5. The times marked A are the dead times when neither transistor is driven on. The dead time must be greater than zero to avoid shoot-through currents. The Si830BB gate drive chip ensures a minimum dead time based on the value of resistor R7, connected to the DT input. The dead time in ns is equal to the resistance in kω x 0, so the default value of k corresponds to 0ns. This will add to any dead time already present in the input signals. The on-board pulse generator circuit; for example, creates dead times of about 60ns. The resulting dead time at the gate pins of Q and Q is about 40ns. Either shorting or removing R7 will reduce the dead time to 60ns. Figure 5. Non-overlapping gate pulses Design details See Figure 6 for a detailed circuit schematic and Figure 7 for the PCB layers (also included in the design files). The parts list can be found in Table. Table. TDHBpG500P00 half-bridge evaluation board bill of materials (BOM) Designator Qty U3 D, D4, D5 FB, FB FB3, FB4, FB5, FB6 JP, JP J, J3, J5, J7 LED, LED, LED3 U 3 J LDS, LGS C7 C0, C, C, C4, C0, C, C C8, C6, C7 R5 R9, R R4 R4 C9, C3 R3 R7, R C3, C5 R8, R0 Description Package Part Number Manufacturer 74LVCG7DBV SOT3-5 SN74LVCG7DBVR DIODE-DO-4AC FB0603 FB0805 DO-4AC ESJ MMZ608S30ATA00 BLMSN300SZD Texas Instruments Fairchild TDK Murata 4 JPE KEYSTONE_769 JP KEYSTONE_ HLF 769 FCI Keystone 3 LEDCHIP-LED0805 CHIP-LED0805 SML-UTT86 Rohm LT308 SOT3-3 LT308EST#PBF 7 0.µF 0.µF PJ-00AH TEKTRONIX-PCB C-EUC8 C-USC0603 PJ-00AH TEKTRONIX-PCB C8 C0603 PJ-00AH C8V04KDRACTU 06033C04JATA Linear Technology CUI Tektronix Kemet AVX 3 0.µF C-USC5K C5K VJ5Y04KXGAT Vishay 0Ω 0Ω 0Ω 00kΩ 00pF 0MΩ 0kΩ 0µF kω R-US_R0603 R-US_R06 R-US_R0805 R-US_R0603 C-USC0603 R-US_R06 R-US_R0603 C-EUC0805 R-US_R0603 R0603 R06 R0805 R0603 C0603 R06 R0603 C0805 R0603 RC0603FR-070RL ERJ-8GEY0R00V ERJ-P06J00V ESR03EZPJ A0FATA HVC06T005JET ERJ-3GEYJ03V C0805C06M4PACTU RC0603FR-07KL Yageo Panasonic Panasonic Rohm AVX Stackpole Panasonic Kemet Yageo February, 07 evk005. Value 300Ω 30Ω 6

7 TDHBG500P00 User Guide Designator Qty Value Description Package Part Number Manufacturer C C3 C R3 C4, C5, C6, C4 R, R5, R6 R7, R8, R9, R0, R, R R C9, C8 U4, U5 4 µf.µf µf kω 4.7nF C-EUC0805 C-EUC0805 C-USC06 R-US_R0805 C-EUC06 C0805 C0805 C06 R0805 C06 CC0805ZRY5V8BB05 C0X5RE5K5AC CL3A6MOCLNNC RC0805FR-07KL C06C47KDRACTU Yageo TDK Samsung Yageo Kemet kΩ 560kΩ R-US_R06 R-US_R0805 R06 R0805 RMCF06FT4K99 ESR0EZPJ564 Stackpole Rohm 499kΩ 0µH R-US_R06 0uH 74AHCG86DBV R06 EPCOS_B3674 SOT3-5 RMCF06FT499K B3794D06K SN74AHCG86DBVR D, D3 J4, J6 BAT54 BU-SMA-G SOT3 BU-SMA-G BAT54W U$3 HS CWS-MP-640 C0-050-AE Stackpole Epcos Texas Instruments NXP TE Connectivity CWS Ohmite U Q, Q SI830BB-D-IS TPH3PS SP SiLabs Transphorm Bergquist TRG0R0-E03Level-VI SJ6A Keystone Keystone Cincon 4 February, 07 evk µH 7mΩ V Inductor HEATSINKC0-050AE SI830 TPH_TO0VERT_TRI Thermal pad between TPH3 and heatsink 4-40 screw Nylon washer shoulder Adaptor Bumper cylin 0.3" dia blk SOIC6N TO-0 3M 7

8 TDHBG500P00 User Guide Figure 6. Detailed circuit schematic February, 07 evk005. 8

9 TDHBG500P00 User Guide (a) PCB top layer (b) PCB bottom layer February, 07 evk005. 9

10 TDHBG500P00 User Guide (c) PCB inner layer (ground plane) + inner layer 3 (power plane) Figure 7. PCB layers Probing Plated through-holes labeled test points (LGS and LDS) are provided for probing the low-side gate pulse and half-bridge switching node waveform. In order to minimize inductance during measurement, the tip and the ground of the probe should be directly attached to the sensing points to minimize the sensing loop. For safe, reliable and accurate measurement, a scope probe tip may be directly soldered to the low-side FET drain and a short ground wire soldered to the low-side FET source. See Figure 8 for an alternative that does not require soldering the probe tip. WARNINGS: There is no specific protection against over-current or over-voltage on this board. If the on-board pulse generation circuit is used in boost mode, a zero input corresponds to 00% duty cycle for the active lowside switch. February, 07 evk005. 0

11 TDHBG500P00 User Guide Figure 8. Low-inductance probing of fast, high-voltage signals Efficiency has been measured for this circuit in boost mode with 00Vdc in and 400Vdc out, switching at 50kHz and 00kHz (Figure 9). Figure 9. Efficiency for a boost 00V:400V converter February, 07 evk005.