Efficient Encoders and Decoders for Polar Codes: Algorithms and Implementations

Transcription

1 Efficient Encoders and Decoders for Polar Codes: Algorithms and Implementations Gabi Sarkis Department of Electrical and Computer Engineering McGill University Montreal, Canada April 2016 A thesis submitted to McGill University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Gabi Sarkis

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3 iii Acknowledgments First and foremost, I am grateful to my supervisor Prof. Warren J. Gross for his continued guidance, encouragement, and support. His vision enabled me to work today on the problems of tomorrow and led to this exciting adventure. I would like to thank my Ph.D. advisory committee members, Prof. Michael Rabbat and Prof. Ioannis Psaromiligkos, for guiding my research and taking the time to ensure that my work remained on track. I wish to thank Prof. Alexander Vardy for inviting me to visit the University of California San Diego. The discussions we had helped significantly advance my learning. During my stay, I also met Prof. Ido Tal, to whom I am grateful for his many insights, fruitful discussions, and the software to construct polar codes. He also developed a proof of correctness for the systematic encoder that is more general than one presented in Chapter 5. For their financial support of this work, I would like to acknowledge the Natural Sciences and Engineering Research Council of Canada (NSERC) and McGill University. This work would have been incredibly more difficult without the help of my friend Pascal Giard. His discussions, hardware design and verification skills, and bug-hunting abilities have been of immense help. Marwan Kanaan, François Leduc-Primeau, Bojan Mihajlović, Alexandre Raymond, Dora Malterre, Erin Moores, and Carlo Condo, I would like to thank for the discussions inside and outside the lab and for the many years of friendship, adventures, and advice. I have been fortunate to receive advice and help from current and former members of Prof. Gross s group: Prof. Saied Hemati, Prof. Camille Leroux, Saeed Sharifi-Tehrani, and many others. Finally, this would not have been possible without the love of my family. The Chahines and Bannas have supported and encouraged me during these many years. I would like to thank my parents, Farid and Ahed, and my brother, Dani, for their unconditional love and support. To my wife, Nicole, I will forever be grateful. Her patience, love, and encouragement saw me safely and successfully through this journey.

4 iv Abstract Error-correcting codes enable reliable and efficient data communication and storage and have become an indispensable part of information processing systems. Polar codes are the latest discovery in the quest for more powerful error correction. They are the first codes with an explicit construction to provably achieve the symmetric capacity of memoryless channels. Moreover, this performance is realizable using the low complexity successive-cancellation decoding algorithm. Despite their attractive theoretical properties, polar codes suffer from two major issues hindering practical implementations: a slow decoding algorithm and mediocre error-correction performance at moderate code lengths. Solutions to these problems in the literature have been mutually exclusive. Decoding speed can be increased, but at the cost of degrading error-correction capability. On the other hand, the error-correction performance can be greatly improved using a list decoding algorithm, which incurs a large cost in both decoding speed and memory requirements. This incompatibility in solutions must be resolved before polar codes become practical. This thesis presents novel, compatible solutions to these problems. It introduces a new decoding algorithm that has the same error-correction performance as successive cancellation, but offers significantly lower latency and higher throughput. A corresponding decoder implementation is shown to be an order of magnitude faster than the state-of-the-art in the literature. Next, the speed of successive-cancellation list decoders for polar codes is improved without degrading error-correction performance. The resulting software decoders implementing the proposed algorithm offer throughput and error-correction performance exceeding the best in the literature and meeting the requirements for the n WiFi standard. This work also brings to light another beneficial property of polar codes that had not been studied before. It presents encoders and decoders that can operate on polar codes of any length and rate, while maintaining low implementation complexity and fast operating speed. Such implementations are important in systems that must adapt to varying channel conditions. Finally, two methods are introduced that improve error-correction performance without incurring the memory overhead of list decoding. The first targets systems where re-transmission is impossible or highly undesirable. The second improves the performance of software decoders using polar codes with rates very close to the channel capacity.

5 v Abrégé Les codes correcteurs d erreurs permettent la transmission et le stockage de données de façon efficace et fiable. Ils sont devenus indispensables aux systèmes de traitement de l information. Les codes polaires sont la plus récente innovation dans la quête de codes plus puissants et sont les premiers codes dotés d une construction explicite pouvant atteindre la capacité symétrique d un canal sans mémoire. De plus, ils peuvent atteindre cette performance grâce à un algorithme de décodage à faible complexité appelé «annulation successive». Malgré leurs propriétés théoriques intéressantes, les codes polaires souffrent de deux problèmes majeurs qui entravent leur implémentation : un algorithme de décodage lent et une performance méiocre de correction d erreurs à des longueurs de codes modérées. Leur vitesse de décodage peut être augmentée en utilisant l algorithme de propagation de croyance, mais au prix d une dégradation de la capacité de correction d erreurs. Leur performance de correction d erreurs, quant à elle, peut aussi être grandement améliorée en utilisant un algorithme de décodage par liste, mais au prix d une perte importante de vitesse de décodage et d une augmentation de la mémoire requise. Cette thèse présente de nouvelles solutions à ces problèmes. Elle propose un nouvel algorithme de décodage ayant la même performance de correction d erreurs que l annulation successive, mais offrant une latence significativement plus faible et un débit plus élevé. Une implémentation circuit de cet algorithme augmente la vitesse de décodage d un ordre de grandeur par rapport aux décodeurs les plus récents dans la littérature scientifique. La vitesse des décodeurs polaires par liste est également améliorée sans toutefois dégrader leur performance de correction d erreurs. Une implémentation logicielle de cet algorithme offre une performance de correction d erreurs et une vitesse qui excèdent tous les systèmes existants tout en répondant aux exigences de la norme Wi-Fi n. Ces travaux mettent en lumière une propriété bénéfique des codes polaires qui n avait pas été étudiée auparavant. Ils présentent également des systèmes d encodage et de décodage pouvant être utilisés avec des codes polaires de toutes longueurs et taux, tout en maintenant une faible complexité circuit ainsi qu une vitesse de fonctionnement rapide. Une telle flexibilité représente un avantage important pour les systèmes devant s adapter à des conditions de canal variées. Finalement, deux méthodes sont présentées pour améliorer les performances de correction d erreurs tout en nécessitant moins d espace mémoire que l algorithme par liste. La première vise les systèmes où la retransmission est impossible ou hautement indésirable, alors que la sec-

6 vi onde améliore la performance des décodeurs logiciels qui utilisent des codes polaires à des taux très proches de la capacité du canal.

7 vii Contents Contents List of Figures List of Tables List of Acronyms vii xii xiv xvii 1 Introduction Objectives Summary of Thesis Contributions Related Publications Thesis Organization Methodology Background Channel Polarization Constructing Polar Codes Systematic Encoding Successive-Cancellation Decoding Tree Structure of an SC Decoder Simplified Successive-Cancellation Decoding Bit-Reversed Indexing SC Decoder Implementation The Processing Element

8 viii Contents The Line SC Decoder The Semi-Parallel SC Decoder The Two-Phase SC Decoder Belief Propagation Decoders Implementations List Decoding Fast-SSC Decoding Latency of Node Updates under Resource Constraints Maximum-Likelihood Nodes Throughput of ML-SSC Decoding The Fast-SSC Nodes Single-Parity-Check Nodes N SPC Repetition Nodes N REP Repetition-SPC Nodes N REP-SPC Node Mergers Required Decoder Functions Performance with Quantization Latency Compared to ML-SSC Decoding Architecture: Top-Level Architecture: Data Loading and Routing Channel α Values Internal α Values Internal β Values Estimated Codeword Routing Architecture: Data Processing The f and g Blocks Repetition Block Repetition-SPC Block Single-Parity-Check Block Maximum-Likelihood Block

9 Contents ix 3.8 Implementation Results Methodology Comparison with the State of the Art SC- and SSC-based Polar Decoders Comparison with an LDPC code of similar error correcting performance Conclusion Fast List Decoders Proposed List-Decoding Algorithm Candidate Generation and Reliability Rate-0 Decoders Rate-1 Decoders SPC Decoders Repetition Decoders Performance Choosing a Suitable CRC Length Error-Correction Performance Unrolled Software Fast-SSC Decoders Tree Optimization C++ Code Generation Memory Layout Computation Other Optimizations Results Unrolled Software Fast-SSC List Decoders Memory Layout for α Values Memory Layout for β Values Rate-R and Rate-0 Nodes Rate-1 Nodes Repetition Nodes SPC Nodes Adaptive Decoder Latency and Throughput

10 x Contents Methodology Results Comparison with LDPC Codes Comparison with the (2048, 1723) LDPC Code Comparison with the n LDPC Codes Conclusion Flexible Encoding and Decoding Proposed Systematic Encoding Algorithm Preliminaries Mathematical Description Auxiliary Lemmas Proof of Correctness Flexible Hardware Encoders Non-Systematic Encoder Architecture Flexible Non-Systematic Encoder Non-Systematic Encoder Implementation Systematic Encoder Architecture Systematic Encoder Implementation On Code Shortening Flexible Software Encoders Flexible Hardware Decoders Stage Indices and Sizes Implementation Results Flexible Software Decoders Memory Vectorization Results Conclusion Improving Error-Correction Performance Chase Decoding of Polar Codes Generating Error Patterns

11 Contents xi Error Pattern Distribution Codeword Selection Metric Proposed Method Performance Effect on Decoding Speed Software-Oriented SPA Approximation Relevance to QKD Results Conclusion Conclusion and Future Work Future Work Further Optimization of the Fast-SSC Decoding Algorithm ASIC Implementation of the Fast-SSC Decoder Low-complexity List Decoder Implementations A Replacement for List Decoding Bibliography 121

12 xii List of Figures 2.1 Polarizing transformation Performance of polar codes of rate 0.84 compared with that of the 802.3an LDPC code Performance of polar codes of compared with those of the n LDPC codes SC decoder tree for an (8, 5) polar code SSC decoder tree for an (8, 5) polar code The graph of an (8, 5) polar code with bit-reversed indexing Flow of soft information in the SC decoder when estimating û 0 and û Architecture of the original processing element Architecture of the line SC decoder for N = Utilization rate and relative speed of the semi-parallel SC decoder for codes of lengths 2 10, 2 11, and Message passing in a section of a belief-propagation decoder Performance of BP and SC decoding when using a (2048, 1723) polar code Error correction performance of list and list-crc decoding FER and BER of the polar-crc codes with of length 1024 and L = 2 compared with those of the n standard of length Decoder tree of the ML-SSC decoder for an (8, 5) polar code Error-correction performance comparison between the SSC and ML-SCC decoding algorithms Effect of code rate (a) and length (b) on the information throughput of the SC, SSC, and ML-SSC decoders with P = SPC (a) and repetition (b) codes of length N =

13 List of Figures xiii 3.5 Effect of quantization on the error-correction performance of the (32768, 27568) and (32768, 29492) codes Top-level architecture of the decoder Architecture of the data processing unit The effect of CRC length on the error-correction performance of (1024, 860) list- CRC decoders with L = FER of the polar-crc (2048, 1723) code using the proposed decoder with different list sizes, with and without SPC decoders Dataflow graph of a (8, 4) polar decoder Frame-error rate of the proposed decoders of length 1024 compared with those of the n standard of length Frame-error rate of polar codes (N = 2048) compared with that of the LDPC codes of the n standard (N = 1944) at rates: (a) R = 1/2, (b) R = 2/3, (c) R = 3/4, and (d) R = 5/ The proposed systematic encoder for an (8, 5) polar code Architecture of the proposed semi-parallel non-systematic polar encoder with N = 16 and P = Flexible encoder with maximum code length N max and parallelism P Frame error rate of the Chase decoder compared to other decoders with N = 2048 and k = 1024 (R = 0.5) FER of the Chase-SC decoder compared to other decoders for N = Efficiency relative to the capacity of the BSC(p) using the approximate SPA and min-sum decoders for codes of length

14 xiv List of Tables 2.1 N = 1024 line decoder post-synthesis area using the TSMC 65nm process with 5-bit quantization and f = 500 MHz Synthesis results for the semi-parallel SC decoder targeting the TSMC 65nm process at 500MHz Resource utilization of the semi-parallel SC decoder using P = 64 on the Altera Stratix EP4SGX530KH40C Resource utilization of the TP-SC decoder on the Altera Stratix EP4SGX530KH40- C Resource utilization of the BP and SC decoders on the Xilinx Virtex XC4VSX25-12 using the (1024, 512) polar code Resource utilization of the BP decoder of [1] implemented using TSMC 65 nm CMOS technology Number of all nodes and of SPC nodes of different sizes in three polar codes of length and rates 0.9, , and Number of all nodes and of repetition nodes of different sizes in three polar codes of length 32,768 and rates 0.9, , and A listing of the different functions performed by the Fast-SSC decoder Latency of ML-SSC decoding of the (32768, 29492) code and the effect of using additional nodes types on it Resource utilization for polar decoders with N = 32,768 on the Altera Stratix EP4SGX530KH40C Information throughput comparison for codes with N = 32,768 on the Altera Stratix EP4SGX530KH40C

15 List of Tables xv 3.7 Resource utilization and information throughput results for a (16384, 14746) code on the Altera Stratix EP4SGX530KH40C Comparison with an LDPC code of similar error correcting performance, on the Xilinx Virtex VI XC6VLX550TL Comparing software polar decoders for codes of rates 1/2, 5/6, 0.84 and Latency (in µs) of decoding the (2048, 1723) polar-crc code using the proposed method with different list sizes, with and without SPC decoders compared to that of SC-list decoder. Speedups compared to SC-List are shown in brackets Information throughput of the proposed adaptive decoder with L max = Information throughput and latency of the proposed adaptive decoder with L max = 32 compared to the (2048, 1723) LDPC decoder Information throughput and latency of the proposed list decoder compared with the LDPC decoders of [2] when estimating 524,280 information bits Notation used in the proof of encoder correctness Implementation of the proposed R-flexible and RN-flexible non-systematic encoders compared with that of [3] for N max = and P = 32 on the Altera Stratix IV EP4SGX530KH40C Implementation of the proposed R-flexible and RN-flexible systematic encoders for n max = and P = 32 on the Altera Stratix IV EP4SGX530KH40C Implementation of the proposed RN-flexible systematic encoder for different N max and P values on the Altera Stratix IV EP4SGX530KH40C Implementation of the proposed RN-flexible systematic encoder with shortening on the Altera Stratix IV EP4SGX530KH40C Latency and coded throughput of a software systematic encoder with N = 32, 768 and different P values running on an Intel Core i Implementation of the RN-flexible polar decoder compared to the R-flexible decoder from Chapter. 3 on the Altera Stratix IV EP4SGX530KH40C Speed of the proposed vectorized decoder compared with that of non-vectorized and fully-unrolled decoders when N = N max = and k = Speed of the proposed vectorized decoder compared with that of non-vectorized and fully-unrolled decoders for a (2048, 1723) code and N max =

16 xvi List of Tables 6.1 Error pattern statistics for collected using a 5-active genie Average number of decoding attempts for three polar-crc Speed comparison between the proposed approximate SPA decoder, the min-sum decoder, and the SPA decoder used in [4]

17 xvii List of Acronyms ASIC AVX AWGN B-DMC BEC BER BP BPSK BSC CRC CS EDC edram FER FPGA LDPC LLR ML ML-SSC OPDG PE application-specific integrated circuit. advanced vector extensions. additive white Gaussian-noise. binary discrete memoryless channel. binary erasure channel. bit-error rate. belief propagation. binary phase-shift keying. binary symmetric channel. cyclic redundancy check. compare select. error-detecting code. embedded dynamic random access memory. frame-error rate. field-programmable gate-array. low-density parity-check. log likelihood ratio. maximum-likelihood. simplified successive cancellation with maximum-likelihood nodes. optimized polar-decoder generator. processing element.

18 xviii List of Acronyms PSN QKD RAM SC SDR SIMD SPA SPC SSC SSE TP-SC partial sorting network. quantum key distribution. random-access memory. successive-cancellation. software-defined radio. single-instruction multiple-data. sum-product algorithm. single parity check. simplified successive cancellation. streaming SIMD extensions. two-phase successive-cancellation.

19 The difference between the right word and the almost right word is the difference between lightning and the lightning bug. Mark Twain

20 1 Chapter 1 Introduction Nearly seventy years ago, Claude Shannon set a limit: no matter how advanced our technology becomes, how sophisticated our algorithms, we cannot reliably transmit information at rates, or efficiency, higher than what he called the channel capacity [5]. However, he left the question of how to achieve this channel capacity unanswered. For decades, researchers tried to find methods to achieve, or even approach, the channel capacity. These efforts bore fruit in 1993 when turbo codes were discovered [6]. These codes came close to capacity in certain cases and rejuvenated the field of error correcting codes. Low-density parity-check (LDPC) codes, originally discovered by Gallager in the 1960s [7], were rediscovered and found to also have excellent error-correction performance. These two codes, along with Reed-Solomon codes, are largely responsible for our ability to communicate with probes on the edge of our solar system [8], to store data at unprecedented densities [9], and to exchange 167 terabits of data per second via wired and wireless internet devices [10]. While the error-correction performance of turbo and LDPC codes under iterative decoding comes within fractions of a db from the Shannon limit in certain cases, they do not achieve the channel capacity. Turbo codes in particular exhibit severe error floor; where the error-correction performance of the decoder almost stops improving with improving channel conditions. Moreover, both codes require randomness in their construction, complicating that process and increasing routing complexity in hardware implementations. In 2008, Arıkan introduced polar codes, which asymptotically achieve the symmetric capacity of memoryless channels [11, 12]. More importantly, they accomplish this with an explicit, nonrandom construction, using the low-complexity successive-cancellation decoding algorithm. Polar

21 2 Introduction codes exploit the channel polarization phenomenon, in which certain bits are always estimated reliably while others are completely unreliable when decoding using successive cancellation. The proportion of reliable bits converges to the channel capacity as the code length increases. The regular, non-random structure of polar codes allows for implementations that are simpler than those required for turbo and LDPC codes. Despite their low-complexity implementations and capacity achieving property, polar codes were not competitive with LDPC codes for two major reasons. First, the successive-cancellation decoding algorithm, being serial in nature, resulted in low-throughput decoders. Successive cancellation decoders had a throughput of 250 Mbps for a decoder running at 500 Mhz [13]. Belief propagation was proposed as a decoding algorithm with higher parallelism than successive cancellation. Its first implementation had a throughput of 2.8 Mbps with a clock frequency of 160 MHz when the number of iterations is adjusted to yield error-correction performance similar to successive cancellation [14]. It was also evident that current implementations did not scale well with code length as a significant degradation in operating clock frequency was observed in [15] for longer codes. The second issue with polar codes was that they only achieved capacity asymptotically, exhibiting mediocre error-correction performance at moderate lengths. List decoding was known to improve the performance of polar codes [16]. However, it was shown that maximum-likelihood (ML) decoding error-correction performance was lacking for codes of moderate length, highlighting the limit of list decoding [16]. List decoding with cyclic redundancy check (CRC) assistance was later shown to resolve that issue and to provide excellent error-correction performance [16]. It is conjectured that the CRC increases the minimum distance of polar codes, leading to the aforementioned improvement [17]. The list decoding process exacerbates decoding slowness, since it is similar to operating multiple successive-cancellation decoders. Early estimates showed that a software successive-cancellation list decoder for polar codes has a throughput of 72 Kbps when running on a modern desktop processor and with a list of size 32. Such was the state of polar decoder implementation when this research began: slow successivecancellation decoder that did scale well with code length, and slower list decoders for which no efficient implementation existed.

22 1.1 Objectives Objectives The objectives of this work are to develop polar encoders and decoders that (a) have high throughput and low latency, (b) have the same or better error-correction performance than non-list successivecancellation decoders, and (c) have low complexity and versatile implementations suitable for use with varying channel conditions. 1.2 Summary of Thesis Contributions This thesis proposes encoding and decoding algorithms for polar codes with their corresponding low-complexity, high-speed implementations. Fast-SSC Decoding The first polar decoders suffered from low throughput and high latency. We introduce a new decoding algorithm with the goal of increasing parallelism in the decoder. It significantly reduces the number of operations in the decoder by utilizing specialized low-complexity ML decoders. An architecture using the new algorithm is presented. Its field-programmable gate-array (FPGA) implementation has a throughput of 1 Gbps at a clock frequency of 100 MHz an order of magnitude faster than the state-of-the-art in the literature. Fast List Decoders for Polar Codes The list decoding algorithm and its variants solved the performance issue of moderate length polar codes. This work presents a new algorithm based on unrolling the decoding tree of polar codes, improving the speed of list decoding by an order of magnitude when implemented in software. Furthermore, it shows that for software-defined radio applications, the proposed algorithm is faster than the fastest software implementations of LDPC decoders in the literature while offering comparable error-correction performance at similar or shorter code lengths. The software implementation is capable of decoding at 196 Mbps on a single core of the Intel Core i processor.

23 4 Introduction Flexible Encoders and Decoders for Systematic Polar Codes Modern communication systems must cope with varying channel conditions and differing throughput and transmission latency constraints. In this thesis, hardware and software implementations of flexible polar systematic encoders and decoders are introduced. The proposed implementations operate on polar codes of any length and rate. The correctness of a new low-complexity, flexible systematic-encoding algorithm is proved. The hardware implementation results show that the overhead of adding code rate and length flexibility is minor, and the impact on operation latency is negligible compared to code-specific versions. The encoder can achieve a throughput in excess of 30 Gbps on FPGA and 10 Gbps in software. Adding flexibility did not affect the throughput or latency of the FPGA decoder at all. Finally, the flexible software encoder and decoder implementations are also shown to be able to maintain high throughput and low latency. Chase Decoding of Polar Codes and a Software-oriented SPA Approximation While list-crc decoding significantly improves the error-correction performance of polar codes, it requires multiple times the memory of a normal polar decoder. This chapter presents two schemes that improve error-correction performance and have advantages over list-crc decoding in certain cases. The first method is a general algorithm that exploits a priori knowledge about the output of polar decoders. The second, is an improved low-complexity approximation for an operation in the decoder, targeting software implementations and codes with rates close to the channel capacity. 1.3 Related Publications This doctoral research has resulted in several publications, a partial list of which and how they relate to the chapters of this thesis is provided here. 1. G. Sarkis and W. J. Gross, Increasing the throughput of polar decoders, IEEE Commun. Lett., vol. 17, no.4, pp , [18] This journal letter analyzed potential speed gains due to parallelization in a resource-constrained polar decoder and presented a new decoding algorithm that was twice as fast as the state of the art. The first part of Chapter 3 discusses the contributions of this paper.

24 1.3 Related Publications 5 2. G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. Gross, Fast polar decoders: Algorithm and implementation, IEEE J. Sel. Areas Commun., vol. 32, no. 5, pp , May [19] This journal publication expanded on the previous one by utilizing specialized decoders to achieve 1 Gbps decoding speed. Chapter 3 includes the algorithm, architecture, and implementation results from this work. The paper also introduced a new algorithm for systematic polar encoding that is incorporated into Chapter G. Sarkis, P. Giard, C. Thibeault, and W. Gross, Autogenerating software polar decoders, in IEEE Glob. Conf. on Signal and Inf. Process. (GlobalSIP), Dec 2014, pp [20] This conference paper described how unrolled software decoder with throughput in excess of 300 Mbps are generated. These results are reported in the non-list decoder section of Chapter G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, Fast list decoders for polar codes, in IEEE J. Sel. Areas Commun., This journal publication applied results from [19] and [20] to list decoding of polar codes, yielding software polar decoders that surpass their LDPC counterparts in speed and errorcorrection performance. Chapter 4 incorporates these results. 5. G. Sarkis, I. Tal, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, Flexible and lowcomplexity encoding and decoding of systematic polar codes, CoRR, vol. abs/ , [Online]. Available: Submitted to IEEE Trans. Commun. [21] This journal paper proved the correctness of the systematic encoding algorithm originally introduced in [19]. It then presented systematic encoders and decoders capable of operating on polar codes of any length and rate while maintaining high speed and low implementation complexity. The implementation results from this paper are incorporated into Chapter 5. The chapter presents a proof of correctness that was the precursor to that in [21]. The proof in [21] was developed by Prof. Ido Tal to be more general than the one in Chapter G. Sarkis and W. J. Gross, Polar codes for data storage applications, in Int. Conf. on Computing, Networking and Commun. (ICNC). 2013, pp (invited) [22]

25 6 Introduction This conference papers discussed the potential use of polar codes in storage applications. It introduced a Chase-like algorithm for improving the error-correction performance of polar codes with smaller memory overhead than list-based decoders. 1.4 Thesis Organization Chapter 2 reviews polar codes, including construction, encoding, and decoding. It summarizes implementation results of the different decoding algorithms in the literature and discusses list decoding. A decoding algorithm for polar codes with increased parallelism and throughput is introduced along with implementation results in Chapter 3. The effect of different code and implementation parameters on throughput and latency is also discussed. Chapter 4 presents fast, unrolled software polar decoders and polar list decoders. It also parallelizes the list decoding algorithm and compares the results with the state of the art in software decoders. A paralleliazable, low-complexity systematic encoding algorithm is presented and proved to be correct in Chapter 5. Rate and length flexible encoder implementations based on this algorithm, in addition to decoder implementations, are also presented in this chapter. A Chase-like decoding algorithm is introduced in Chapter 6 and is shown to improve errorcorrection performance with less memory requirements than the list decoding algorithm. A softwaresuitable approximation to an operation in the polar decoder is also presented and is shown to offer the same error-correction performance as the sum-product algorithm, but with speed closer to that of the min-sum algorithm. Finally, Chapter 7 concludes this work and presents potential avenues for future work. 1.5 Methodology The error-correction performance results presented in this work are obtained by simulating the transmission of a minimum of 10,000 randomly-generated codewords over a noisy channel. A minimum of 100 frame errors were also observed for each data point. The decoders presented in this work, with the exception of the adaptive list decoder in Table 4.3, decode one codeword at a time. Their latency, L, and throughput, T, are related according to T = k/l; where k is the

26 1.5 Methodology 7 number of information bits per codeword. Therefore, the methods presented in this work both reduce latency and increase throughput.

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28 9 Chapter 2 Background This chapter provides a review of polar codes and their encoding and decoding methods. It starts with a description of polar codes and their construction. It then describes the basic encoding method for both non-systematic and systematic codes. The low-complexity successivecancellation decoding method is reviewed next, along with hardware implementations from the literature. The chapter proceeds with a description of the simplified successive-cancellation decoding algorithm, which was the first to provide a significant increase in decoding speed. The belief-propagation decoding algorithm and two implementations are discussed. Finally, the list decoding algorithm for improving the error-correction performance is reviewed. In addition to the algorithms that yielded major improvements, ones with smaller impact are mentioned throughout the chapter. 2.1 Channel Polarization In his seminal work, Arıkan introduced the concept of channel polarization [12], where a polarizing transformation is applied to improve the probability of correctly detecting a proportion of the bits transmitted over a memoryless channel. Let W be a binary discrete memoryless channel (B-DMC) with input and output alphabets X and Y, respectively; and transition probability W(y x), where x X and y Y. The symmetric channel capacity, I(W), and the Bhattacharyya parameter, Z(W)

29 10 Background are two measures of the channel quality that are defined as and I(W) = y Y x X 1 2 W(y x) log W(y x) 1 W(y 0) + 1W(y 1) 2 2 Z(W) = W(y 0)W(y 1). y Y The symmetric capacity is the highest rate at which reliable communications can take place over W and the Bhattacharyya parameter provides an upper bound on the probability of erroneous detection when ML is used to estimate a single received symbol y. Both metrics have values [0, 1] and are related by these two inequalities when transmission occurs over a B-DMC: I(W) log Z(W) (2.1) I(W) 1 Z(W) 2 ; (2.2) from which it can be observed that I(W) 1 iff Z(W) 0 and I(W) 0 iff Z(W) 1; where I(W) = 1 indicates error free transmission (a perfect channel) and I(W) = 0 indicates that information transmission is not possible (a completely-unreliable channel). When two bits (u 0, u 1 ) X 2 are transmitted using two independent instances of W or by using the memoryless W twice, two values (y 0, y 1 ) Y 2 are received (as shown in Fig. 2.1a) with the following mutual information values: I(Y 0,Y 1 ;U 0 ) = I(W) = I(Y 0,Y 1 ;U 1 ). However, if (u 0, u 1 ) are transformed into (x 0, x 1 ) so that: x 0 = u 0 u 1 and x 1 = u 1 (as in Fig. 2.1b); the mutual information values between the information and received symbols become: I(Y 0,Y 1 ;U 0 ) I(W) I(Y 0,Y 1 ;U 1 ). In other words, the probability of correctly estimating u 0 decreases while that of u 1 increases. Proof of this inequality is presented in [12]. The polarizing transformation can be applied recursively to transform multiple instances (or uses) of W, as shown in Fig. 2.1c for eight instances of the

30 2.2 Constructing Polar Codes 11 S 0 S 1 S 2 S 3 u 0 x W y 0 u x 1 W y 1 u x 2 W y 2 u 3 + x 3 W y 3 u x 4 W y 4 u 0 x 0 W y 0 u 0 + x 0 W y 0 u 5 + u 6 + x 5 W y 5 x 6 W y 6 u 1 x 1 W y 1 (a) No transformation u 1 x 1 W y 1 (b) Two instances u 7 x 7 W y 7 (c) Eight instances Fig. 2.1 Polarizing transformation. channel. As the number of transformed channels increases, i.e. the code length, N,, the probability of correctly estimating a symbol u i approaches either 1.0 (completely reliable) or 0.5 (completely unreliable). The proportion of reliable bits approaches the channel capacity, i.e. the code rate, R, approaches the channel capacity, C. 2.2 Constructing Polar Codes To construct a polar code of length N and dimension k referred to as an (N, k) polar code an N-bit vector u is created by placing the information bits in the k most reliable locations; while the remaining bits are frozen by setting them to a know value usually 0. We denote the information and frozen bit sets A and A C, respectively. The polarizing transformation is then applied log 2 N times, yielding the polar codeword x. This process is illustrated in Fig. 2.1c for an (8, 5) polar code. Bits u 0, u 1, and u 2 highlighted in gray are the least reliable bits and, as such, are set to 0. The location of the least-reliable, or frozen, bits in u varies based on channel conditions. Determining the frozen bit locations for the binary symmetric channel (BSC) and the binary erasure channel

31 12 Background (BEC) was done in [12] and a practical method for the additive white Gaussian-noise (AWGN) channel was developed in [23]. Fig. 2.1c also demonstrates how the graph is decomposed into stages, with stage S 0 corresponding to bits u 0...u N 1 and S i to the ith level of concatenation. Using matrices, the basic two-bit transformation depicted in Fig. 2.1b is represented by F = The matrix for a transformation of length N, a power of 2, is constructed using the Kronecker power: F log 2 N = F F log 2 N 1 ; where F 1 = F. The matrix F log 2 N is also called the generator matrix of length N, G N, and is used to encode a properly prepared N-bit row-vector, u, according to x = ug N. For example, G 8, which is used in Fig. 2.1c, is G 8 = F = The resulting codeword, x, is non-systematic, i.e. the information bits do not appear unaltered. It should be noted that the generator matrix does not change with the number and location of the frozen bits. These changes affect the input vector u. An alternative method of encoding where u contains only information bits and G only the corresponding rows was presented in [12] as well. 2.3 Systematic Encoding The encoding scheme presented in the previous section, where the input vector u is multiplied by the generator matrix G, results in a non-systematic polar codeword x in which information bits do

32 2.4 Successive-Cancellation Decoding 13 not appear. A systematic codeword on the other hand can be separated into information and parity bits, i.e. it includes the information bits unaltered. There are multiple advantages to systematic encoding: easier information extraction, better bit-error rate (BER), and suitability for use in a turbo coding schemes are some examples. A systematic encoding scheme for polar codes was introduced in [24] and was shown to improve the BER. This systematic encoding algorithm starts with the information bits, denoted x A here, and calculates the parity bits according to x A C = x A (G AA ) 1 G AA C; (2.3) where G AA is a submatrix of G whose rows and columns correspond to the information bit indices, and G AA C s rows and columns corresponds to the information and frozen bits, respectively. The parity and information bits are then combined into a systematic codeword where they are placed in the frozen and information bit locations, respectively. When the recursive nature of the generator matrix G is exploited, a serial implementation of this algorithm has a time complexity of O(N log N); where N is the code length. 2.4 Successive-Cancellation Decoding A very interesting property of polar codes is that they are proved to achieve the symmetric channel capacity with the low-complexity successive-cancellation decoding algorithm. As indicated by its name, successive-cancellation (SC) decoding estimates bits sequentially starting with u 0. Once the estimates û 0 to û i 1, denoted û i 1 0, are available, an information bit, u i, is estimated according to the following rule 0, when Pr[y, û i 1 0 û i = u i = 0] Pr[y, û i 1 0 u i = 1]; 1, otherwise. In this work, it is assumed that all frozen bits are set to 0 ; therefore, estimates for such bits are always 0. The probabilities Pr[y, û i 1 0 û i = 0] and Pr[y, û i 1 0 û i = 1] can be calculated recursively. For example, using the values x N 1 0, shown in Fig. 2.1b for N = 2, the likelihood values for û 0 can be calculated as follows: (2.4)

33 14 Background Pr[y û 0 = 0] = Pr[y ˆx 0 = 0]Pr[y ˆx 1 = 0] + Pr[y ˆx 0 = 1]Pr[y ˆx 1 = 1] Pr[y û 0 = 1] = Pr[y ˆx 0 = 0]Pr[y ˆx 1 = 1] + Pr[y ˆx 0 = 1]Pr[y ˆx 1 = 0]. (2.5) The likelihoods of û 1 depend on the value of û 0 and are calculated as the following when û 0 = 0: and Pr[y, û 0 = 0 û 1 = 0] = Pr[y ˆx 0 = 0]Pr[y ˆx 1 = 0] Pr[y, û 0 = 0 û 1 = 1] = Pr[y ˆx 0 = 1]Pr[y ˆx 1 = 1]; when û 0 = 1. Pr[y, û 0 = 1 û 1 = 0] = Pr[y ˆx 0 = 1]Pr[y ˆx 1 = 0] Pr[y, û 0 = 1 û 1 = 1] = Pr[y ˆx 0 = 0]Pr[y ˆx 1 = 1], (2.6) These operations are applied recursively for longer polar codes until the channel output y is used as input to (2.5) and (2.6). It was shown in [25] that log likelihood ratios (LLRs) can be used instead of likelihoods when decoding polar codes. Using LLRs, the Rule (2.4) can be written as where 1 0, when λ ui 0; û i = 1, otherwise; λ i = log Equations (2.5) and (2.6) become [26, 25] Pr(y, ûi 1 0 u i = 0) Pr(y, û i 1 0 u i = 1). (2.7) λ 0 = f (λ v0, λ v1 ) = λ v0 λ v1 1 To simplify notation in this work, λ will be used to denote an arbitrary LLR. Whereas y will be used to denote both the channel outputs and the LLRs calculated from them. Since, this work discusses LLR-based implementations, y will always refer to an LLR from this point on, unless otherwise noted.

34 2.4 Successive-Cancellation Decoding 15 = 2 tanh 1 (tanh(λ v0 /2) tanh(λ v1 /2)); (2.8) and λ v0 + λ v1, when û 0 = 0, λ 1 = g(λ v0, λ v1, û 0 ) = λ v0 + λ v1, otherwise; (2.9) respectively. Additionally, the min-sum approximation of the operator can be used to reduce the complexity of (2.8) without significantly affecting the error-correction performance [26, 13], yielding: λ 0 = sign(λ v0 )sign(λ v1 ) min( λ v0, λ v1 ). (2.10) Fig. 2.2 shows the error correction performance of polar codes of rate 0.84 and different lengths compared to the LDPC code of the 802.3an 10-gigabit Ethernet standard [27]. Transmission was simulated over the AWGN channel using binary phase-shift keying (BPSK) and random codewords. The polar decoders all used the min-sum approximation and the LDPC decoder used the min-sum algorithm with a scaling factor of 0.5. At the same length and rate, it can be seen that the polar code s performance is 0.25 db worse than the LDPC s at a frame-error rate (FER) of and the gap grows to 1 db at The N = polar code outperforms the LDPC code once the energy per bit to noise-power spectral density ratio, E b /N 0, is greater than 3.75 db, and the N = code closely matches the LDPC code for E b /N The change in the slope of the polar codes FER is due to the code construction point: the polar codes were constructed for an E b /N 0 value of 4.25 db at this code rate. To illustrate the effect of the code construction on its performance, a second code of length that is constructed for E b /N 0 = 4.5 is shown in Fig. 2.2 and denoted PC*. Its FER is better than the other N = code for E b /N 0 = 4.5, but worse for lower values. In other cases, polar codes have comparable error-correction performance to LDPC codes of similar length as shown in Fig. 2.3, which compares polar of length 2048 with the 1944-bit LDPC codes of the n standard at the same rates [28]. The polar codes were decoded using an SC decoder and the LDPC codes used a scaled min-sum decoder with 10 iterations. The FER of the two code families is comparable down to 10 4 : polar codes are slightly better at high FER values and the LDPC codes at lower values. LDPC codes show better BER results. The rate 0.5 codes are an exception: the polar code consistently has better FER and BER than its LDPC counterpart.

35 16 Background FER 10 6 BER E b /N 0 E b /N 0 Fig. 2.2 LDPC code PC (2048, 1723) PC (16384, 13784) PC* (16384, 13784) PC (32768, 27568) LDPC (2048, 1723) Performance of polar codes of rate 0.84 compared with that of the 802.3an 2.5 Tree Structure of an SC Decoder A polar code of length N is the concatenation of two constituent polar codes of length N/2. Since this construction is recursive, a binary tree is a natural representation for a polar code where each node corresponds to a constituent code. Fig. 2.4 shows the tree representation for an (8, 5) polar code where the white (N 0 ) and black (N 1 ) nodes correspond to frozen and information bits, respectively; gray nodes represent the operations required to concatenate two constituent codes. Each sub-tree at a distance i from the leaf-nodes is a constituent polar code of length N v = 2 i. The tree is traversed depth-first. A node v, corresponding to a constituent code of length N v, receives a real-valued message vector, α v containing the N v soft-valued inputs to the constituent polar decoder from its parent node, p. It calculates the soft-valued input to its left child, α l, using (2.10) applied element-wise: α l [i] = f (α v [i], α v [i + N v /2]) = α v [i] α v [i + N v /2]. (2.11) Once the binary-valued constituent-codeword estimate, β l, from the left child is available, it is