XRT73L02M GENERAL DESCRIPTION FEATURES APPLICATIONS TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

Transcription

1 xr XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT MAY 23 REV... GENERAL DESCRIPTION The XRT73L2M is a two-channel fully integrated Line Interface Unit (LIU) for E3/DS3/STS- applications. It incorporates independent Receivers, Transmitters in a single pin TQFP package. The XRT73L2M can be configured to operate in either E3 ( MHz), DS3 ( MHz) or STS- (5.84 MHz) modes.the transmitter can be turned off or tri-stated for redundancy support and for conserving power. The XRT73L2M s differential receiver provides high noise interference margin and is able to receive the data over feet of cable or with up to 2 db of cable attenuation. The XRT73L2M provides both Serial Microprocessor Interface as well as Hardware mode for programming and control. The XRT73L2M supports local,remote and digital loop-backs. The XRT73L2M also contains an onboard Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error. FEATURES RECEIVER: On chip Clock and Data Recovery circuit for high input jitter tolerance. Meets the jitter tolerance requirements as specified in ITU-T G.823_993 for E3 and Telcordia GR-499- CORE for DS3 applications. Detects and Clears LOS as per G.775. Receiver Monitor mode handles up to 2 db flat loss with 6 db cable attenuation. On chip B3ZS/HDB3 encoder and decoder that can either be enabled or disabled. On-chip clock synthesizer generates the appropriate rate clock from a single frequency XTAL. Provides low jitter clock outputs for either DS3,E3 or STS- rates. On-chip clock synthesizer provides the appropriate rate clock from a single MHz Clock. Provides low jitter output clock. TRANSMITTER: Compliant with Bellcore GR-499, GR-253 and ANSI T.2 Specification for transmit pulse Tri-state Transmit output capability for redundancy applications Transmitter can be turned on or off. CONTROL AND DIAGNOSTICS: 5 wire Serial Microprocessor Interface for control and configuration. Supports optional internal Transmit Driver Monitoring. PRBS error counter register to accumulate errors. Hardware Mode for control and configuration. Supports Local, Remote and Digital Loop-backs. Single 3.3 V ± 5% power supply. 5 V Tolerant I/O. Available in pin TQFP. -4 C to 85 C Industrial Temperature Range. APPLICATIONS E3/DS3 Access Equipment. STS-SPE to DS3 Mapper. DSLAMs. Digital Cross Connect Systems. CSU/DSU Equipment. Routers. Fiber Optic Terminals. Exar Corporation 4872 Kato Road, Fremont CA, (5) FAX (5)

2 XRT73L2M xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT FIGURE. BLOCK DIAGRAM OF THE XRT 73L2M SDI SDO INT SClk CS RESET Serial Processor Interface XRT75L3 CLK_OUT E3Clk,DS3Clk, STS-Clk RLOL RxON RxClkINV HOST/HW STS-/DS3 E3 REQEN RTIP RRING AGC/ Equalizer Peak Detector Slicer Clock & Data Recovery Clock Synthesizer MUX Invert HDB3/ B3ZS Decoder RxClk RPOS RNEG/ LCV SR/DR LLB Local LoopBack LOS Detector Remote LoopBack RLB RLOS TTIP TRING Line Driver Tx Pulse Shaping Timing Control MUX HDB3/ B3ZS Encoder TPOS TNEG TxClk MTIP MRING DMO Device Monitor Tx Control TAOS TxLEV TxON Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode. TRANSMIT INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line Integrated Pulse Shaping Circuit. Built-in B3ZS/HDB3 Encoder (which can be disabled). Accepts Transmit Clock with duty cycle of 3%- 7%. Generates pulses that comply with the ITU-T G.73 pulse template for E3 applications. Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T.2_993. Generates pulses that comply with the STSX- pulse template, as specified in Bellcore GR-253- CORE. Transmitter can be turned off in order to support redundancy designs. RECEIVE INTERFACE CHARACTERISTICS Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery. Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications. Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_993 for E3 Applications. Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications. Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms. Built-in B3ZS/HDB3 Decoder (which can be disabled). Recovered Data can be muted while the LOS Condition is declared. Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment. 2

3 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... FIGURE 2. PIN OUT OF THE XRT73L2M TAOS_ TxLEV_ MRING_ MTIP_ TRING_ TTIP_ TxDVDD_ TxDGND_ DVDD E3CLK DGND DGND DS3CLK DVDD DVDD STSCLK/SFMCLK DGND TxDGND_ TxDVDD_ TTIP_ TRING_ MTIP_ MRING_ TxLEV_ TAOS_ TNEG_ TPOS_ TxCLK_ DMO_ CLKOUT_ TxON TxMON TxAGND_ TxAVDD_ AGND_ AVDD_ DVDD_ DGND_ RxDVDD_ RxDGND_ RxCLK_ RPOS_ RNEG/LCV_ RLOS_ RLOL_ TEST RESET ICT SFM_EN SR/DR XRT73L2M TNEG_ TPOS_ TxCLK_ DMO_ CLKOUT_ CLKOUT_EN TxAGND_ TxAVDD_ AGND_ AVDD_ DVDD_ DGND_ DVDD_ DGND_ RxCLK_ RPOS_ RNEG/LCV_ RLOS_ RLOL_ SDI/RxON SCLK/TxCLKINV CS/RxCLKINV INT/LOSMUT SDO/RxMON HOST/HW REQEN_ E3_ STS/DS3_ LLB_ RLB_ RxAVDD_ RxAGND_ RRING_ RTIP_ AGND RxA RxB AVDD AGND AGND AGND RTIP_ RRING_ RxAGND_ RxAVDD_ RLB_ LLB_ STS/DS3_ E3_ REQEN_ ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT73L2MIV 4mm x 4mm Pin TQFP -4 C to +85 C 3

4 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... TABLE OF CONTENTS GENERAL DESCRIPTION... FEATURES... APPLICATIONS... Figure. Block Diagram of the XRT73L2M... 2 TRANSMIT INTERFACE CHARACTERISTICS... 2 RECEIVE INTERFACE CHARACTERISTICS... 2 Figure 2. Pin Out of the XRT73L2M... 3 ORDERING INFORMATION... 3 TABLE OF CONTENTS... I PIN DESCRIPTIONS (BY FUNCTION)... 4 TRANSMIT INTERFACE... 4 RECEIVE INTERFACE... 6 CLOCK INTERFACE... 9 OPERATING MODE SELECT... CONTROL AND ALARM INTERFACE... 4 ANALOG POWER AND GROUND... 5 DIGITAL POWER AND GROUND ELECTRICAL CHARACTERISTICS... 7 TABLE : ABSOLUTE MAXIMUM RATINGS... 7 TABLE 2: DC ELECTRICAL CHARACTERISTICS: TIMING CHARACTERISTICS... 8 Figure 3. Typical interface between terminal equipment and the XRT73L2M (dual-rail data)... 8 Figure 4. Transmitter Terminal Input Timing... 8 Figure 5. Receiver Data output and code violation timing... 9 Figure 6. Transmit Pulse Amplitude test circuit for E3, DS3 and STS- Rates LINE SIDE CHARACTERISTICS: E3 LINE SIDE PARAMETERS:... 2 Figure 7. Pulse Mask for E3 ( mbits/s) interface as per itu-t G TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS... 2 Figure 8. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS- Applications TABLE 4: STS- PULSE MASK EQUATIONS TABLE 5: STS- TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253). 23 Figure 9. Transmit Ouput Pulse Template for DS3 as per Bellcore GR TABLE 6: DS3 PULSE MASK EQUATIONS TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) Figure. Microprocessor Serial Interface Structure Figure. Timing Diagram for the Microprocessor Serial Interface TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 25C, VDD=3.3V± 5% AND LOAD = PF) FUNCTIONAL DESCRIPTION: The Transmitter Section: Figure 2. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) Figure 3. Dual-Rail Data Format (encoder and decoder are disabled) Transmit Clock: B3ZS/HDB3 Encoder: Figure 4. B3ZS Encoding Format Transmit Pulse Shaper: Figure 5. HDB3 Encoding Format Transmit Drive Monitor: Transmitter Section On/Off:... 3 Figure 6. Transmit Driver Monitor set-up The Receiver Section: AGC/Equalizer:... 3 IV

5 xr XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT REV... Figure 7. Interference Margin Test Set up for DS3/STS Figure 8. Interference Margin Test Set up for E TABLE 9: INTERFERENCE MARGIN TEST RESULTS Clock and Data Recovery: B3ZS/HDB3 Decoder: LOS (Loss of Signal) Detector: DISABLING ALOS/DLOS DETECTION: TABLE : THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS- APPLICATIONS) Figure 9. Loss Of Signal Definition for E3 as per ITU-T G Figure 2. Loss of Signal Definition for E3 as per ITU-T G Jitter: Jitter Tolerance - Receiver: Figure 2. Jitter Tolerance Measurements Figure 22. Input Jitter Tolerance For DS3/STS Figure 23. Input Jitter Tolerance for E Jitter Transfer - Receiver/Transmitter: TABLE : JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) TABLE 2: JITTER TRANSFER SPECIFICATION/REFERENCES TABLE 3: JITTER TRANSFER PASS MASKS Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance Jitter Generation: Serial Host interface:... 4 TABLE 4: FUNCTIONS OF SHARED PINS... 4 TABLE 5: REGISTER MAP AND BIT NAMES... 4 TABLE 6: REGISTER MAP DESCRIPTION - GLOBAL... 4 TABLE 7: REGISTER MAP AND BIT NAMES - CHANNEL REGISTERS TABLE 8: REGISTER MAP AND BIT NAMES - CHANNEL REGISTERS TABLE 2: REGISTER MAP DESCRIPTION Diagnostic Features: PRBS GENERATOR AND DETECTOR: LOOPBACKS: ANALOG LOOPBACK: Figure 25. PRBS MODE DIGITAL LOOPBACK: Figure 26. Analog Loopback REMOTE LOOPBACK:... 5 Figure 27. Digital Loopback TRANSMIT ALL ONES (TAOS):... 5 Figure 28. Remote Loopback... 5 Figure 29. Transmit All Ones (TAOS)... 5 APPENDIX Figure 3. EVALUATION BOARD SCHEMATICS Figure 3. Evaluation Board Schematics ORDERING INFORMATION PACKAGE DIMENSIONS - 4X2 MM, PIN PACKAGE REVISIONS V

6 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... PIN DESCRIPTIONS (BY FUNCTION) TRANSMIT INTERFACE PIN # SIGNAL NAME TYPE DESCRIPTION 8 TxON I Transmitter ON Input : This pin is active only when the corresponding TxON bit is set. Table below shows the status of the transmitter based on thetxon bit and TxON pin settings. Bit Pin Transmitter Status OFF OFF OFF ON TxCLK_ TxCLK_ TNEG_ TNEG_ TPOS_ TPOS_ TTIP_ TTIP_ TRING_ TRING_ NOTES:. This pin will be active and can control the TTIP and TRING outputs only when the TxON_n bits in the channel register are set. 2. When Transmitters are turned off the TTIP and TRING outputs are Tristated. 3. This pin is internally pulled up. I Transmit Clock Input for TPOS and TNEG - Channel : Transmit Clock Input for TPOS and TNEG - Channel : The frequency accuracy of this input clock must be of nominal bit rate ± 2 ppm. The duty cycle can be 3%-7%. By default, input data is sampled on the falling edge of TxCLK when input data is changing on the rising edge of TxCLK.. I Transmit Negative Data Input - Channel : Transmit Negative Data Input - Channel : In Dual-rail mode, these pins are sampled on the falling or rising edge of TxCLK_n NOTE: These input pins are ignored and must be grounded if the Transmitter Section is configured to accept Single-Rail data from the Terminal Equipment. I Transmit Positive Data Input - Channel : Transmit Positive Data Input - Channel : By default sampled on the falling edge of TxCLK O Transmit TTIP Output - Channel : Transmit TTIP Output - Channel : These pins along with TRING transmit bipolar signals to the line using a : transformer. O Transmit Ring Output - Channel : Transmit Ring Output - Channel : These pins along with TTIP transmit bipolar signals to the line using a : transformer. 4

7 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... TRANSMIT INTERFACE PIN # SIGNAL NAME TYPE DESCRIPTION 3 TxClkINV/ SClk I Hardware Mode: Transmit Clock Invert Host Mode: Serial Clock Input: Function of this pin depends on whether the XRT73L2M is configured to operate in Hardware mode or Host mode. In Hardware mode, setting this input pin High configures all the Transmitters to sample the TPOS_n and TNEG_n data on the rising edge of the TxClk_n. NOTES:. If the XRT73L2M is configured in HOST mode, this pin functions as SClk input pin (please refer to the pin description for Microprocessor interface). 82 TxMON I Transmitter Monitor: When this pin is pulled High, MTIP and MRING are connected internally to TTIP and TRING and allows self monitoring of the transmitter TxLEV_ TxLEV_ I Transmit Line Build-Out Enable/Disable Select - Channel : Transmit Line Build-Out Enable/Disable Select - Channel : These input pins select the Transmit Line Build-Out circuit. Setting these pins to "High" disables the Line Build-Out circuit of Channel n. In this mode, Channel n outputs partially-shaped pulses onto the line via the TTIP_n and TRing_n output pins. Setting these pins to "Low" enables the Line Build-Out circuit of Channel n. In this mode, Channel n outputs shaped pulses onto the line via the TTIP_n and TRing_n output pins. To comply with the Isolated DSX-3/STSX- Pulse Template Requirements per Bellcore GR-499-CORE or Bellcore GR-253-CORE:. Set these pins to "" if the cable length between the Cross-Connect and the transmit output of Channel is greater than 225 feet. 2. Set these pins to "" if the cable length between the Cross-Connect and the transmit output of Channel is less than 225 feet. These pins are active only if the following two conditions are true: a. The XRT73L2M is configured to operate in either the DS3 or SONET STS- Modes. b. The XRT73L2M is configured to operate in the Hardware Mode. NOTES:. These pins are internally pulled down. 2. If the XRT73L2M is configured in HOST mode, these pins should be tied to GND. 5

8 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... TRANSMIT INTERFACE PIN # SIGNAL NAME TYPE DESCRIPTION 75 5 TAOS_ TAOS_ I Transmit All Ones Select - Channel : Transmit All Ones Select - Channel : A High" on this pin causes the Transmitter Section of Channel_n to generate and transmit a continuous AMI all s pattern onto the line. The frequency of this s pattern is determined by TxClk_n. NOTES:. This input pin is ignored if the XRT73L2M is operating in the HOST Mode and should be tied to GND. 2. Analog Loopback and Remote Loopback have priority over request. 3. This pin is internally pulled down. RECEIVE INTERFACE PIN # SIGNAL NAME TYPE DESCRIPTION 25 REQEN_ REQEN_ I Receive Equalization Enable Input - Channel : Receive Equalization Enable Input - Channel : Setting this input pin "High" enables the Internal Receive Equalizer of Channel_n. Setting this pin "Low" disables the Internal Receive Equalizer. NOTES:. This input pin is ignored and should be connected to GND if the XRT73L2M is operating in the HOST Mode 2. This pin is internally pulled down. 3 RxON/ SDI 27 RxMON/ SDO I I Hardware Mode: Receiver Turn ON Input Host Mode: Serial Data Input: Function of this pin depends on whether the XRT73L2M is configured to operate in Hardware mode or Host mode. In Hardware mode, setting this input pin High turns on and enables the Receivers of all the channels. NOTES:. If the XRT73L2M is configured in HOST mode, this pin functions as SDI input pin (please refer to the pin description for Microprocessor Interface) 2. This pin is internally pulled down. Hardware Mode: Receive Monitoring Mode Host Mode: Serial Data Output: In Hardware mode, when this pin is tied High all 2 channels configure into monitoring channels. In the monitoring mode, the Receiver is capable of monitoring the signals with 2 db flat loss plus 6 db cable attenuation. This allows monitoring very weak signal before declaring LOS. In HOST Mode each channel can be independently configured to be a monitoring channel by setting the bits in the channel control registers. NOTE: If the XRT73L2M is configured in HOST mode, this pin functions as SDO pin (please refer to the pin description for the Microprocessor Interface). 6

9 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... RECEIVE INTERFACE PIN # SIGNAL NAME TYPE DESCRIPTION 9 36 RxCLK_ RXCLK_ 92 RPOS_ 35 RPOS_ 93 RNEG_/LCV_ 34 RNEG_/LCV_ 8 RRING_ 8 RRING_ 9 RTIP_ 7 RTIP_ 29 RxClkINV/ CS O Receive Clock Output - Channel : Receive Clock Output - Channel : By default, RPOS and RNEG data sampled on the rising edge RxCLK.. Set the RxCLKINV bit or tie RClkINV pin High to sample RPOS/RNEG data on the falling edge of RxCLK O Receive Positive Data Output - Channel : Receive Positive Data Output - Channel : NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero suppression patterns in the incoming line signal (such as: "V", "V", "BV", "BV") is removed and replaced with. O Receive Negative Data Output/Line Code Violation Indicator - Channel : Receive Negative Data Output/Line Code Violation Indicator - Channel : In Dual Rail mode, a negative pulse is output through RNEG. Line Code Violation Indicator - Channel n: If configured in Single Rail mode then Line Code Violation will be output. I Receive Ring Input - Channel : Receive Ring Input - Channel : These pins along with RTIP receive the bipolar line signal from the remote DS3/ E3/STS- Terminal. I Receive TIP Input - Channel : Receive TIP Input - Channel : These pins along with RRING receive the bipolar line signal from the Remote DS3/E3/STS- Terminal. I Hardware Mode: RxClk INVERT Host Mode: Chip Select: Function of this pin depends on whether the XRT73L2M is configured to operate in Hardware mode or Host mode. In Hardware mode, setting this input pin High configures the Receiver Section of all channels to invert the RxClk_n output signals and outputs the recovered data via RPOS_n and RNEG_n on the falling edge of RxClk_n. NOTE: If the XRT73L2M is configured in HOST mode, this pin functions as CS input pin (please refer to the pin description for Microprocessor Interface). 7

10 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... CLOCK INTERFACE PIN # SIGNAL NAME TYPE DESCRIPTION 66 E3CLK I E3 Clock Input ( MHz ± 2 ppm): If any of the channels is configured in E3 mode, a reference clock MHz is applied on this pin. NOTE: In single frequency mode, this reference clock is not required. 63 DS3CLK I DS3 Clock Input ( MHz ± 2 ppm): If any of the channels is configured in DS3 mode, a reference clock MHz. is applied on this pin. NOTE: In single frequency mode, this reference clock is not required. 6 STS-CLK/ 2M I STS- Clock Input (5.84 MHz ± 2 ppm): If any of the channels is configured in STS- mode, a reference clock 5.84 MHz is applied on this pin.. In Single Frequency Mode, a reference clock of MHz ± 2 ppm is connected to this pin and the internal clock synthesizer generates the appropriate clock frequencies based on the configuration of the channels in E3, DS3 or STS-. 99 SFM_EN I Single Frequency Mode Enable: Tie this pin High to enable the Single Frequency Mode. A reference clock of MHz ± 2 ppm is applied. This offers the flexibility of using a low cost reference clock and configures the board for either E3 or DS3 or STS- without the need to change any components on the board. Tie this pin Low if single frequency mode is not selected. In this case, the appropriate reference clocks must be provided. NOTE: This pin is internally pulled down 8 46 CLKOUT_ CLKOUT_ O Clock output for channel Clock output for channel Low jitter clock is output for each channel based on the mode selection (E3,DS3 or STS-) if the CLK_EN_n bit is set in the control register or CLKOUT_EN pin is tied High. This eliminates the need for a separate clock source for the framer. NOTES:. The maximum drive capability for the clockouts is 6 ma. 45 CLKOUT_EN I Clock Output Enable in Single Frequency Mode: Tie this pin High to enable the output clocks via the CLKOUT pins. 8

11 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... CONTROL AND ALARM INTERFACE PIN # SIGNAL NAME TYPE DESCRIPTION MRING_ MRING_ MTIP_ MTIP_ DMO_ DMO_ RLOS_ RLOS_ RLOL_ RLOL_ I Monitor Ring Input - Channel : Monitor Ring Input - Channel : The bipolar line output signal from TRING_n is connected to this pin via a 27 Ω resistor to check for line driver failure. NOTE: This pin is internally pulled "High". I Monitor Tip Input - Channel : Monitor Tip Input - Channel : The bipolar line output signal from TTIP_n is connected to this pin via a 27- ohm resistor to check for line driver failure. NOTE: This pin is internally pulled "High". O Drive Monitor Output - Channel : Drive Monitor Output - Channel : If MTIP_n and MRING_n has no transition pulse for 28 ± 32 TxCLK_n cycles, DMO_n goes High to indicate the driver failure. DMO_n output stays High until the next AMI signal is detected. O Receive Loss of Signal Output Indicator - Channel : Receive Loss of Signal Output Indicator - Channel : This output pin toggles "High" if the receiver has detected a Loss of Signal Condition. The criteria for declaring /clearing an LOS Condition depends upon whether it is operating in the E3 or STS-/DS3 Mode. O Receive Loss of Lock Output Indicator - Channel : Receive Loss of Lock Output Indicator - Channel : This output pin toggles "High" if a Loss of Lock Condition is detected. LOL (Loss of Lock) condition occurs if the recovered clock frequency deviates from the Reference Clock frequency (available at either E3CLK or DS3CLK or STS- CLK input pins) by more than.5%. RXA **** External Resistor of 3 K Ω ± %. Should be connected between RxA and RxB for internal bias. 2 RXB **** External Resistor of 3K Ω ±%. Should be connected between RxA and RxB for internal bias. 98 ICT I In-Circuit Test Input: Setting this pin "Low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. For normal operation, tie this pin "High". NOTE: This pin is internally pulled High". 96 TEST **** Factory Test Pin NOTE: This pin must be connected to GND for normal operation. 9

12 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... CONTROL AND ALARM INTERFACE 28 LOSMUT/ INT 4 LLB_ 22 LLB_ 5 RLB_ 2 RLB_ I/O Hardware Mode: MUTE-upon-LOS Enable Input Host Mode: Interrupt Ouput: In Hardware Mode, setting pin High configures all the channels to Mute the recovered data on the RPOS_n and RNEG_n whenever one of the channels declares an LOS condition. RPOS_n and RNEG_n outputs are pulled Low. Muting of the output data can be configured/controlled on a per channel basis in Host Mode. NOTE: If the XRT73L2M is configured in HOST mode, this pin functions as INT pin (please refer to the pin description for the Microprocessor Interface). I Local Loop-back - Channel : Local Loop-back - Channel : This input pin along with RLB_n configures different Loop-Back modes. A "High" on this pin with RLB_n set to "Low" configures Channel_n to operate in the Analog Local Loop-back Mode. A "High" on this pin with RLB_n set to "High" configures Channel_n to operate in the Digital Local Loop-back Mode. NOTE: This input pin is ignored and should be connected to GND if operating in the HOST Mode. I Remote Loop-back - Channel : Remote Loop-back - Channel : This input pin along with LLB_n configures different Loop-Back modes. A "High" on this pin with LLB_n set to Low" configures Channel_n to operate in the Remote Loop-back Mode. A "High" on this pin with LLB_n set to "High" configures Channel_n to operate in the Digital Local Loop-back Mode. RLB_n LLB_n Loopback Mode Normal Operation Analog Local Remote Digital NOTE: This input pin is ignored and should be connected to GND when operating in the HOST Mode.

13 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... MODE SELECT PIN # SIGNAL NAME TYPE DESCRIPTION 2 24 E3_ E3_ I E3 Mode Select Input A "High" on this pin configures in E3 mode. A "Low" on this pin configures in either STS- or DS3 mode depending on the settings on pins 3 and 23.. NOTES:. This pin is internally pulled down 2. This pin is ignored if configured to operate in HOST mode STS/DS3 _ STS/DS3 _ I STS-/DS3 Select Input A High on these pins configures in STS- mode. A Low on these pins configures in DS3 mode. These pins are ignored if the E3_n pins are set to High. NOTES:. This pin is internally pulled down 2. This pin is ignored if configured to operate in HOST mode. 26 HOST/HW I Host/Hardware Mode: Tie this pin High to configure in Host mode and Low for Hardware mode. SR/DR I Single-Rail/Dual-Rail Select: Setting this High configures both the Transmitter and Receiver to operate in Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In Single-rail mode, TNEG_n pin should be grounded. Setting this Low configures both the Transmitter and Receiver to operate in Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder. NOTE: This pin is internally pulled down. MICROPROCESSOR SERIAL INTERFACE - (HOST MODE) PIN # SIGNAL NAME TYPE DESCRIPTION 29 CS RxCLKINV 3 SCLK TxCLKINV I I Microprocessor Serial Interface - Chip Select Tie this Low to enable the communication with the Microprocessor Serial Interface. NOTE: If configured in Hardware Mode, this pin functions as RxClkINV. Serial Interface Clock Input The data on the SDI pin is sampled on the rising edge of this signal. Additionally, during Read operations the Microprocessor Serial Interface updates the SDO output on the falling edge of this signal. NOTE: If configured in Hardware Mode, this pin functions as TxClkINV.

14 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... MICROPROCESSOR SERIAL INTERFACE - (HOST MODE) PIN # SIGNAL NAME TYPE DESCRIPTION 3 SDI RxON 27 SDO RxMON I I/O Serial Data Input: Data is serially input through this pin. The input data is sampled on the rising edge of the SClk.. NOTES:. This pin is internally pulled down 2. If configured in Hardware Mode, this pin functions as RxON. Serial Data Output: This pin serially outputs the contents of the specified Command Register during Read Operations. The data is updated on the falling edge of the SClk and this pin is tri-stated upon completion of data transfer. NOTE: If configured in Hardware Mode, this pin functions as RxMON. 97 RESET I Register Reset: Setting this input pin "Low" causes to reset the contents of the Command Registers to their default settings and default operating configuration NOTE: This pin is internally pulled up. 28 INT LOSMUT I/O INTERRUPT Output: A transition to Low indicates that an interrupt has been generated. The interrupt function can be disabled by setting the interrupt enable bit to in the Channel Control Register. NOTES:. In Hardware mode, this pin functions as LOSMUT. 2. This pin will remain asserted Low until the interrupt is serviced. ANALOG POWER AND GROUND PIN # SIGNAL NAME TYPE DESCRIPTION 84 TxAVDD_ **** Transmitter Analog 3.3 V ± 5% VDD - Channel 43 TxAVDD_ **** Transmitter Analog 3.3 V ± 5% VDD - Channel 83 TxAGND_ **** Transmitter Analog GND - Channel 44 TxAGND_ **** Transmitter Analog GND - Channel 6 RxAVDD_ **** Receiver Analog 3.3 V ± 5% VDD - Channel 2 RxAVDD_ **** Receiver Analog 3.3 V ± 5% VDD - Channel 7 RxAGND_ **** Receiver Analog GND - Channel_ 9 RxAGND_ **** Receive Analog GND - Channel 86 AVDD_ **** Analog 3.3 V ± 5% VDD - Channel 4 AVDD_ **** Analog 3.3 V ± 5% VDD - Channel 85 AGND_ **** Analog GND - Channel 42 AGND_ **** Analog GND - Channel 3 AVDD **** Analog 3.3 V ± 5% VDD 2

15 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... ANALOG POWER AND GROUND PIN # SIGNAL NAME TYPE DESCRIPTION AGND **** Analog GND 4 AGND **** Analog GND 5 AGND **** Analog GND 6 AGND **** Analog GND DIGITAL POWER AND GROUND PIN # SIGNAL NAME TYPE DESCRIPTION 69 TxVDD_ **** Transmitter 3.3 V ± 5% VDD Channel 57 TxVDD_ **** Transmitter 3.3 V ± 5% VDD Channel 68 TxGND_ **** Transmitter GND - Channel 58 TxGND_ **** Transmitter GND - Channel 89 RxDVDD_ **** Receiver 3.3 V ± 5% VDD - Channel 38 RxDVDD_ **** Receiver 3.3 V ± 5% VDD - Channel 9 RxDGND_ **** Receiver Digital GND - Channel 37 RxDGND_ **** Receiver Digital GND - Channel 87 DVDD_ **** 3.3 V ± 5% VDD - Channel 4 DVDD_ **** 3.3 V ± 5% VDD - Channel DGND_ **** Digital GND - Channel 39 DGND_ **** Digital GND - Channel 6 DVDD **** Digital VDD 3.3.v ± 5% 62 DVDD **** Digital VDD 3.3.v ± 5% 67 DVDD **** Digital VDD 3.3.v ± 5% 59 DGND **** Digital GND 64 DGND **** Digital GND 65 DGND **** Digital GND 3

16 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV.... ELECTRICAL CHARACTERISTICS TABLE : ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER MIN MAX UNITS COMMENTS V DD Supply Voltage V Note V IN Input Voltage at any Pin V Note I IN Input current at any pin ma Note S TEMP Storage Temperature C Note A TEMP Ambient Operating Temperature C linear airflow ft./min ThetaJA Thermal Resistance 35 C/W linear air flow ft/min ThetaJC 6 C/W M LEVL Exposure to Moisture 5 level EIA/JEDEC JESD22-A2-A ESD ESD Rating 2 V Note 2 NOTES:. Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair reliability of the device. 2. ESD testing method is per MIL-STD-883D,M TABLE 2: DC ELECTRICAL CHARACTERISTICS: SYMBOL PARAMETER MIN. TYP. MAX. UNITS DV DD Digital Supply Voltage V AV DD Analog Supply Voltage V I CC Supply current requirement ma P DD Power Dissipation 7 9 mw V IL Input Low Voltage.8 V V IH Input High Voltage V V OL Output Low Voltage, I OUT = - 4mA.4 V V OH Output High Voltage, I OUT = 4 ma 2.4 V I L Input Leakage Current ± µa C I Input Capacitance pf C L Load Capacitance pf NOTES:. Not applicable for pins with pull-up or pull-down resistors. 2. The Digital inputs and outputs are TTL 5V compliant. 4

17 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV TIMING CHARACTERISTICS FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT73L2M (DUAL-RAIL DATA) TxPOS TPData Terminal Equipment (E3/DS3 or STS- Framer) TxNEG TxLineClk TNData TxClk Transmit Logic Block Exar E3/DS3/STS- LIU FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING t RTX t FTX TxCLK TPOS or TNEG t TSU t THO TTIP or TRING t TDY SYMBOL PARAMETER MIN TYP MAX UNITS TxClk Duty Cycle E3 DS3 STS % MHz MHz MHz t RTX TxCLK Rise Time (% to 9%) 4 ns t FTX TxCLKFall Time (% to 9%) 4 ns t TSU TPOS/TNEG to TxCLK falling set up time 3 ns t THO TPOS/TNEG to TxCLK falling hold time 3 ns t TDY TTIP/TRINGto TxCLK rising propagation delay time 8 ns 5

18 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... FIGURE 5. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING t RRX t FRX RxCLK t LCVO LCV RPOS or RNEG t CO SYMBOL PARAMETER MIN TYP MAX UNITS RxClk Duty Cycle E3 DS3 STS % MHz MHz MHz t RRX RxCLK rise time (% o 9%) 2 4 ns t FRX RxCLKfalling time (% to 9%) 2 4 ns t CO RxCLKto RPOS/RNEG delay time 4 ns t LCVO RxCLK to rising edge of LCV output delay 2.5 ns FIGURE 6. TRANSMIT INTERFACE CIRCUIT FOR E3, DS3 AND STS- RATES TTIP(n) R 3.6Ω +% TxPOS(n) TxNEG(n) TxLineClk(n) TPOS(n) TNEG(n) TxCLK(n) : R3 75Ω 3 kω + % RxB RxA TRING(n) 3.6Ω + % R2 XRT73L2M (nly one channel shown) 6

19 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV LINE SIDE CHARACTERISTICS: 3. E3 LINE SIDE PARAMETERS: The XRT73L2M line output at the transformer output meets the pulse shape specified in ITU-T G.73 for Mbits/s operation. The pulse mask as specified in ITU-T G.73 for Mbits/s is shown in Figure 7. FIGURE 7. PULSE MASK FOR E3 ( MBITS/S) INTERFACE AS PER ITU-T G.73 7 ns ( ) V = % 8.65 ns Nominal Pulse 5% 4.55ns % % % 2% 2.ns ( ) TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS PARAMETER MIN TYP MAX UNITS TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (Measured at secondary of the transformer).9.. V pk Transmit Output Pulse Amplitude Ratio Transmit Output Pulse Width ns RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) 2 feet Interference Margin -2-6 db Jitter Jitter Frequency 8KHz.5.3 UI PP Signal level to Declare Loss of Signal -35 db Signal Level to Clear Loss of Signal -5 db Occurence of LOS to LOS Declaration Time 255 UI Termination of LOS to LOS Clearance Time 255 UI NOTE: The above values are at TA = 25 C and V DD = 3.3 V± 5%. 7

20 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS- APPLICATIONS STS- Pulse Template.2.8 Normalized Amplitude.6.4 Lower Curve Upper Curve Time, in UI TABLE 4: STS- PULSE MASK EQUATIONS TIME IN UNIT INTERVALS NORMALIZED AMPLITUDE LOWER CURVE -.85 < T < < T < < T < UPPER CURVE -.85 < T < < T <.26 π T + sin π T + sin < T < x e -2.4[T-.26] 8

21 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... TABLE 5: STS- TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) NOTE: The above values are at TA = 25 C and V DD = 3.3 V ± 5%. PARAMETER MIN TYP MAX UNITS TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = ) Transmit Output Pulse Amplitude (measured with TxLEV = ).75 V pk.98 V pk Transmit Output Pulse Width ns Transmit Output Pulse Amplitude Ratio.9.. RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) 9 feet Jitter Jitter Frequency 4 KHz.5.79 UI pp FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 DS3 Pulse Template.2.8 Normalized Amplitude.6.4 Lower Curve Upper Curve Time, in UI

22 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... TABLE 6: DS3 PULSE MASK EQUATIONS TIME IN UNIT INTERVALS NORMALIZED AMPLITUDE LOWER CURVE -.85 < T < < T < < T < UPPER CURVE -.85 < T < < T <.36 π T + sin π T + sin < T < x e -.84[T-.36] TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) NOTE: The above values are at TA = 25 C and V DD = 3.3V ± 5%. PARAMETER MIN TYP MAX UNITS TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = ) Transmit Output Pulse Amplitude (measured with TxLEV = ).75 V pk. V pk Transmit Output Pulse Width ns Transmit Output Pulse Amplitude Ratio.9.. RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) 9 feet Jitter 4 KHz (Cat II).6 UI pp 2

23 xr TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT XRT73L2M REV... FIGURE. MICROPROCESSOR SERIAL INTERFACE STRUCTURE CS SClk SDI R/W A A A2 A3 A4 A5 D D D2 D3 D4 D5 D6 D7 SDO High Z D D D2 D3 D4 D5 D6 D7 High Z FIGURE. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE t 28 CS t 2 t 26 SCLK t 24 t25 t27 t 22 t 23 SDI R/W A A CS SCLK t 29 t 3 t 32 t 3 SDO D D D2 D7 Hi-Z SDI Hi-Z TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( T A = 25 C, V DD =3.3V± 5% AND LOAD = PF) SYMBOL PARAMETER MIN. TYP. MAX UNITS t 2 CS Low to Rising Edge of SClk 5 ns t 22 SDI to Rising Edge of SClk 5 ns t 23 SDI to Rising Edge of SClk Hold Time 5 ns 2

24 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( T A = 25 C, V DD =3.3V± 5% AND LOAD = PF) SYMBOL PARAMETER MIN. TYP. MAX UNITS t 24 SClk "Low" Time 25 ns t 25 SClk "High" Time 25 ns t 26 SClk Period 5 ns t 27 Falling Edge of SClk to rising edge of CS ns t 28 CS "Inactive" Time 5 ns t 29 Falling Edge of SClk to SDO Valid Time 2 ns t 3 Falling Edge of SClk to SDO Invalid Time ns t 3 Rising edge of CS to High Z ns t 32 Rise/Fall time of SDO Output 5 ns 22

25 xr XRT73L2M REV... TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT FUNCTIONAL DESCRIPTION: Figure shows the functional block diagram of the device. Each channel can be independently configured either by Hardware Mode or by Host Mode to support E3, DS3 or STS- modes. A detailed operation of each section is described below. Each channel consists of the following functional blocks: 4. THE TRANSMITTER SECTION: The Transmitter Section, within each Channel, accepts TTL/CMOS level signals from the Terminal Equipment in selectable data formats. Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. Figures 7, 8 and 9 illustrate the pulse template requirements. Encode the un-encoded NRZ data into either B3ZS format (for DS3 or STS-) or HDB3 format (for E3) and convert to pulses with shapes and width that are compliant with industry standard pulse template requirements. Figures 7, 8 and 9 illustrate the pulse template requirements. In Single-Rail or un-encoded Non-Return-to-Zero (NRZ) mode, data is input via TPOS_n pins while TNEG_n pins must be grounded. The NRZ or Single-Rail mode is selected when the SR/DR input pin is High (in Hardware Mode) or bit of channel control register is (in Host Mode). Figure 2 illustrates the Single-Rail or NRZ format. FIGURE 2. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) Data TPData TxClk In Dual-Rail mode, data is input via TPOS_n and TNEG_n pins. TPOS_n contains positive data and TNEG_n contains negative data. The SR/DR input pin = Low (in Hardware Mode) or bit of channel register = (in Host Mode) enables the Dual-Rail mode. Figure 3 illustrates the Dual-Rail data format. FIGURE 3. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED) Data TPData TNData TxClk 23

26 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV TRANSMIT CLOCK: The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = MHz, DS3 = MHz or STS- = 5.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 5% duty cycle clock to the pulse shaping circuit. This allows a 3% to 7% duty cycle Transmit Clock to be supplied B3ZS/HDB3 ENCODER: When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS format (for either DS3 or STS-) or HDB3 format (for E3) B3ZS Encoding: An example of B3ZS encoding is shown in Figure 4. If the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either BV or V, where B refers to Bipolar pulse that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and V refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of BV or V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses. This avoids the introduction of a DC component into the line signal. FIGURE 4. B3ZS ENCODING FORMAT TClk TPDATA Line Signal V V B V B V HDB3 Encoding: An example of the HDB3 encoding is shown in Figure 5. If the HDB3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either V or BV pattern. The substitution code is made in such a way that an odd number of bipolar (B) pulses exist between any consecutive V pulses. This avoids the introduction of DC component into the analog signal. FIGURE 5. HDB3 ENCODING FORMAT TClk TPDATA Line Signal V V B V B NOTES:. When Dual-Rail data format is selected, the B3ZS/HDB3 Encoder is automatically disabled. 2. In Dual-Rail format, the Bipolar Violations in the incoming data stream is converted to valid data pulses. 3. Encoder and Decoder is enabled only in Single-Rail mode. 24

27 xr XRT73L2M REV... TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT 4..3 TRANSMIT PULSE SHAPER: The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark Inversion (AMI) pulse that meet the industry standard mask template requirements for STS- and DS3. See Figures 8 and 9. For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped pulse with very little slope. This is illustrated in Figure 7. The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can either be disabled or enabled by setting the TxLEV_n input pin High or Low (in Hardware Mode) or setting the TxLEV_n bit to or in the control register (in Host Mode). For DS3/STS- rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that transmit pulse template requirements are met at the Cross-Connect system. The distance between the transmitter output and the Cross-Connect system can be between to 45 feet. For E3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no Cross-Connect system pulse template requirements, the Transmit Build Out Circuit is always disabled Guidelines for using Transmit Build Out Circuit: If the distance between the transmitter and the DSX3 or STSX-, Cross-Connect system, is less than 225 feet, enable the Transmit Build Out Circuit by setting the TxLEV_n input pin Low (in Hardware Mode) or setting the TxLEV_n control bit to (in Host Mode). If the distance between the transmitter and the DSX3 or STSX- is greater than 225 feet, disable the Transmit Build Out Circuit Interfacing to the line: The differential line driver increases the transmit waveform to appropriate level and drives into the 75Ω load as shown in Figure Transmit Drive Monitor: This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on the line or a defective line driver. To activate this function, connect MTIP_n pins to the TTIP_n lines via a 27 Ω resistor and MRing_n pins to TRING_n lines via 27 Ω resistor as shown in Figure 6. FIGURE 6. TRANSMIT DRIVER MONITOR SET-UP. TTIP(n) R 3.6Ω +% TxPOS(n) TxNEG(n) TxLineClk(n) 3kΩ + % TPOS(n) TNEG(n) TxCLK(n) RxB RxA TRING(n) MTIP(n) MRING(n) R2 3.6Ω + % R4 27Ω R5 27Ω : R3 75Ω XRT73L2M (nly one channel shown) 25

28 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... When the MTIP_n and MRING_n are connected to the TTIP_n and TRING_n lines, the drive monitor circuit monitors the line for transitions. The DMO_n (Drive Monitor Output) will be asserted Low as long as the transitions on the line are detected via MTIP_n and MRING_n. If no transitions on the line are detected for 28 ± 32 TxClk_n periods, the DMO_n output toggles High and when the transitions are detected again, DMO_n toggles Low. NOTES:. The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter. 2. With TxMON pin High, MTIP and MRING will be internally connected to TTIP and TRING for self-monitoring TRANSMITTER SECTION ON/OFF: The transmitter section of each channel can either be turned on or off. To turn on the transmitter, set the input pin TxON to High (in Hardware Mode) or in Host Mode set the TxON_n control bits and tie the TxON pins High When the transmitter is turned off, TTIP_n and TRING_n are tri-stated. NOTES:. This feature provides support for Redundancy. 2. If configured in Host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, setting the TxON_n control bits transfers the control to TxON pins. 5. THE RECEIVER SECTION: This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses. 5.. AGC/EQUALIZER: The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 3 db. The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation up to 9 feet of coaxial cable (3 feet for E3). The Equalizer also boosts the high frequency content of the signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 5% of peak voltage to generate Positive and Negative data. The Equalizer can either be IN or OUT by setting the REQEN_n pin High or Low (in Hardware Mode) or setting the REQEN_n control bit to or (in Host Mode). RECOMMENDATIONS FOR EQUALIZER SETTINGS: The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/ STS- pulses (pulses that meet the template requirements) that has been driven through to 9 feet of cable, the Equalizer can be left IN by setting the REQEN_n pin to High (in Hardware Mode) or setting the REQEN_n control bit to (in Host Mode). However, for square-shaped pulses such as E3 or for DS3/STS- high pulses (that does not meet the pulse template requirements), it is recommended that the Equalizer be left OUT for cable length less than 3 feet by setting the REQEN_n pin Low (in Hardware Mode) or by setting the REQEN_n control bit to (in Host Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characteristics. NOTE: The results of extensive testing indicates that even when the Equalizer was left IN (REQEN_n = HIGH ), regardless of the cable length, the integrity of the E3 signal was restored properly over to 2 db cable loss at Industrial Temperature. 26

29 xr XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT REV... The Equalizer also contain an additional 2 db gain stage to provide the line monitoring capability of the resistively attenuated signals which may have 2dB flat loss. This capability can be turned on by setting the RxMON_n bits in the control register or by setting the RxMON pin High INTERFERENCE TOLERANCE: For E3 mode, ITU-T G.73 Recommendation specifies that the receiver be able to recover error-free clock and data in the presence of a sinusoidal interfering tone signal. For DS3 and STS- modes, the same recommendation is being used. Figure 7 shows the configuration to test the interference margin for DS3/STS. Figure 8 shows the set up for E3. FIGURE 7. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS- Attenuator Sine Wave Generator N to 9 feet Coaxial Cable DUT (XRT73L2M) Test Equipment Pattern Generator PRBS S DS3 = MHz STS- = MHz FIGURE 8. INTERFERENCE MARGIN TEST SET UP FOR E3. Attenuator Attenuator 2 Noise Generator PRBS N to 2 db Cable Loss DUT (XRT73L2M) Test Equipment Signal Source S TABLE 9: INTERFERENCE MARGIN TEST RESULTS MODE CABLE LENGTH (ATTENUATION) INTERFERENCE TOLERANCE E3 db - 7 db 2 db -5 db 27

30 XRT73L2M TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT xr REV... TABLE 9: INTERFERENCE MARGIN TEST RESULTS MODE CABLE LENGTH (ATTENUATION) INTERFERENCE TOLERANCE feet -6 db DS3 225 feet - 5dB 45 feet - 5dB feet - 7 db STS- 225 feet - 6 db 45 feet - 6 db 5..2 CLOCK AND DATA RECOVERY: The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the following two modes: TRAINING MODE: In the absence of input signals at RTIP_n and RRING_n pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the E3/DS3/STSCLK input pins exceed.5%, a Loss of Lock condition is declared by toggling RLOL_n output pin High (in Hardware Mode) or setting the RLOL_n bit to in the control registers. Also, the clock output on the RxClk_n pins are the same as the reference clock applied on E3/DS3/STSCLK pins. DATA/CLOCK RECOVERY MODE: In the presence of input line signals on the RTIP_n and RRING_n input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than.5%, the clock that is output on the RxClk_n out pins is the Recovered Clock signal B3ZS/HDB3 DECODER: The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or STS-) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data stream. When the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active High pulse is generated on the RLCV_n output pins to indicate line code violation. NOTE: In Single- Rail (NRZ) mode, the decoder is bypassed LOS (Loss of Signal) Detector: DS3/STS- LOS Condition: A Digital Loss of SIgnal (DLOS) condition occurs when a string of 75 ± 75 consecutive zeros occur on the line. When the DLOS condition occurs, the DLOS_n bit is set to in the status control register. DLOS condition is cleared when the detected average pulse density is greater than 33% for 75 ± 75 pulses. Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the Table.The status of the ALOS condition is reflected in the ALOS_n status control register. 28

31 xr XRT73L2M REV... TWO CHANNEL E3/DS3/STS- LINE INTERFACE UNIT RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled High and the RLOS_n bit is set to in the status control register. TABLE : THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS- APPLICATIONS) APPLICATION REQEN SETTING SIGNAL LEVEL TO DECLARE ALOS SIGNAL LEVEL TO CLEAR ALOS DS3 <7 mv >7 mv <2 mv >9 mv STS- <2 mv >9 mv <25 mv >5 mv DISABLING ALOS/DLOS DETECTION: For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Setting both ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis E3 LOS Condition: If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the LOS condition is detected. Loss of signal level is defined to be between 5 and 35 db below the normal level. If the signal drops below 35 db for 75 ± 75 consecutive pulse periods, LOS condition is declared. This is illustrated in Figure 9. FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 db -2 db LOS Signal Must be Cleared Maximum Cable Loss for E3-5dB LOS Signal may be Cleared or Declared -35dB LOS Signal Must be Declared 29