A Virtually Isolated Transformerless Off Line Power Supply

Transcription

1 Virtually Isolated Transformerless Off Line Power Supply S. OFINS, M. MNOLROU Hellenic Naval cademy Terma Hatzikyriakou, Piraeus GREEE bstract This paper describes a new method of isolation between a.c. mains and d.c. voltage output without the use of a transformer. It consists of two buck converters, connected in series, each one using a pair of two MOSFET transistors. Each pair of transistors is conducting at different time intervals, thus under the assumption that the impedance of an OFF state MOSFET is practically infinite, there is transfer of energy from the a.c side to the d.c. side without actual ohmic continuation in the circuit. If the maximum limit of the drain to source voltage is not exceeded, the power supply becomes virtually isolated, making redundant the transformer used in classic power supplies. This configuration is suitable for output powers above Watts. The proposed circuit is analysed and simulated results are derived. KeyWords: buck converter, power supply, transformer, voltage isolation, transformeless isolation, high efficiency power supply 1 Introduction Tranditionally, the isolation of a power supply is achieved by using a transformer. This paper describes an off line dc power supply which makes the large impedance of OFF state transistor MOSFETs equal the impedance between the.. and. side. The circuit consists of two buck converters, connected in series, each one using a pair of two MOSFET transistors, as shown in Fig.1. The necessity of using four transistors, makes this configuration attractive for output powers above Watts. Fig. 1 shows the basic principle of operation for this circuit. Tr 1, Tr 2, L, 8, 3 form one buck converter [1],[2], while Tr 3, Tr 4, L 8, 13, 4, form the second one. There are four repeated modes in steady state operation. MOE I Tr 1 and Tr 2 are closed with Tr 3, Tr 4 opened. apacitor 3 is charged through Tr 1 and Tr 2. MOE II Tr 1 and Tr 2 are opened with Tr 3, Tr 4 opened. urrent freewheels through L, 8, 3, keeping the voltage variation of 3 at low levels. MOE III Tr 1 and Tr 2 are opened with Tr 3, Tr 4 closed. apacitor 4 is charged through the discharging of capacitor 3 and through the energy stored in L. MOE IV Tr 1 and Tr 2 are opened with Tr 3, Tr 4 opened. urrent freewheels through 13 and L 8 keeping the load voltage variation at low levels. 2 ircuit design and operation The purpose of this design is to demonstrate the isolating principle of operation and not the production of an optimized power supply where all factors such as efficiency, optimized control, soft starting, current limiting and suitably optimized values of components are taken into account. R 3 L L 8 L 1 L 2 R Tr 1 R 1 Tr 3 R 8 1 R 2 L L R LO R E1=,1Ω 2 4 L 3 8 L 6 13 R E2 =4Ω R Tr 2 R Tr 4 R E3 =,1Ω Fig. 1. The proposed circuit ISSN: ISN:

2 The theoretical design was in the Orcad environment, the requirement being a supply fed from the mains with 23 ± 1% V RMS / Hz giving an output of 14V/14/196W. part from the standardized OR components such as the MOSFETs used (IRFP36), diodes (MUR16),the PWM control integrated circuit (SG12/2) and the bipolar transistors (46), assumed values of the resistive lossy component of the inductors and capacitors are taken into account, approaching practical values of laboratory components. The general circuit layout is shown in Fig.1. With the actual circuit developed in OR program not shown in this paper due to its complexity. Usual values of components are chosen as those used in ordinary power supplies. The use of the antiparallel diodes, 6, 9 was found necessary to minimize the voltage stress on the MOSFETs. iodes 14, 1, 1, 11 were used to block reverse currents in diodes of MOSFETs though the earth loop and power supply. 2.1 PWM ontrol The control method is based on the integraded circuit 12. The control circuit is shown in Fig.2. Here, the output is used to produce the two pulses driving the two pairs of MOSFETs (Tr 1 Tr 2 and Tr 3 Tr 4 ). The first pulse drives directly the drive circuit of Tr 3 and Tr 4 and being modulated, produces the constant load voltage. The pulse driving the other pair of input MOSFETs has a constant maximum width occupying almost % of the period which the 12 operates. This action ensures that the first buck converter always gives the maximum voltage irrespective of load conditions, with the second buck converter providing the control. The antiphase nature of the pulses is achieved via the circuit shown in Fig.3. The pulse derived from output is differentiated through and R 9. R 1 and R 11 bring the amplitude of this pulse at appropriate voltage levels, feeding the clear input of the counter 74H193. This zeroes all outputs of the counter. The clocking of this counter is provided by the oscillator output of the 12 circuit. The oscillator output is independent of the 12 control circuit and always gives two pulses of short duration during one period, so that even if output is zeroed due to current limiting or other reasons, the oscillator output will provide the inverter 74H4 with a pulse. The inverter output is fed to the UP count of the counter, driving the output of the counter high. Here, it must be noted that the clear input of the counter, needs only to be applied once, since odd number of pulses will drive output of the counter high and even number of pulses will drive output low. N OUTPUT of PWM control Oscillator output R 9 R 1 R 11 From power supply of PWM M K UP OWN LR LO Fig.3. ntiphase circuit Fig. 4 shows waveforms in various parts of the antiphase circuit O O L From output of power supply 17Vdc Oscillator output 16 4 OS VIN 13 SYN T RT OUT 11 ERR OUT 14 ERR+ IS STRT SG K L M 4.26ms 4.28ms 4.3ms 4.32ms 4.34ms 4.36ms 4.38ms 4.4ms 4.42ms 4.44ms 4.46ms 4.48ms 4.ms 4.2ms 4.4ms V(U1:OUT) V(R34:2) V(R7:2) V(U2:Q) Fig. 4. Voltage waveforms at various points of the antiphase circuit. N GN Transistor drive circuits 7Vdc Fig.2. PWM control circuit The requirement is to drive the MOSFETs through four isolated circuits, two for every MOSFET pair. The authors recommend the use of the integraded circuit HPL316J. Two identical drive circuits were designed as the one shown in Fig.. Fig. 6 shows the waveforms of ISSN: ISN:

3 the pulses applied to the drive circuits and Gate to Source voltages of transistors Tr 1 and Tr 3. 16V 12V Vout(V) 8V 1Ω 4V 1Ω 3Ω V s 1ms 2ms 3ms 4ms ms 6ms 7ms 8ms 9ms 1ms Ω 46 1Ω 3Ω Fig.7. Power supply output voltage. Fig. 8 shows that the voltage appearing across Tr 1 is less than 4Volts. Figures 9,1,11 show the voltages appearing in the other three MOSFETs where the voltages are less than 3Volts. 2Ω Ω 46 Fig. MOSFETs drive circuit VS(Tr1)(V) V s 4 1ms 2ms 3ms 4ms ms 6ms 7ms 8ms 9ms1ms Fig.8. rain to source voltage of Tr m 2.22m 2.24m 2.26m 2.28m 2.3m 2.32m 2.34m 2.36m 2.38m 2.4m 2.42m 2.44ms 2.46m 2.48m V(3:2) V(U2:Q V(M17:g,L6:1 V(M16:g,L3:1 2.3 Snubbers The snubber used, is shown in Fig.1 with components 8, 7, L 4 and R. Its use was necessary due to large spikes of current flowing through the MOSFETs during switch ON. 3 Simulation results Fig.6. :Pulse input to driver of Tr 1 :V GS of Tr 1 :Pulse input to driver of Tr 3 :V GS of Tr 3 Repeated runs were made on the theoretical model with the most important parameters plotted in the following figures. Since the power supply must be operated with minimum mains voltage of 231%Volts, these figures were taken at this voltage, even though a separate waveform is taken with the mains voltage being 23+1%Volts showing the potential difference between rain and Source of the most voltage stressed MOSFET. Fig. 7 shows the output voltage of the supply with an 1 Ohm load resistance the output power being 196Watts. VS(Tr2)(V) s 1ms 2ms 3ms 4ms ms 6ms 7ms 8ms 9ms 1ms 4 3 VS(Tr3)(V ) VS(Tr4)(V) Fig.9. rain to source voltage of Tr 2. s 1ms 2ms 3ms 4ms ms 6ms 7ms 8ms 9ms 1ms Fig.1. rain to source voltage of Tr 3. s 1ms 2ms 3ms 4ms ms 6ms 7ms 8ms 9ms 1ms Fig.11. rain to source voltage of Tr 4. ISSN: ISN:

4 Fig. 12 shows the voltages across point, and output voltage showing the function of each buck converter. Fig. 13 shows the currents in Tr 3 and Tr 1, with the currents in Tr 4 and Tr 2 being identical. The current through Tr 1 is somewhat higher than expected because the circuit operation has not reached the steady state. Rise times of currents show the effect of the snubber circuits. ITr1, ITr3 () s 1ms 2ms 3ms 4ms ms 6ms 7ms 8ms 9ms 1ms Fig.12. :Voltage across points :Voltage across points :Output voltage V out (V) IRE1() IRE1() 1s 1ms 2ms 3ms 4ms ms 6ms 7ms 8ms 9ms 1ms Fig.14. urrent through R E1 1 4.ms 4.1ms 4.2ms 4.3ms 4.4ms 4.ms 4.6ms 4.7ms 4.8ms 4.9m 4.1ms Fig.1. urrent through R E1 at higher time resolution Fig. 16 shows the overall efficiency versus output power for 231% applied mains voltage with the ouput d.c. voltage being 14Volts. y making the mains voltage 23Volts, the output d.c. voltage was raised to 4Volts for possible applications of this circuit in telecommunication industry. s Fig. 17 shows, for an output power variation 4Watts, the efficiency is higher than 9%..2ms.22ms.24ms.26ms.28ms.3ms.32ms.34ms.36ms.38ms.4ms I(M17) Fig.13 :urrent in Tr 3 :urrent in Tr 1 Figs. 14 and 1 demonstrate the isolation principle of this power supply. Fig. 14 shows the current from the mains, to earth and output of the supply from starting to 1ms (current through R E1 ). Even though at steady state the current reaches peak values of ±3mperes, if seen at higher time resolution, as in Fig.1, this current is constituted from short duration (1nsec) pulses associated with the capacitive nature between rain and Source of MOSFETs during switching. The energy associated with these spikes is very small and easily filtered using commercial type filters associated with power electronic circuits. However, these spikes will not trip a leakage current relay even if remained unfiltered as the manufacturers of standard type leakage current relays have assured the authors. Efficiency n(%) P LO (W) Fig.16. Efficiency versus load power for 14V d.c output. ISSN: ISN:

5 Efficiency n(%) P LO (W) Fig.17. Efficiency versus load power for 4V d.c output. Fig. 18 shows the potential difference between rain and Source of the most voltage stressed MOSFET (Tr 1 ). The waveform was taken with the upper limit of the a.c. mains voltage being 23+1%. The voltage across it does not exceed 48Volts. The circuit operated satisfactorily, thus fulfilling the requirement of operation in the range of mains voltage 23±1% rectified voltage. This is because simultaneous conduction of primary and secondary transistors is prohibited. The maximum conduction of the primary transistors is limited to a theoretical % of the PWM cycle while the secondary transistors conduct during the other half of the cycle. So, if we assume that the a.c. mains rectified voltage is 3V, the maximum theoretical output voltage is 7Volts. Practically, assuming that the power supply has operating range of 23Vrms±1%, the PWM integrated circuit must have a dead time of at least one microsecond, allowing switching times of transistors, diodes and transistor drive circuits also assuming a switching operating frequency of khz, the maximum output voltage is practically limited to about Volts. If higher voltages are required, for example in telecommunication applications, the authors propose the a.c. line rectification circuit shown in Fig.19. v=32sinωt(v) V peak=64v VS(Tr1) m 2m 3m 4m m 6m 7m 8m 9m 1m V(M17:d,L6:1 Fig.18. rain to source voltage of Tr1. 4 onsiderations in practical applications 4.1 Protection Personnel and equipment safety is ensured by earthing the output and connecting a classic blow fuse in the ac mains. ircuit malfunctioning due to simultaneous conduction of primary and secondary transistor or shorting of the transistor will blow this fuse. The leakage current relay of the installation provides additive security. Transient mains overvoltages can be suppressed using voltage dependent resistors or other techniques. Fig.19. Mains rectification circuit for higher output voltage applications onclusion This paper describes a new method of isolation between a.c. mains and d.c. voltage output without the use of a transformer. The necessity of using four transistors, makes this configuration attractive for output powers above Watts. s the power increases, the complexity of handling the magnetizing currents and leakage reactance energy of transformers used in rival half and full bridge converters makes this circuit more attractive. The proposed cinfiguration has been presented and analysed. The results from simulation have confirmed the theoretical predictions. References: [1] Mohan, Undeland, Robbins, Power Electronics onverters, pplication and esign, John Wiley and Sons Ltd., 22. [2] Keith illings, Switchmode Power Supplies Handbook, McgrawHill, Maximum output voltage ue to the nature of buck converters, the maximum output voltage is limited to one quarter of the a.c. line ISSN: ISN: