Design and Implementation of a Sort Free K-Best Sphere Decoder

Transcription

1 Desgn and Impementaton of a Sort Free K-Best Sphere Decoder Sudp Monda, Ahmed Etaw, Member, IEEE, Chung-An Shen, and Khaed N. Saama, Member, IEEE. Abstract:- Ths paper descrbes the desgn and VLSI archtecture for a 4x4 breadth frst K-Best MIMO decoder usng a 64 QAM scheme. A nove sort free approach to path extenson, as we as quantzed metrcs resut n a hgh throughput VLSI archtecture wth ower power and area consumpton compared to state of the art pubshed systems. Functonaty s confrmed va an FPGA mpementaton on a Xnx Vrtex II Pro FPGA. Comparson of smuaton and measurements are gven and FPGA utzaton fgures are provded. Fnay, VLSI archtectura tradeoffs are expored for a syntheszed ASIC mpementaton n a 65nm CMOS technoogy. Index Terms:- MIMO, Very Large Scae Integraton, Sphere decoder, K-best, Wreess I. INTRODUCTION Mutpe Input Mutpe Output (MIMO wreess communcaton has shown great promse for future communcatons systems as they acheve very hgh spectra effcency [1]. However, practca reazatons of MIMO wreess communcaton systems have been mted by ther dffcuty of mpementaton. The maor botteneck s the computatona compexty of the Maxmum Lkehood (ML detecton probem, especay for arrays wth a arge number of transmt and receve eements. Ths reaty motvated researchers to consder other suboptma approaches for MIMO decodng, such as Zero Forcng (ZF, Mnmum Mean Square Error (MMSE, VBLAST [4] etc, a of whch vary n performance and compexty. Recenty, there has been sgnfcant research actvty n K-best Sphere decoders [],[3] as a means of achevng cose to ML soutons wth ower compexty. For ease of dscusson and to better ustrate the tradeoffs nvoved, we brefy revew the K-best Sphere decodng method. A. K-Best Sphere Decodng The K-best decodng approach reduces the MIMO detecton probem to a tree search operaton, where nodes Ths work s supported n part by the Center for Automaton Technooges and Systems (CATS under a bock grant from the New York State Foundaton for Scence, Technoogy and Innovaton (NYSTAR and by the Natona Insttute of Justce (NIJ, Department of Justce (DOJ under grant number 006-IJ-CX-K044. S. Monda s wth the Eectrca, Computers and Systems Engneerng, Rensseaer Poytechnc Insttute, Troy, NY, USA. A. Etaw and C. Shen are wth the Department of Eectrca Engneerng and Computer Scence, Unversty of Caforna at Irvne, CA e-ma: {aetaw, chungans}@uc.edu K. N. Saama s wth the Eectrca Engneerng program, Kng Abduah Unversty of Scence and Technoogy, Thuwa, Kngdom of Saud Araba. e-ma:khaed_saama@eee.org that exceed a certan metrc are pruned to reduce the search space []. Furthermore, to mantan a constant throughput, at each eve of the tree, K best nodes are seected to be expanded to the next eve. Any other nodes are dscarded. Ths process essentay nvoves two tasks. The frst task nvoves fndng the so caed center at that specfc tree eve, whe the second task nvoves fndng the parta branch metrc or cost of extenson to a node. These two tasks can be expressed as foows: 1 1- Computng the Center c = sˆ ( ˆ s = 1 s - Computng ( s c Where s denotes the tree node chosen at eve, and are functons of the specfc channe reazaton experenced by a transmtted vector. Most often, rea vaued decomposton of the channe s used, such that each compex consteaton pont can be represented as two rea consteaton ponts, and the correspondng metrc s dstrbuted over two tree eves [],[3]. The compete extenson and seecton process conssts of severa operatons; the metrc computaton for newy extended paths (path extenson, the comparson wth prevousy extended paths (path comparson and the remova of a path exceedng any pre-defned bound (path purge. The speed and power bottenecks of the K-best agorthm arses many from the parae executon of a sad operatons at each eve. A hgh throughput MIMO detector for 16 QAM has been reported n [6] and a detector pus decoder for 64 PSK system has been reported n [7]. Both empoy the K-best breadth frst agorthm to acheve a near constant throughput. However, the throughput n [6] degrades heavy wth ncreasng K due to the ncrease n the number of parae operatons requred to be executed smutaneousy. The scheme reported n [7] attempts to reduce the number of smutaneous parae operatons by ntroducng feedback from the seecton unt to the Path Extenson unt. It used the Schnorr-Euchner (SE strategy, reported n [9] to acheve ths, however, t suffers from hgh power consumpton and arge area. Aternatvey, the VLSI mpementaton of a Sphere decoder for a 4x4, 16 QAM system, reported n [8], s reatvey power and area effcent but suffers from non-unform throughput. In ths paper, we present the mpementaton of a compact, ow power K-best 4x4, 64 QAM system, that provdes the benefts assocated wth a K-best approach such as constant

2 throughput and ease of ppenng, whe mantanng ow power and area. The man contrbutons of the paper are: 1- A sort free archtecture s proposed that sgnfcanty reduces the computatona compexty nvoved n fndng and sortng the K nodes at each ayer of the tree. The paper dscusses the tradeoffs nvoved wth ths approach n terms of both the power deay product and bt error rate (BER performance. - Tradtonay, parta metrcs are computed at each node of the tree and are recomputed n fu for each new receved vector. In the proposed structure, a quantzed ook up tabe s constructed once per channe reazaton and reused to cacuate the parta resuts for each new receved vector as a set of shfts and addtons rather than mutpcatons, whch resuts n ower area and power consumpton. The paper dscusses the tradeoffs assocated wth ths approach n terms of power consumpton, BER performance and area. 3- A compact hardware archtecture based on resource sharng s proposed and mpemented targetng both an FPGA patform and an ASIC n 0.13µm technoogy. Functona verfcaton resuts run on an FPGA patform are presented and compared to the smuaton resuts to confrm performance. ASIC power and area resuts are compared to state of the art mpementatons. The remander of the paper s organzed as foows: Secton II presents a dscusson and fu anayss of a modfcaton to the Schnorr-Euchner (SE strategy, reported n [9] that resuts n a sort free approach to the K-best agorthm. Ths w be referred to as the Wnner Path Extenson (WPE method. Secton III presents the VLSI archtecture of a detector based on the WPE method, whe secton IV presents the FPGA functona verfcaton and VLSI mpementaton resuts and statstcs. The paper s concuded n secton V. II. WINNER PATH EXTENSION (WPE: A SORT FREE APPROACH The WPE technque s ustrated n Fgure 1. Instead of extendng a the chdren of a node n parae, ony the mnmum metrc chd of each node s extended. The mnmum among these s seected as the wnner and s the frst of the K-best extended paths; the parent whch produced the wnner s aowed to extend to ts next best chd, and the process s repeated, t a K paths have been extended. Ths requres ony K-1 paths to be extended for seecton of K-paths, and emnates the need for a sorter. Ths approach has been frst reported by the authors n [10] and [11], and aso ndependenty n [1] and [13]. In ths paper, we study the compexty of the WPE approach versus tradtona extenson and sortng. We propose a nove reduced cost (n terms of power and area WPE whch s used as the core of a K-Best detector and quantfy mprovement n cost and performance. Fnay, t s mportant to note that the method presented n [1] and [13] requre exact sortng among the set of frst chdren, whch s not a requrement n our proposed approach. A. Wnner Path Extenson: Compexty Tradtonay, parae path extenson s empoyed to acheve a hgh throughput at the cost of both area and power [7]. The proposed WPE approach soves the probem of sortng as dscussed prevousy; however, as shown n Fgure 1, t s a hghy sera agorthm. To estabsh a far comparson, t s mportant to study the agorthms n terms of ther Power Deay Product (PDP. To factate generatng the PDP, we defne a compexty factor (C whch ndcates the reatve compexty of a metrc operaton (.e. computng ( s c when referred to an adder or a comparson operaton. Note that addton, subtracton, comparson and purgng are assumed to have a normazed compexty of 1. Ceary C depends on the bt wdth used and the archtecture of both the metrc operaton and adder. A reasonabe vaue to assume s C=8 or 16. Ths can be ustfed as foows; If the mutpcatons requred for computng ( s c are each eght bt, sxteen add operatons (each eght bt needs to be carred out by a shft and add mutper. The atency s equa to that of eght cascaded adders. Assumng adder bypass ogc s used, f a mutpcand bt s zero, ony haf of the adders are actve at a tme (.e. assumng that a mutpcand bts have equa probabty of beng zero and one. Ths resuts n eght tmes more power consumpton than an adder and eght adder deays. Smar anayss can be carred out for dfferent adder archtectures or mutpcand ength. Hence, as dscussed C can take expected vaues between 8 and 16. Fnay, the cost of computng the mnmum among a set of K vaues s ogarthmc n K. Wth ths understandng, the PDPs for both the parae and wnner path extenson approaches can be computed for a gven K and Q, where the consteaton sze s Q. These are computed for a 64 QAM consteaton (Q=6 for the two agorthms and are presented n Fgure. As shown n the fgure the proposed extenson technque s better n terms of PDP. The power deay advantage of the WPE technque for C=8 s amost 50%, however t reduces to around 30% for C=16. Thus, as the cost of one path extenson ncreases, the advantage tends to reduce, whch n turn mpes that maxmzng the PDP gans of the WPE approach s contngent on mnmzng the cost of a path extenson. 1 K Q Q Q MINIMUM Incude n K-Best st Repace wth next chd Fgure 1 The sort free, Wnner Path Extenson approach

3 Power X Deay 6 x Parae Extenson (C=8 Wnner Extenson (C=8 Parae Extenson (C=16 Wnner Extenson (C= No. Survvor Paths (K Fgure Power Deay Product vs survvor paths B. Quantzed Path Metrc Computaton: Power and Latency Reducton The path metrc computatons requred n each path extenson step are expensve, both n terms of power and atency. To reduce the overhead assocated wth computng the path metrc ( s c, t s mportant to note that part of the computaton depends on the channe (, whe the other part depends on the receved vector. In the proposed archtecture, we use ths observaton, n addton to the structure of the QAM consteaton to construct ook up tabes (LUTs that are updated ony once per channe reazaton. These LUTs are then accessed on a per-vector bass, where quantzaton s used to ensure that the ensung operatons are pure shfts and adds rather than hgh precson mutpcatons to mnmze power consumpton. The operaton ( s c can be quantzed by takng advantage of the QAM consteaton structure, where the rea and magnary parts of a QAM consteaton can be expressed as odd ntegers. For a 64 QAM consteaton, a symbo takes the vaues p, where p { 7, 5,..,5,7}. The space between two adacent symbos s dvded nto q dvsons. The resutng computatons are sad to be q-quantzed, where m represents the nteger number of symbo offsets and n represents the fractona parts n terms of q as shown n Fgure 3. Wth ths representaton, the ncrementa metrc from α to c becomes: [( m, n β ] = = 4 ( q qmβ nβ m β 4 n β 8q mnβ where β s 1/ q. For the symbo set { 7, 5,..,5,7}, m can take ony nteger vaues from 0 through 7. Centers takng vaues ess than -9 or greater than 9 are truncated to -9 and 9 respectvey, wthout any sgnfcant oss n performance. Smary, n can take nteger vaues from 1 through q. We choose q=8 as t resuts n both the terms m β and n β takng ony 8 possbe vaues. It s cear to see that the ony vaue that requres storage s, where a other vaues can be derved by smpe shfts and adds. Ths approach eads to sgnfcant power savngs and mprovement n speed, especay when the path metrcs are represented usng a arge number of bts. As the crtca path conssts of ony one mutpexer and two adders, the atency s much reduced compared to that of cascaded mutpers. From a compexty pont of vew, the tme cost of one path extenson usng quantzed metrcs s roughy equa to tmes that of a comparson (or add operaton (as opposed to 8 or16,.e. C as defned n Secton II, s. Ths resuts n an mproved power deay product as shown n Fgure 4. It s mportant to note that the quantzed approach can be apped to both the conventona (Parae Extenson and the proposed (Wnner Path Extenson as shown n the Fgure. n n1 Zg Zag (3, Dvded nto 8 equa dvsons Center: -3.8 Canddate: 3 Two centers coser than /8 cannot be dstngushed Setup Crtca Path Computaton Crtca Path (m,n From Preprocessng MUX Quantzed Term m /q - Fgure 3 The representaton of quantzed dstance usng an ordered par Power X Deay x 106 Parae Extenson (Unquantzed Wnner Extenson (Unquantzed Parae Extenson (Quantzed Wnner Extenson (Quantzed No. Survvor Paths (K Fgure 4 PDP mprovement usng quantzed path metrc computaton C. Quantzed Metrc: Detecton Performance A MIMO detector system for a 4x4, 64 QAM consteaton was smuated usng quantzed path metrcs n order to check the performance degradaton due to nexact metrcs. A fat fadng channe s assumed wth the MIMO channe SNR as defned n [1]. From smuatons, t was observed that the performance degradaton for dfferent eves of quantzaton s seen to be neggbe (around 0.7 db at 5 db for K=8. However, for K=64, t ncreases to around db, whch s unacceptabe. To avod the oss n performance, an Expct Path Metrc Computer (EPM bock was ntroduced at the ast stage, whch computed the exact path metrcs of the K-best eaf nodes, usng mutpers. As ths metrc was computed ony at the ast stage, the power requrements were mnma. However, the ntroducton of ths stage mproved the performance of the system consderaby as detaed n Fgure 5, whch shows the Symbo Error Rates (SERs versus SNR for dfferent vaues of K. As shown n the

4 fgure, by ntroducng the EPM stage the unquantzed and the best seect for both K=8 and K=64 are on par. Fgure 5 System performance wth Expct Path Metrc computaton at the eaf nodes for K=8 and K=64 III. VLSI ARCHITECTURE The detector ce archtecture of the system s shown n Fgure 6. The two basc tasks of computng the center and computng the path metrc are carred out by the Center Cacuator (CC and the Path Metrc Computer (PM bock respectvey. Each detector ce has ts oca memory bocks, M1 and M. At the begnnng of the cyce, M1 contans the K best paths extended t 1th eve. M1 aso contans the K centers correspondng to the K paths, computed for the th eve. The extenson cyce starts wth PM extendng a the centers to ther nearest symbos and computng the correspondng path metrcs. Henceforth, at every cock cyce, a new path s extended to the th eve and wrtten to M. At the end of the extenson cyce, M contans the K best paths extended t the th eve. Before the next cyce starts, M1 and M swap ther roes, hence emnatng the need of any data transfer from one stage to the other stage. A. Dynamc Load Center Cacuator Typcay, mutpe detector ces are empoyed on a chp to acheve the requred throughput. Each detector ce processes one receved symbo; however each detector ce requres dfferent mutpcatve resources based on the tree eve t s processng. Ths can be easy understood by ookng at the expresson for the center gven by c = sˆ 1 =1 ( s sˆ. The summaton wthn the moduus operaton vares n ength wth varyng eves. Due to the constant throughput requrements t s necessary to aocate more resources to the CC for deeper eves of the tree (.e. for arger vaues of, compared to startng eves (smaer vaues of. A group of mutpers and a smpe Bderectona MUtpeXer(BMUX bocks are used to create a confgurabe CC, whch caters to the dfferent detector ces as requred. Fgure 6 shows how the three dfferent detector ces process three dfferent eves of tree, and how the BIMUX bocks smpy program the nterconnects. The proposed scheme s hghy scaabe; for processng hgher depths, one can smpy add two or more of the outputs ( CC1 out, CC out and CC3 out, to compute centers for arge tree eves. Fnay, the WPE technque aso requres the seecton of the mnmum metrc path from a set of K paths after every extenson. Ths s acheved by the MnFnder (MF bock, whch s mpemented usng a ogarthmc arrangement of K-comparators. The MF s ppened wth regsters after every comparator. IV. VLSI IMPLEMENTATION A. FPGA Impementaton and Verfcaton An FPGA mpementaton of the system utzng 6 parae detectors was carred out usng a Xnx XCVP30 devce runnng at 6.5 MHz. The expermenta resuts are shown aganst the smuaton resuts n Fgure 7. As expected, a sma performance oss due to fxed pont effects s observed. A channe entres and path metrcs were represented usng 7 bts for ntegra part and 7 bts for Center Cacuator (CC D3 D D1 Center for th eve Logarthmc Array of Comparators Mnmum Fnder (MF Mutpers CC3 CC CC1 CC CC3 CC1 CC3 CC CC1 BMUX BMUX BMUX BMUX BMUX BMUX M1 Path at -1th eve M Path Metrc Computer (PM Path at th eve BMUX BMUX BMUX BMUX BMUX MUX MUX MUX The Detector Ce DIN BMUX SEL OP1 OP If (SEL OP1 = DIN OP = 0 ese OP1 = 0 OP = DIN CC3 out CC out CC1 out The Confguraton Scheme The BMUX bock Fgure 6 The MIMO Detector Archtecture

5 fractona part. The FPGA mpementaton metrcs are presented n Tabe 1. The FPGA mpementaton requres 0.05 MBytes of RAM. Fgure 7 Performance verfcaton resuts from FPGA Tabe 1: FPGA Resource Utzaton Report Sces Fp Fops LUTs DSP Shared Avaabe Resources CC YES PM NO MF YES EPM YES ICON YES Tota B. ASIC Impementaton A chp that mpements the above mentoned functonaty was syntheszed usng TSMC standard CMOS ce brares havng 8 meta ayers (65 nm technoogy were used. Synopsys Desgn Comper area estmates and power estmates are reported n Tabe. The numbers correspond to the typca case. The frequency of operaton was set to 158 MHz at a suppy votage of 1 Vot. The area s reported n Ko Gate Equvaents (kge to normaze the dfference n technoogy, where a snge two nput NAND gate wth drve strength of one, was used for comparson. To better compare the dfferent systems a Fgure Of Mert (FOM s defned as: FOM = K. ThPut, where K s the number of nodes Area used n the K-Best approach and ThPut s the throughput n Mbps and Area s the area expressed n kge. Ths FOM can be thought of as a normazaton of the throughput n terms of the area nvested per node (K-pont nvestgated. Ceary as the number of K ponts ncrease, the area ncreases and the performance (BER mproves, typcay at a cost of reducton n throughput. From the tabe, the proposed work has the hghest FOM for K=64. For K=10 and K=5, the work n [5], [6] exhbts a better FOM. Ths s attrbuted to the fact that the syntheszed ASIC was desgned for a 64 QAM system wth K=64. Ceary smaer area and thus a hgher FOM can be acheved by targetng the ASIC for a smaer vaue of K. Furthermore, note that the presented work acheves 100 Mbps of throughput at much ower power that that reported for other archtectures. Tabe Performance Comparson Ths Work Z.Guo M. Wenk [6] S. Chen [7] [5] QAM K Th.Put Mbps Area (kge FOM Power (mw 165 Not Reported Not Reported 847 V. CONCLUSION A nove, hgh throughput, VLSI archtecture for the K-best MIMO detector system has been presented and expermentay verfed. The use of a sort free K-best engne n conuncton wth a quantzed path metrc unt yeds a hghy scaabe and power effcent archtecture as compared to state of the art approaches. REFERENCES [1] B. M. Hochwad and S. Brnk, "Achevng near-capacty on a mutpe antenna channe," IEEE Trans. Comm., vo. 51, no.3, pp , Mar 003 [] H. Vkao, B. Hassb and U. Mtra, "Sphere-constraned ML detecton for frequency-seectve channes," IEEE Trans. Comm., vo. 54, no. 7, pp , Ju 006 [3] B. Hassb and H. Vkao, "On the sphere decodng agorthm. Part I: The expected compexty," IEEE Trans. Sg. Proc., vo. 53, no. 8, pp , Aug 005 [4] J. Wang and B. Daneshrad, "Performance of near nterpoaton-based MIMO detecton for MIMO-OFDM systems," In Proc. of IEEE Wreess Comm. and Networkng Conf., pp , Mar 004 [5] Z. Guo and P. Nsson, "Agorthm and mpementaton of the K-best sphere decodng for MIMO detecton," IEEE J. Seected Areas n Comm., vo. 4, no. 3, pp , Mar 006 [6] M. Wenk et. a.,"k-best MIMO detecton VLSI archtectures achevng upto 44 Mbps," Proc. IEEE-ISCAS'06, pp , May 006 [7] S. Chen et. a. "Reaxed K-Best MIMO sgna detector desgn and VLSI Impementaton," IEEE Tran. very Large Scae Integ. (VLSI Syst., vo. 15, no. 3, pp , Mar 007 [8] A. Burg et. a., VLSI Impementaton of MIMO detecton usng the sphere decodng agorthm, IEEE J. Sod State Crcuts, vo.40, no. 7, pp , Ju 005 [9] C. P. Schnorr and M. Euchener, "Lattce bass reducton: mproved practca agorthms and sovng subset sum probems," Math Programmng, vo. 66, pp , 1994 [10] S. Monda, et. a., "Nove PSK enumeraton for effcent VLSI mpementaton of MIMO detecton," Proceedngs of IEEE Md West Symposum on Crcuts and Systems, MWSCAS'07, pp , Aug 007 [11] S. Monda, W. A and K. N. Saama, "A nove approach for K-Best MIMO detecton and ts VLSI mpementaton," Proceedngs of IEEE Internatona Symposum on Crcuts and Systems, ISCAS'08, pp , May 008 [1] M. Shabany and P. G. Guak, "The appcaton of attce-reducton to the K-Best agorthm for near-optma MIMO detecton," Proceedngs of IEEE Internatona Symposum on Crcuts and Systems, ISCAS'08, pp , May 008 [13] M. Shabany and P. G. Guak, "Scaabe VLSI archtecture for K-Best attce decoders," Proceedngs of IEEE Internatona Symposum on Crcuts and Systems, pp , May 008