Power Quality Assessment and its Enhancement in a Distribution Power System Network

Transcription

1 Doctoral Thesis Power Quality Assessment and its Enhancement in a Distribution Power System Network Priyabrat Garanayak Department of Electrical Engineering National Institute of Technology Meghalaya Shillong-7933, Meghalaya, India October 26

2 Power Quality Assessment and its Enhancement in a Distribution Power System Network A thesis submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering Submitted by Priyabrat Garanayak Roll No- P4EE2 Under the supervision of Dr. Gayadhar Panda Department of Electrical Engineering National Institute of Technology Meghalaya Shillong-7933, Meghalaya, India October 26

3 National Institute of Technology Meghalaya Department of Electrical Engineering Copyright 26 by Priyabrat Garanayak Shillong, Meghalaya Permission is hereby granted to the National Institute of Technology Meghalaya Library to reproduce a single copy of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the National Institute of Technology Meghalaya will advise potential users of the thesis of these terms. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author s prior written permission. Recommended Citation Garanayak, Priyabrat, "Power quality assessment and its enhancement in a distribution power system network." Ph.D. dissertation, Department of Electrical Engineering, National Institute of Technology Meghalaya, India, October 26.

4 Department of Electrical Engineering National Institute of Technology Meghalaya Bijni Complex, Laitumkhrah, Shillong-7933, India Dr. Gayadhar Panda Associate Professor October 28, 26 Certificate of Supervisor This is to certify that the work presented in this thesis entitled ''Power Quality Assessment and its Enhancement in a Distribution Power System Network'' by ''Priyabrat Garanayak'', Roll No. P4EE2, is a record of original research carried out by him under my supervision and guidance in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering. All help received by him from various sources have been duly acknowledged. No part of this thesis has been submitted to any institute or university in India or abroad for the award of any degree or diploma. Dr. Gayadhar Panda

5 Declaration I, Priyabrat Garanayak, Roll No. P4EE2 hereby declare that this thesis entitled ''Power Quality Assessment and its Enhancement in a Distribution Power System Network'' represents my original work carried out as a doctoral student of National Institute of Technology Meghalaya and, to the best of my knowledge, it contains no material previously published or written by another person, nor any material presented for the award of any other degree or diploma of any other university or similar institution. Any contribution made to this research by others, with whom I have worked at National Institute of Technology Meghalaya or elsewhere, is explicitly acknowledged in the thesis. I also declared that, as required by these rules and conduct, I have fully cited and referenced all material and results that are not original to this work. Priyabrat Garanayak

6 Department of Electrical Engineering National Institute of Technology Meghalaya Bijni Complex, Laitumkhrah, Shillong-7933, India October 28, 26 Approval of the Thesis Certified that the thesis entitled Power Quality Assessment and its Enhancement in a Distribution Power System Network submitted by Priyabrat Garanayak in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering Department, National Institute of Technology Meghalaya by, Supervisor Members of DC External Examiner(s) DRC Chairman, HOD of EE

7 Dedicated to my Father, Mother and Grandmother

8 Acknowledgements I would like to express my deepest gratitude to my supervisor Assoc. Prof. Dr. Gayadhar Panda not only for his guidance, criticism, encouragements and insight throughout this research but also for his continuous confidence in me, and his unforgettable and valuable contributions to my career. I am grateful to honorable Director, Prof. Dr. Dilip Kumar Saikia for his encouragement and good wishes for my research work. I am also very much obliged to Assist. Prof. Dr. Atanu Banerjee, Head of Electrical Engineering Department for providing all the possible facilities towards this work. I am especially indebted to my Doctoral Committee members, Prof. Dr. Chandan Kumar Chanda (IIEST Shibpur), Assist. Prof. Dr. Praveen Tripathy (IIT Guwahati), Assoc. Prof. Dr. Anup Dandapat, Assist. Prof. Dr. Supriyo Das and Assist. Prof. Dr. Biswajit Kar for their technical helps and valuable suggestions during the study. I am also grateful to all the faculty members of EE Department, NIT Meghalaya for their useful suggestions and encouragements. I would like to show my gratitude to Assist. Prof. Dr. Pravat Kumar Ray, NIT Rourkela for his invaluable discussion and support in the field of harmonic estimation that has been used to achieve some important goals of the research study. I would like to thank Mr. Sushanta Nath, Mr. Inventjoy Shabong, Mr. Bankit Laloo and Mr. Talatson Surong for their helpful company and technical support in carrying out experimental work. I would like to thank and acknowledge MHRD, Government of India, for the financial support and continued assistance throughout the course of my studies at the NIT Meghalaya. vii

9 I most especially appreciate the help, acceptance and advice of many individuals without whom this opportunity would never have become fruitful. Professors, staff members, present colleagues and friends of the NIT Meghalaya have been the source of inspiration and support to pursue scientific and personal growth. I wish to express my special thank to Sandeep Mishra for his companionship and cooperation throughout this research work. Finally, I would like to express my deepest gratitude to my family, particularly my brothers Satyabrat and Subrat for their love, patience, encouragement and continuous moral support. Priyabrat Garanayak viii

10 Abstract In the modern age, AC distribution systems have been experiencing high harmonic pollution due to the intensive usage of nonlinear loads especially power electronics equipment. These nonlinear loads generate harmonics which degrade the power quality of a system and may affect the communication and control system. This has raised worldwide interest in assessing and improving the power quality of a distribution system connected to nonlinear loads. The research finding described in this thesis mainly relates to two important aspects: the fast and accurate estimation algorithm to evaluate harmonic parameters of a distorted power signal, and dynamic filtering approach to improve the power quality of a system. First, the thesis focuses on accurate harmonic estimation of a distorted current signal with additive noise by applying an adaptive linear neural network and filtered-x least mean square (ADALINE-FXLMS) algorithm. With the help of this algorithm, the adaptive step-size parameter is expanded up to the upper bound limit that assists in further improvement of system stability. The performance of the proposed algorithm has been studied under several critical cases that often arise in a power system. The efficacy of the proposed algorithm is also compared with the conventional adaptive linear neural network and least mean square (ADALINE-LMS) algorithm. Subsequently, power quality enhancement of a distribution system using a shunt APF with nonlinear control strategy is investigated under various transient conditions. The exact feedback linearization technique is applied to design the controller, which allows the decoupling operation of current and voltage control loops. This strategy boosts the tracking behavior and enhances DC-link voltage regulation. Additionally, a pole placement strategy is used in the current control loop to provide fast current harmonic compensation and simplify the control scheme. The steady-state and dynamic performances of the shunt APF equipped with a nonlinear control strategy under different operating situations of source and load are demonstrated via MATLAB/Simulink environment. ix

11 Besides the power quality improvement achieved using shunt APF, it has some drawbacks of high rating inverter and DC-link capacitor. The research effort has been made to reduce the rating of APF and minimize the DC-link capacitor voltage by developing a shunt connected hybrid power filter (HPF) topology. In this study, the adopted HPF is configured by combining APF in series with 7 tth tuned shunt passive power filters (PPFs) without using a coupling transformer. An adaptive linear neural network and variable leaky least mean square (ADALINE-VLLMS) based detection algorithm is applied for extracting the sum of harmonics and reactive current from the sensed three-phase load currents. The adopted VLLMS learning principle can overcome the limitations of conventional LMS algorithm by introducing a time-varying leakage factor. Results obtained from simulation and a real-time prototype is presented to validate the effectiveness of the HPF system with ADALINE-VLLMS algorithm. Lastly, a midpoint DC-link capacitor HPF topology is adopted to suppress further the voltage stress of insulated gate bipolar transistors (IGBTs). To enhance the compensation performance of HPF system, a sliding window Fourier analysis (SWFA) technique is utilized in this research work. The novel composite current control technique utilizes SWFA based high pass filtering for determining the reference voltages and SWFA based low pass filtering for absorbing the negative sequence currents of 5 tth order harmonic. In this thesis, an additional effort has been made to evaluate the compensation effect of HPF system by using a combinational adaptive linear neural network and dynamic forgetting factor recursive least squares (ADALINE-DFFRLS) algorithm. Due to the use of dynamic forgetting factor (DFF) mechanism, the DFFRLS based weight updating rule shows faster and accurate estimation results in noisy environments than the conventional recursive least squares (RLS). The performance of the proposed ADALINE-DFFRLS estimation algorithm is compared with the ADALINE-RLS to exemplify its faster-tracking capability. Extensive simulation is carried out to show the compensating performance of the HPF system employing SWFA based proposed controller under different critical conditions. Additionally, an experimental setup is developed for validation of the proposed control strategy in the real-time using a Spartan 3A DSP processor. At the end of chapter 5, a comparative performance study of different APF configurations is made to justify the viability and effectiveness in achieving better power quality of a system under various operating conditions. x

12 Table of Contents Acknowledgement vii Abstract ix Table of Contents xi List of Figures xv List of Tables xxiii Abbreviations xxiv List of Publications xxvi Introduction. Background and problem statement.2 Review of power quality assessment 3.3 Review of power quality enhancement 6.3. Power filter configurations Development of control strategies applied to APFs.4 Research objectives 3.5 Outline of the thesis 4 2 Power System Harmonics Estimation Employing Hybrid ADALINE- FXLMS Algorithm 7 2. Introduction State-space model of a time-varying signal Architecture of ADALINE-LMS algorithm Architecture of ADALINE-FXLMS algorithm Prediction error calculation MSE function Stability analysis Computational complexity and memory load Simulation results Estimation in the presence of noise Estimation in the presence of sub- and inter-harmonics Estimation in the presence of DC decaying function 34 xi

13 2.5.4 Steady-state performance comparison Estimation of time-varying amplitude and phase Estimation in the presence of dynamic signal Experimental results Computation of estimated signals Computation of estimated amplitudes and phases Chapter summary 42 3 Power Quality Enhancement Using Shunt APF with Nonlinear Control Strategy Introduction Modelling of three-phase shunt APF Dynamic model of APF in abc reference frame Model transformation into dq reference frame Implementation of control strategies Calculation of d- and q-axis references Current control loop Voltage control loop PWM control system Simulation results Steady-state performance of APF in a system connected to voltage-source type nonlinear load Dynamic performance of APF in a system connected to currentsource type nonlinear load Response of APF to current-source type nonlinear load variation Response of APF under temporary disconnection of currentsource type nonlinear load Steady-state performance of APF: unbalanced source voltages and balanced nonlinear load Steady-state performance of APF: distorted source voltages and balanced nonlinear load Steady-state performance of APF: balanced source voltages and unbalanced nonlinear loads Steady-state performance of APF: unbalanced source voltages and unbalanced nonlinear loads Steady-state performance of APF: distorted source voltages and unbalanced nonlinear loads Chapter summary 95 xii

14 4 Power Quality Improvement Using ADALINE-VLLMS Based HPF System Introduction System configuration with control structure Harmonic detection technique 4.3. An ADALINE based detection technique VLLMS weight adaptation rule DC-link voltage control loop Simulation results Steady-state performance of HPF Response of HPF under load current variation Response of HPF under temporary disconnection of load Response of HPF under voltage sag Dynamic performance of HPF to step increase in DC-link reference voltage Steady-state performance of HPF in a system with non sinusoidal supply Experimental results Steady-state performance of HPF Dynamic performance of HPF to a load variation Chapter summary 23 5 Harmonic Elimination Using SWFA Based HPF System and Evaluation of Compensation Effect Employing ADALINE-DFFRLS Algorithm Introduction System description Control techniques for harmonic and reactive currents extraction Algorithms for parameter estimation DFFRLS weight updating rule Computational complexity Simulation results Steady-state performance of HPF system Transient performance of HPF in a system with variation of load Transient performance of HPF in a system with a temporary disconnection of load Response of HPF with a voltage sag Response of HPF with a step change of DC-link reference voltage Experimental results 54 xiii

15 5.6. Response of HPF under steady-state Response of HPF under transient Chapter summary 6 6 Conclusions and Future Work Conclusions Future work 63 References 65 xiv

16 List of Figures. Generalized structure of a distribution power system network 2.2 Classification of harmonic estimation methods 4.3 Classification of power filters topology 7 2. Functional block diagram of ADALINE-LMS algorithm Functional block diagram of ADALINE-FXLMS algorithm Actual and estimated waveforms for test signal with different SNR values Actual and estimated waveforms for fundamental with different SNR values Actual and estimated waveforms for the sum of all harmonics with different SNR values Estimated amplitude of fundamental and harmonic components for 5 db SNR Estimated phase of fundamental and harmonic components for 5 db SNR ADALINE-FXLMS estimation performance of MSEs with different SNR values Estimation in the presence of decaying DC component, sub- and inter-harmonics components Estimated amplitude and phase of sub- and inter-harmonics components for 3 db SNR Estimated parameter of the DC decaying component for 3 db SNR. (a) Magnitude II DDDD. (c) Time constant BB Comparison of robustness of estimation with different SNR values. (a) 5 tth harmonic amplitude. (b) 3 tth harmonic phase Dynamic response of signal for 3 db SNR. (a) Estimation of time-varying 7 tth harmonic amplitude. (b) Estimation of time-varying 3 rrrr harmonic phase Estimated time-varying fundamental amplitude for 3 db SNR Single-line diagram of the test system for real-time signal parameter estimation A photograph of the complete hardware setup Experimental waveforms recorded by DSO. (a) Load current. (b) Spectrum of load current Estimation of signals from a real-time data. (a) Actual and estimated signals. (b) xv

17 Estimated fundamentals. (c) Estimated sum of all harmonics. (d) Estimated MSEs Estimation of amplitude of fundamental, harmonic, sub- and inter-harmonics components from a real-time data Estimation of phase of fundamental, harmonic, sub- and inter-harmonics components from a real-time data 4 3. Main circuit configuration of three-phase shunt APF connected to nonlinear loads Calculation of inverter output voltage with respect to common node MM (vv aaaa ) and DClink capacitor current (ii dddd ), in terms of switching function (QQ aa ) Control block diagram of shunt APF Block diagram of d- and q-axis references for current control loop Control block diagram of d- and q-axis current controller of the APF Equivalent control block diagram. (a) d-axis current loop. (b) q-axis current control loop Equivalent control block diagram of voltage control loop Block diagram of PWM control system Harmonic compensation of a voltage-source type nonlinear load under steady-state condition. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II. (h) d-axis source voltage vv dd. (i) q-axis source voltage vv qq Steady-state tracking performance of current control loop. (a) d-axis APF current ii ffff. (b) d-axis refence current ii dd. (c) q-axis APF current ii ffff. (d) q-axis reference current ii qq Simulated waveforms of APF under steady-state with voltage-source type nonlinear load condition. (a) Instantaneous active power PP LL on load side. (b) Instantaneous active power PP SS on source side. (c) Instantaneous reactive power QQ LL on load side. (d) Instantaneous reactive power QQ SS on source side. (e) Power factor on load side. (f) Power factor on source side Harmonic spectra of a voltage-source type nonlinear load. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss Response of APF under the start operation, i.e. APF is switched on at tt =.4 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II Simulated waveforms under transient state, i.e. APF startup. (a) Instantaneous active power PP LL on load side. (b) Instantaneous active power PP SS on source side. (c) Instantaneous reactive power QQ LL on load side. (d) Instantaneous reactive power QQ SS on source side. (e) Power factor on load side. (f) Power factor on source side Harmonic spectra of a current-source type nonlinear load. (a) Load current ii LLLL. (b) Source current ii ssss 68 xvi

18 3.6 Dynamic performance of APF for harmonic compensation with a current-source type nonlinear load variation during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II. (h) Instantaneous active power PP LL on load side. (i) Instantaneous active power PP SS on source side. (j) Instantaneous reactive power QQ LL on load side. (k) Instantaneous reactive power QQ SS on source side. (l) Power factor on load side. (m) Power factor on source side Dynamic performance of APF for harmonic compensation with a temporarily disconnected current-source type of nonlinear load during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II. (h) Instantaneous active power PP LL on load side. (i) Instantaneous active power PP SS on source side. (j) Instantaneous reactive power QQ LL on load side. (k) Instantaneous reactive power QQ SS on source side. (l) Power factor on load side. (m) Power factor on source side Harmonic compensation of unbalanced source voltages under steady-state condition. (a)-(c) Three-phase source voltage vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (j)-(l) Three-phase APF currents ii ffff, ii ffff, ii ffff, respectively. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side Harmonic spectra under unbalanced power supply and balanced nonlinear load. (a)-(c) Three-phase source voltages vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively Harmonic compensation of distorted source voltages under steady-state condition. (a)- (c) Three-phase source voltages vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (j)-(l) Three-phase APF currents ii ffff, ii ffff, ii ffff, respectively. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side Harmonic spectra under distorted power supply and balanced nonlinear load. (a)-(c) Three-phase source voltages vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively Harmonic compensation of unbalanced nonlinear loads under steady-state condition. (a) Source voltage vv aa. (b)-(d) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (e)- (g) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (h)-(j) Three-phase APF currents ii ffff, ii ffff, ii ffff, respectively. (k) DC-link capacitor voltage vv dddd. (l) Charging current II. (m) Instantaneous active power PP LL on load side. (n) Instantaneous active power PP SS on source side. (o) Instantaneous reactive power QQ LL on load side. (p) Instantaneous reactive power QQ SS on source side. (q) Power factor on load side. (r) xvii

19 Power factor on source side Harmonic spectra under balanced power supply and unbalanced load condition. (a) Source voltage vv aa. (b)-(d) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (e)-(g) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively Harmonic compensation of unbalanced supply voltages and unbalanced nonlinear loads under steady-state condition. (a)-(c) Three-phase source voltages vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Threephase source currents ii ssaa, ii ssss, ii ssss, respectively. (j)-(l) Three-phase APF currents ii ffff, ii ffff, ii ffff, respectively. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side Harmonic spectra under unbalanced power supply and unbalanced loads. (a)-(c) Three-phase source voltages vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively Harmonic compensation of distorted supply voltages and unbalanced nonlinear loads under steady-state condition. (a)-(c) Three-phase source voltage vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Threephase source currents ii ssss, ii ssss, ii ssss, respectively. (j)-(l) Three-phase APF currents ii ffff, ii ffff, ii ffff, respectively. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side Harmonic spectra under distorted power supply and unbalanced nonlinear loads. (a)- (c) Three-phase source voltages vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively Main circuit configuration and control block diagrams. (a) Structure of three-phase HPF topology. (b) A DC-link voltage control loop, current control loops and PWM control loops Functional block diagram of ADALINE-VLLMS based reference signal generation Waveforms of HPF under steady-state. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) DC-link reference current II. (h) Instantaneous active power PP LL on load side. (i) Instantaneous active power PP SS on source side. (j) Instantaneous reactive power QQ LL on load side. (k) Instantaneous reactive power QQ SS on source side. (l) Power factor on load side. (m) Power factor on source side Steady-state waveforms of HPF. (a) Reference voltage vv rrrrrrrr. (b) Triangular carrier xviii

20 wave vv tttttt. (c) Switching signal gg aa for IGBT SS aa. (d) switching signal gg aa for IGBT SS aa Harmonic spectra. (a) Load current ii LLLL. (b) Source current ii ssss Dynamic performance of HPF with a % increase in load current during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side Dynamic performance of HPF under no-load condition during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side 4.8 Dynamic performance of HPF under supply voltage sag during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side Response of HPF with increase in DC-link reference voltage during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side 4 4. Steady-state performance of HPF with non sinusoidal source voltages. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DClink capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side 6 4. Harmonic spectra. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss Photograph of experimental setup for implementing the proposed algorithm Experimental waveforms under steady-state condition (all plots XX aaaaaaaa =. ss/dddddd). (a) Source voltages (vv aa, vv bb, vv cc ) YY aaaaaaaa = VV/dddddd. (b) Load currents (ii LLLL, ii LLLL, ii LLLL ) YY aaaaaaaa = 5 AA/dddddd. (c) Source currents (ii ssss, ii ssss, ii ssss ) YY aaaaaaaa = 5 AA/dddddd. (d) Compensating currents (ii ffff, ii ffff, ii ffff ) YY aaaaaaaa = 5 AA/dddddd. (e) DC-link capacitor voltage (VV dddd ) YY aaaaaaaa = 25 VV/dddddd and DC-link reference current (II ) YY aaaaaaaa = 5 AA/dddddd. (f) Top-to-bottom plots source voltage (vv aa ) YY aaaaaaaa = 2 VV/dddddd, source current (ii ssss ) YY aaaaaaaa = 5 AA/dddddd, load current (ii LLLL ) YY aaaaaaaa = AA/dddddd, HPF current (ii ffff ) YY aaaaaaaa = 5 AA/dddddd, with HPF 2 xix

21 4.4 Harmonic spectra. (a) FFT of load current (ii LLLL ). (b) THD of load current (ii LLLL ). (c) FFT of source current (ii ssss ). (d) THD of source current (ii ssss ) Experimental waveforms under transient condition (all plots XX aaaaaaaa =.25 ss/ dddddd). (a) and (b) Top-to-bottom plots source voltage (vv aa ) YY aaaaaaaa = 2 VV/dddddd, source current (ii ssss ) YY aaaaaaaa = AA/dddddd, load current (ii LLLL ) YY aaaaaaaa = AA/dddddd, filter current (ii ffff ) YY aaaaaaaa = AA/dddddd with increase the load from.5 kw to kw and vice versa, respectively.(c)-(d) Top-to-bottom plots load current (ii LLLL ) YY aaaaaaaa = AA/dddddd, source current (ii ssss ) YY aaaaaaaa = AA/dddddd, DC-link capacitor voltage (VV dddd ) YY aaaaaaaa = VV/dddddd, with increase the load from.5 kw to kw and vice versa, respectively Main circuit description and control block diagrams. (a) Configuration of three-phase four-wire midpoint DC-link capacitor HPF topology. (b) Harmonic parameter estimation, reference signal calculation and switching signal generation Block diagram of LPF based conventional and SWFA based proposed control techniques for voltage references generation SWFA based fundamental component extraction ADALINE-DFFRLS for estimation of fundamental and harmonic components Steady-state performance of HPF using LPF and SWFA based extraction methods. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) and (d) Source current ii ssss with conventional and proposed controllers respectively. (e) and (f) HPF current ii ffff with conventional and proposed controllers respectively. (g) and (h) DC-link capacitor voltage vv dddd with conventional and proposed controllers respectively. (i) and (j) DClink capacitor voltage vv dddd2 with conventional and proposed controllers respectively. (k) and (l) DC balance current II with conventional and proposed controllers respectively. (m) and (n) DC loss current II 2 with conventional and proposed controllers respectively Response of HPF under steady-state. (a) d-axis transformed source current (ii ssss ). (b) and (c) d-axis fundamental DC current (ii ssss,dddd ) with conventional and proposed controllers respectively. (d) q-axis transformed source current (ii ssss ). (e) and (f) q-axis fundamental DC current (ii ssss,dddd ) with conventional and proposed controllers respectively Response of HPF under steady-state. (a) Instantaneous active power PP LL on the load side. (b) and (c) Instantaneous active power PP SS on source side with conventional and proposed controllers respectively. (d) Instantaneous reactive power QQ LL on load side. (e) and (f) Instantaneous reactive power QQ SS on source side with conventional and proposed controllers respectively. (g) Power factor on the load side. (h) and (i) Power factor on source side with conventional and proposed controllers respectively Harmonic spectra. (a) Load current ii LLLL. (b) Source current ii ssss with conventional controller. (c) Source current ii ssss with proposed controller Estimated amplitudes of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column), by using ADALINE-RLS and ADALINE- xx

22 DFFRLS estimation algorithms Estimated phases of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column), by using ADALINE-RLS and ADALINE-DFFRLS estimation algorithms Transient performance of HPF to a % increase in load current during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss with conventional controller. (d) Source current ii ssss with proposed controller. (e) and (f) HPF current ii ffff with conventional and proposed controllers respectively. (g) and (h) DC-link capacitor voltage vv dddd with conventional and proposed controllers respectively. (i) and (j) DC-link capacitor voltage vv dddd2 with conventional and proposed controllers respectively. (k) and (l) DC balance current II with conventional and proposed controllers respectively. (m) DC loss current II 2 with conventional controller. (n) DC loss current II 2 with proposed controller. (o) Instantaneous active power PP LL on load side. (p) and (q) Instantaneous active power PP SS on source side with conventional and proposed controllers respectively. (r) Instantaneous reactive power QQ LL on load side. (s) and (t) Instantaneous reactive power QQ SS on source side with conventional and proposed controllers respectively. (u) Power factor on load side. (v) and (w) Power factor on source side with conventional and proposed controllers Harmonic spectra. (a) Load current ii LLLL. (b) and (c) Source current ii ssss with conventional and proposed controllers, respectively Response of HPF under temporarily disconnected load during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) and (f) DC-link capacitor voltages vv dddd and vv dddd2, respectively. (g) DC balance current II. (h) DC loss current II 2. (i) Instantaneous active power PP LL on load side. (j) Instantaneous active power PP SS on source side. (k) Instantaneous reactive power QQ LL on load side. (l) Instantaneous reactive power QQ SS on source side. (m) Power factor on load side. (n) Power factor on source side Transient performances of HPF under supply voltage sag during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) and (f) DC-link capacitor voltages vv dddd and vv dddd2, respectively. (g) DC balance current II. (h) DC loss current II 2. (i) Instantaneous active power PP LL on load side. (j) Instantaneous active power PP SS on source side. (k) Instantaneous reactive power QQ LL on load side. (l) Instantaneous reactive power QQ SS on source side. (m) Power factor on load side. (n) Power factor on source side Transient performances of HPF under step increase in DC-link voltage during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) and (f) DC-link capacitor voltages vv dddd and vv dddd2, respectively. (g) DC balance current II. (h) DC loss current II 2. (i) Instantaneous active power PP LL on load side. (j) Instantaneous active power PP SS on source side. (k) Instantaneous reactive power QQ LL on load side. (l) Instantaneous reactive power QQ SS on source side. (m) Power factor on load side. (n) Power factor on source side Experimental waveforms from top-to-bottom in each figure shows source voltage vv aa, source current ii ssss, load current ii LLLL and compensating currents ii ffff (X axis = xxi

23 . s/div). (a) Response of HPF under steady-state with 2 kw load by employing conventional controller. (b) Response of HPF under steady-state with 2 kw load by employing proposed controller Harmonic spectrum of currents. (a) Load current (ii LLLL ). (b) and (c) Source current (ii ssss ) with conventional and proposed controller, respectively Experimental waveforms of amplitude estimation of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column) by using conventional ADALINE-RLS and proposed ADALINE-DFFRLS algorithms Experimental waveforms of phase estimation of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column) by using conventional ADALINE-RLS and proposed ADALINE-DFFRLS algorithms Experimental results from top-to-bottom in each figure shows source voltage vv aa, source current ii ssss, load current ii LLLL and compensating currents ii ffff (X axis =. s/div). (a) Load increases from kw to 2 kw by employing conventional controller (b) Load increases from kw to 2 kw by employing proposed controller (c) Load decreases from 2 kw to kw by employing conventional controller (d) Load decreases from 2 kw to kw by employing proposed controller 59 xxii

24 List of Tables 2. Computational resources needed for ADALINE-LMS and ADALINE-FXLMS algorithms Overall characteristics of ADALINE-LMS and ADALINE-FXLMS algorithms Percentage error in ADALINE-LMS and ADALINE-FXLMS algorithm at 3 db SNR List of parameters used in simulation tests Summary of the simulation results List of parameters used in simulation tests Harmonics content in load and source currents Summary of the simulation results List of parameters used in experimental tests Device utilization summary 2 5. List of parameters used in simulation tests Summary of the simulation results List of parameters used in experimental tests Comparative performance analysis of three APF topologies 6 xxiii

25 Abbreviations ABSA Adaptive Bacterial Swarming Algorithm AC Alternate Current ADALINE Adaptive Linear Neural Network ADC Analog to Digital Converter ANN Artificial Neural Network APF Active Power Filter BFO Bacterial Foraging Optimization CS Clonal Selection CSI Current Source Inverter CWT Continuous Wavelet Transform DAC Digital to Analog Converter DC Direct Current DFFRLS Dynamic Forgetting Factor Recursive Least Square DFT Discrete Fourier Transform DSO Digital Storage Oscilloscope DSP Digital Signal Processor DWPT Discrete Wavelet Packet Transform DWT Discrete Wavelet Transform ECKF Extended Complex Kalman Filter EnKF Ensemble Kalman Filter ESPRIT Estimation of Signal Parameters via Rotational Invariance Technique FXLMS Filtered-x Least Mean Square GA Genetic Algorithm HCC Hysteresis Current Control HPF Hybrid Power Filter IEEE Institute of Electrical and Electronics Engineers xxiv

26 IGBT Insulated Gate Bipolar Transistor IRP Instantaneous Reactive Power KF Kalman Filter LMS Least Mean Square LPF Low Pass Filter LS Least Squares MSE Mean Square Error PC Personal Computer PCC Point of Common Coupling PHC Perfect Harmonic Cancellation PI Proportional Integral PLL Phase Locked Loop PPF Passive Power Filter PSOPC Particle Swarm Optimizer with Passive Congregation PWM Pulse Width Modulation RDFT Recursive Discrete Fourier Transform RLS Recursive Least Square RWT Recursive Wavelet Transform SNR Signal to Noise Ratio SRF Synchronous Reference Frame SWFA Sliding Window Fourier Analysis THD Total Harmonic Distortion UPF Unity Power Factor UPQC Unified Power Quality Conditioner VHDL Very High Speed Integrated Circuit Hardware Description Language VLLMS Variable Leaky Least Mean Square VSI Voltage Source Inverter VSLMS Variable Step-size Least Mean Square WT Wavelet Transform xxv

27 List of Publications. P. Garanayak and G. Panda, Fast and accurate measurement of harmonic parameters employing hybrid adaptive linear neural network and filtered-x least mean square algorithm, IET Generation, Transmission & Distribution, vol., no. 2, pp , Feb. 26. (SCI Journal, 25 Impact Factor.576) 2. P. Garanayak, G. Panda, and P. K. Ray, Harmonic estimation using RLS algorithm and elimination with improved current control technique based SAPF in a distribution network, International Journal of Electrical Power & Energy Systems, vol. 73, pp , Dec. 25. (SCIE Journal, 25 Impact Factor 2.587) 3. P. Garanayak and G. Panda, Harmonic elimination and reactive power compensation by novel control algorithm based active power filter, Journal of Power Electronics, vol. 5, no. 6, pp , Nov. 25. (SCIE Journal, 25 Impact Factor.93) 4. P. Garanayak, G. Panda, and S. Mishra, A high-speed Master Slave ADALINE for accurate power system harmonics and inter-harmonics parameter estimation, IEEE Transactions on Neural Networks and Learning Systems, Revised version submitted. (SCI Journal, 25 Impact Factor 4.854) 5. P. Garanayak and G. Panda, An ADALINE with Nonlinear Weight Updating Rule Employed for Harmonic Identification and Power Quality Monitoring, Transactions of the Institute of Measurement and Control, Revision need to be submitted. (SCIE Journal, 25 Impact Factor.82) 6. P. Garanayak and G. Panda, FPGA Based Shunt Hybrid Active Power Filter for Harmonic Mitigation, 5 th International Exhibition & Conference, New Technologies in Transmission, Distribution, Smart Grid & Communication (GRIDTECH-25), pp , New Delhi, Apr P. Garanayak, G. Panda and P. K. Ray, Power System Harmonic Parameters Estimation using ADALINE-VLLMS Algorithm, IEEE International Conference on Energy, Power and Environment: Towards Sustainable Growth (ICEPE 25), pp. 6, NIT Meghalaya, Shillong, Jun. 25. xxvi

28 Chapter Introduction. Background and problem statement The widespread use of power converters and other nonlinear loads in a distribution network produces current harmonics along with reactive, negative and zero sequence current components. These harmful components cause various problems such as equipment overheating, capacitor fuse blowing, malfunctioning of control devices, excessive neutral current, operation failure of electronic equipment and poor accuracy in power meters. This has necessitated research attention in finding a fast and accurate harmonic estimation together with the dynamic filtering approach to achieve the power quality standard of a system. The generalized structure of a distribution system along with power quality assessment and its enhancement approach is shown in Fig... The system structure is constituted by various functional blocks to assess and improve the power quality of a distribution network. Due to the intensive use of nonlinear loads in a system, harmonic related problems arise. The distorted current signal is collected and analyzed via estimation block to determine the harmonics present in the system. On the other hand, the harmonic and reactive components present in the distorted signal are compensated by means of power filtering circuit with a suitable control strategy to enhance the power quality of the system.

29 Chapter : Introduction ii ss PCC ii LL Balanced/ Unbalanced Nonlinear Loads Power Supply ii ff Actual Feedback Signals Power Filtering Circuit DC-Link Voltage/Current Source Currents Source/PCC Voltages Load Currents Gating Signals Amplifier Circuit Voltage/Current Sensor Current Sensors Voltage Transducers Current Sensors DAC ADC PC PWM Switching Strategy Reference Signals Control Technique for Harmonic and Reactive Currents Detection DSP Processor Algorithm for Individual Harmonic Parameter Estimation Power Quality Monitoring Fig..: Generalized structure of a distribution power system network. Power Quality Assessment The filtering of harmonics from a distorted power signal follows few basic steps. In the first step, the required voltage and current signals are sensed using voltage transducers and current sensors respectively. In the second step, the measured signals are converted into digital data with a fixed sampling interval by analog to digital converter (ADC) and these digital data are used as input for microcontroller or digital signal processor (DSP). The reference signals in terms of currents/voltages are evaluated based on the harmonic detection technique. The last step of control is to produce switching pulses for the operation of filtering circuit using pulse width modulation (PWM) technique. The outputs of the PWM controller, i.e. digital data are converted into continuous values via digital to analog converter (DAC). These low amplitude pulses are further strengthened by an amplifier circuit and then applied to the gate terminals of semiconductor devices in the active power filter (APF). Based on the switching signals, the power filter injects compensating current, which is the equal magnitude and opposite in phase of the harmonic components present in the load current. Thus the power quality of the distribution network connected to nonlinear loads is improved. To evaluate the compensation effect of filtering approach, the sensed 2

30 Chapter : Introduction current signals before and after filtering are estimated effectively by applying an accurate and fast estimation algorithm..2 Review of power quality assessment Due to the intensive use of nonlinear loads in a distribution network, the distorted power signals (i.e. current/voltage signals) obtained at the point of common coupling (PCC) usually contain harmonics and these harmonics are characterized by various parameters such as amplitude, phase, and frequency. These parameters must be estimated accurately by employing suitable techniques to assess the power quality of a system. This section describes a comprehensive survey of different techniques used for estimation of harmonics present in a distorted power signal. The techniques used to estimate these parameters can be broadly classified into three categories, namely nonparametric, parametric and hybrid [-3] as shown in Fig..2. Non-parametric estimation techniques are based on the transformation of the given time-series data sequence. These techniques do not make any assumption of the model from which data samples are being generated. They are also known as the classical techniques. Discrete Fourier Transform (DFT) is widely used for power harmonic estimation due to its simplicity and easy implementation. However, the DFT based estimation has inherent limitations such as spectral leakage, aliasing and picket fence effect [4-6]. An estimation technique based on wavelet transform (WT) was reported towards the end of the last decade of the twentieth century. Pham and Wong [7] applied discrete wavelet transform (DWT) or discrete wavelet packet transform (DWPT) for decomposing a signal into uniform sub-bands and then harmonic content were obtained using continuous wavelet transform (CWT). These techniques are not capable of incorporating any available information about the system in the estimation. The parametric methods need sufficient prior information about the system and the system is modeled to evaluate the harmonic parameters. These methods are commonly used to obtain high-resolution estimates, especially in applications where short data records are available during transient phenomena as well as the signal structure must be known. A widely used parameter estimation method is the least squares (LS) technique that minimizes the sum of the squares of the errors between actual and estimated values of a signal [4, 8]. The performance of this algorithm 3

31 Chapter : Introduction Harmonic Estimation Methods Non-parametric Methods Parametric Methods Hybrid Methods Discrete Fourier Transform (DFT) Wavelet Transform (WT) Linear Methods Nonlinear Methods Least Squares (LS) M-Estimator Recursive Least Square (RLS) Kalman Filter (KF) Artificial Neural Network (ANN) Adaptive Linear Neural Network (ADALINE) Fig..2: Classification of harmonic estimation methods. depends on the width of the observation window, the sampling frequency, the reference time and the Taylor series truncation. Pradhan et al. [9] and Subudhi et al. [] suggested least mean square (LMS) algorithm for power system frequency estimation. However, this method is not so effective for estimation of harmonics. On the other hand, the recursive least squares (RLS) technique is a well-established numerical method that can estimate harmonic parameters of a distorted signal even with the presence of decaying DC offsets and noise [-3]. However, the computational complexity of the RLS algorithm is higher than LMS and thus, it is not suitable for real-time harmonic estimation under the highly distorted power system environment. Another commonly used estimation technique is the Kalman filter (KF), which works on the principle of recursive stochastic technique and provides a least square optimal estimate under noisy environment [6, 4]. This algorithm possesses bulk calculations that limit on-line harmonics estimation. This algorithm also fails to track abrupt or dynamic changes of the signal. Dash et al. [5] proposed an extended complex Kalman filter (ECKF) based improved algorithm for on-line harmonics analysis. Ray and Subudhi [6] suggested ensemble Kalman filter (EnKF) algorithm, which can be applied to a distorted signal with a large number of variables. In the last couple of decades, many power system harmonic estimation techniques based on the learning principles have become quite popular. These techniques are applied to overcome the shortcomings such as inaccuracy on account of 4

32 Chapter : Introduction incorrect modeling, noise present in the signal and nonlinearity. Osowski [7] and Lin [8] proposed an artificial neural network (ANN) to estimate the harmonic components accurately by taking ½ cycle sampled values of a distorted waveform in noisy environments. Later, Dash et al. [9] proposed a new approach using adaptive linear neural network (ADALINE) for on-line harmonic estimation. In recent years, ADALINE structure is widely used as harmonic estimator due to its simple structure and non-stationary signal parameter tracking capability. Recently, Chang et al. [2] proposed two-stage ADALINE that is robust and capable of detecting harmonics and inter-harmonics. Sarkar et al. [2] proposed a modified ADALINE structure, namely self-synchronized adaptive linear neural network (S-ADALINE) that provides faster response and better noise immunity than the conventional ADALINE structure. Some well documented harmonic estimation approaches using modified ADALINE structures along with different weight updating rules provide accuracy and reduce response time [22-26]. Tao et al. [27] proposed a nonlinear technique based on M-Estimators for harmonic estimation to overcome the error in estimation under highly impulsive noise. The initial values of harmonic frequencies are calculated using estimation of signal parameters via rotational invariance technique (ESPRIT) algorithm, which avoids the cost function of M-Estimator to be stuck in local minima and improves the convergence rate of optimization. With the idea of utilizing the strengths of the individual harmonics estimation method and restraining the shortcomings, several hybrid techniques have been reported in the literature [28-36]. These techniques utilize combination of linear parameters (i.e. amplitudes) and nonlinear parameters (i.e. phases) estimation. In [28-32], the linear parameters are estimated using LS technique. Whereas the nonlinear parameters were estimated by applying various optimization techniques. Bettayeb and Qidwai [28] proposed a genetic algorithm (GA) to evaluate nonlinear parameters of a signal under consideration. However, GA suffers from the drawback of premature convergence that degrades its performance and search capability. To overcome these limitations, Mishra [29] suggested Fuzzy based bacterial foraging optimization (BFO) technique for phase estimation of fundamental and harmonic components. Moreover, Ji et al. [3] and Lu et al. [3] proposed adaptive bacterial swarming algorithm (ABSA) and particle swarm optimizer with the passive congregation (PSOPC) for phase estimation, respectively. Moravej and Enayati [32] utilized clonal selection (CS) based algorithm for nonlinear parameter estimation. Joorabian et al. [33] and Sahoo et al. [34] applied LS and robust 5

33 Chapter : Introduction H estimator for the evaluation of amplitudes, respectively. However, ADALINE structure was utilized for phase estimation of harmonics of a distorted power signal. Ren and Kezunovic [35] suggested the recursive wavelet transforms (RWT) based estimation technique that provides fast response and accuracy. However, it has some limitations of requiring high sampling rate and data for one complete cycle. Subudhi and Ray [36] proposed combined RLS-ADALINE and KF-ADALINE approaches for power system harmonic estimation. Both RLS and KF algorithms are utilized for weights updating in the ADALINE. It was reported that KF-ADALINE based estimation performance is better than RLS-ADALINE. Some advanced signal processing techniques such as variable step-size least mean square (VSLMS) [37, 38], filtered-x least mean square (FXLMS) [39-42], variable leaky least mean square (VLLMS) [43-46], and dynamic forgetting factor recursive least squares (DFFRLS) [47-5] are suggested in this research work for weight adaptation of the ADALINE. These are improved version of conventional LMS and RLS based estimation algorithms..3 Review of power quality enhancement Dynamic filtering approach plays an important role in power quality improvement of the distribution system connected with nonlinear loads. The research on power quality improvement deals mainly with the development of power filter topology along with suitable control strategy. This section presents a comprehensive review of various filter configurations and control strategies..3. Power filter configurations The power filters used for harmonic compensation are broadly classified into three categories [5], namely passive power filter (PPF), APF and hybrid power filter (HPF) as illustrated in Fig..3. PPFs are commonly used to eliminate the harmonic-related problems in the distribution system due to its low cost and simplicity in structure. These filters are configured with various combinations of capacitors and inductors. The filtering of a particular harmonic component from the distorted signal depends on the filter topology and values of filter elements. Nassif et al. [52] and Yousif et al. [53] suggested various 6

34 Chapter : Introduction Harmonic Filters Passive Power Filter (PPF) Active Power Filter (APF) Hybrid Power Filter (HPF) Single Tuned Filter High Pass Filter Shunt APF Series APF Active-Active Passive-Passive Active-Passive Series APF and Shunt PPF Shunt APF and Shunt PPF APF in Series with Shunt PPF Fig..3: Classification of power filters topology. configurations of shunt PPF. The shunt connected PPFs in the system provide a low impedance path for the flow of harmonic currents and also, monitor the reactive power at the fundamental frequency. The most commonly used filters are the single tuned filter and high pass filter. The single tuned filter is aimed at filtering a particular harmonic, while the high pass filter is intended to eliminate harmonics above certain frequencies. However, the PPFs have many drawbacks such as fixed compensation, large size, and series/parallel resonance. The increased severity of harmonic pollution in the distribution network has attracted to employ dynamic filtering solution with APFs. In recent years, many circuit topologies of APFs are well documented and considered as an effective and viable solution for improving the power quality of the system. This active filtering approach works on the principle of injecting harmonic currents into the AC system, of the same amplitude and opposite phase to that of the load current harmonics. The APFs are generally classified into shunt- and series-apf depending on the connections with the supply systems [54, 55]. Akagi [56], Singh et al. [57] and Routimo et al. [58] suggested the classification of APFs into current source inverter (CSI) and voltage source inverter (VSI) based topologies. CSI based APFs are fed from the energy stored in the inductor [59, 6], whereas VSI based APFs are fed from the energy stored in the capacitor [6-75]. VSI based APFs are commonly used due to higher in efficiency, lower in cost and smaller in physical size than the CSI based APFs [56]. 7

35 Chapter : Introduction A shunt APF is connected in parallel with the AC mains at the PCC [59-75]. It injects equal compensating currents with opposite phase to revoke harmonics and/or reactive components of the distorted load currents. Fujita and Akagi [76], Chang and Chen [77] and Wang et al. [78] proposed series APF to eliminate voltage harmonics and balance the voltages. The APF is connected in series between the mains and nonlinear load via a matching transformer. It has also been used to reduce the negativesequence voltage and regulate the voltage on three-phase systems. However, the series filter is less popular in the industrial applications due to the inherent drawbacks of series circuits, namely it must handle high load currents that increase their current rating compared with the shunt APF. Although APFs provide satisfactory dynamic compensation, their initial and operational costs are relatively high. Furthermore, the use of high DC-link voltage has many disadvantages such as large filter inductance, and high voltage rating of DC-link capacitor and semiconductor switching devices. A large filter inductor will result in significant power loss, more heat dissipation, bulk dimension and weight, degrades the performance of frequency response. The requirement of high voltage rating of DC-link capacitor and semiconductor devices limits high power application of APFs [79]. Over the last few years, HPF topologies have been developed to solve the harmonic related problems effectively. The use of low cost passive filters along with high performance APFs provide cost effective solution for harmonic compensation and voltage regulation. The HPFs are classified into three categories, namely passivepassive, active-active and active-passive [8]. Fujita and Akagi [8], Karanki et al. [82] and Basu et al. [83] proposed a unified power quality conditioner (UPQC), which is a combination of series APF and shunt APF. The DC-link storage element (either inductor or capacitor) is shared between two CSI or VSI based APFs. This type of combination mitigates voltage and current related power quality issues. Due to the involvement of a large number of semiconductor devices, the computational cost and circuit complexity of the UPQC are high. Khadkikar [84] suggested different possible UPQC system topologies for power quality enhancement. The active-passive combination utilizes the advantages of both filters and at the same time eliminates the drawbacks of individual filter type. Lam and Wong [85] and Jain et al. [86] classified the active-passive topologies into three general categories, 8

36 Chapter : Introduction namely series APF and shunt PPF, shunt APF and shunt PPF and APF in series with shunt PPF. The series APF and shunt PPF topology is particularly suited for the system to the voltage source type of load, i.e. RC load [87-9]. Under this topology, the series APF acts as a harmonic isolator between the source and load by constraining all the load harmonics to flow into the shunt PPF. At the fundamental frequency, the shunt PPF shows high impedance while the series APF shows low impedance. On the contrary, the shunt PPF shows low impedance while the series APF shows high impedance at harmonic frequencies. This type of combination significantly reduces the rating of the APF, around 5% to % of the rating of nonlinear load. However, the series APF requires adequate protection as it is connected in series with the distribution power system through coupling transformer [85, 86]. The shunt APF and shunt PPF topology is preferred when the load is of current source type i.e. RL load. Under this topology, the PPF acts as the main compensator and the APF is used to compensate the remaining current harmonics, which have been filtered by the PPF [92, 93]. Thus this topology aims to reduce the current rating of the APF as compared to the previous hybrid topology. Moreover, it can prevent the parallel resonance phenomena. However, the major drawback with this configuration is that their ratings are decided by the peak harmonic current and therefore, they are not suited to the high peak harmonic current loads [85, 86]. The APF in series with shunt PPF topology via coupling transformer was presented by Fujita and Akagi [94] and Basic et al. [95]. Whereas Srianthumrong and Akagi [96], Lin et al. [97], Corasaniti et al. [98] and Rahmani et al. [99] proposed the same topology without using a coupling transformer. Under this hybrid topology, the APF and PPF are connected in series with or without coupling transformer and this combination is then shunted to the distribution power system. The PPF can be a tuned LC filter or high pass filter or any combination of them. In this topology, the APF aims to change the impedance of the PPF so that the PPF has a nearly zero impedance to the load side current harmonics and infinite impedance to the source side voltage harmonics, so as to improve the compensation characteristics of the PPF [85]. When a PPF and an APF are connected in series, the fundamental system voltage mainly drops on the capacitor of PPF, but not the APF. Thus this topology aims to reduce the voltage rating of APF. Moreover, it can prevent the series and parallel resonance phenomena []. 9

37 Chapter : Introduction.3.2 Development of control strategies applied to APFs The dynamic and effective harmonic compensation employing APF is strongly dependent on the control strategy, which is implemented in three stages. In the first stage, the essential voltage and current signals are sensed using voltage transducers and current sensors respectively. In the second stage, the reference signals in terms of either voltages or currents are evaluated based on compensating methods and APF configurations. In the third stage of control, the gating signals for semiconductor devices of the APF are generated using PWM current control technique. Development of reference signals in terms of either voltages or currents employing suitable compensating control strategy is the most important part in the efficient functioning of the active power filter. The compensating control strategies are based on frequency and time domain correction techniques [-4]. Several frequency domain control approaches, namely Fourier analysis [5], DFT [4, 6], recursive discrete Fourier transform (RDFT) [7, 8], KF [8] and WT [9], were implemented to control the APF performance. The frequency domain corrections depend on the periodic characteristics of the distortion [3]. These methods have some advantages over the time domain approaches; they are appropriate for the unbalanced system and do not need both voltage and current measurements [6]. The major drawbacks of these methods are large memory requirements, large response time, large computation burden and imprecise results in transient conditions [4]. Compensating control methods of the APFs in the time domain are based on the instantaneous derivation of reference signals in the form of either voltage or current signals from distorted waveforms. The time domain methods offer fast response, easy to implement and less computational burden as compared to the frequency domain. It ignores periodic characteristics of the distorted waveform and does not learn from past experiences. The most popular methods in the time domain are instantaneous reactive power (IRP) and synchronous reference frame (SRF) theories. The IRP theory works on the computation of active and reactive powers using three-phase to two-phase transformation [88, 9, -4]. The working principle of SRF theory is based on Park s transformation, where three-phase voltage and current signals are transformed to a synchronously rotating frame. In this approach, the fundamental quantities become DC quantities, which can be separated easily through filtering. Subtracting transformed

38 Chapter : Introduction load currents from these DC components, reference signals in the synchronous rotating frame are evaluated [6, 67-75, 92, 95-, 5]. Patidar and Singh [6] and Machmoum and Bruyant [6] suggested power balance control method for calculating the amplitude of the reference current. This amplitude is multiplied with the sinusoidal fundamental template of unity magnitude that is generated from phase locked loop (PLL), leading to an estimated instantaneous fundamental active component of the load current. Jou [7] proposed energy balance method, which is based on the estimation of the active power required by the load and DC-link capacitor of the APF. With the help of such estimated components, instantaneous reference supply currents are obtained using instantaneously sensed supply voltage. Subtracting load currents from these supply reference currents, reference signals for APF are obtained. Basic et al. [8], Karimi et al. [9] and Ketabi [2] recommended notch filter based harmonic and reactive current extraction. In this method, the distorted load current is passed through a notch filter of fundamental supply frequency that removes the fundamental component. The resultant signal thus extracted is used as a reference signal for the APF. Montero et al. [] and Rafiei et al. [2] presented unity power factor (UPF) and perfect harmonic cancellation (PHC) strategies for load compensation under distorted voltage. The UPF compensation strategy conditions the current flowing in the plant where compensation is realized to feed the voltage waveform, thus reaching a unity power factor. Montero et al. [] and Rafiei et al. [2] presented unity power factor (UPF) and perfect harmonic cancellation (PHC) strategies for load compensation under distorted voltage. The UPF compensation strategy conditions the current flowing in the plant where compensation is realized to feed the voltage waveform, thus reaching a unity power factor. Hsu and Wu [22] employed sine multiplication technique for reference signal extraction. This method is based on the process of multiplying the load current signal by a sine wave of fundamental frequency and integrating the result to calculate the fundamental active component of the load current. The difference between the instantaneous load current and this fundamental component is the reference signal for the APF []. Bhattacharya et al. [23] proposed synchronous frame flux-based control strategy for shunt APF. This method utilizes the linear relation between the flux and

39 Chapter : Introduction current in a linear inductor and facilitates direct implementation of a current regulator without explicit generation of voltage reference. Using synchronous dq transformation technique, the harmonic current components are separated from the measured load currents. From this current value, reference flux is derived. The deviation between the actual inductor flux and the reference inductor flux in the synchronously rotating frame dictates the inverter switching operation, and thereby resulting current regulation. The application of ANN for extraction of reference signals were proposed in [24-27]. The ANNs present two principal characteristics. It is not necessary to establish specific input-output relationships, but they are formulated through a learning process or through an adaptive algorithm. This parallel computing architecture increases the system speed and reliability. However, the ANN technique needs an a priori offline long training phase and works properly for the certain topology of known loads [28]. A slightly different structure called ADALINE has been used to estimate the reactive power and harmonic content in the load current [29-38]. This method is based on adaptive interference cancelling theory. Taking undistorted voltage signal as the reference and distorted current signal as the primary input, it can effectively extract the sum of total harmonic and reactive components present in the current signal. Operating in a closed loop, it maintains suitable operating state by continuously self studying and self adjusting from start to end. This makes it highly robust with respect to power frequency variations, thereby can eliminate few limitations associated with the conventional detection techniques. In addition, this method is useful in places where there are possibilities of suffering measurement accuracy due to the noise or parameter variations []. The performance of an APF is affected significantly by the selection of PWM current control techniques [3]. To compensate for the distorted current drawn by the nonlinear loads from the utility grid, the APF and its PWM current control must have the capability to track sudden slope variations in the generated reference signals. Therefore, in the APF application, the choice and implementation of the current regulator is more important for the achievement of a satisfactory performance level. A variety of approaches such as PWM current or voltage control, predictive control and hysteresis based current control are implemented either through hardware or software to obtain the control signals for the switching devices of the APF [6, 39, 4]. 2

40 Chapter : Introduction Kim and Sul [4] and Zhou and Wang [42] proposed the carrier-based PWM control technique, which is also called linear current control. The principle of conventional carrier-based PWM control is that the modulation signal achieved by a current regulator from the current error signal (i.e. the difference between the generation of reference and compensating currents) is compared with the fixed frequency triangular carrier wave to generate the switching pulses for semiconductor devices of the APF. With this type of control, the inverter is switched at the frequency of the triangle wave and its output current contains a maximum number of harmonics. [67-69, 96, 3]. The main advantage of carrier-based PWM control technique is that the inverter switches operate at a fixed frequency. However, the system response is affected by the stability requirements of the feedback loop, which also depends on the system parameters [43]. Rodriguez et al. [44] proposed predictive current control method for generation of switching signals. This technique provides optimum performance in terms of both response time and accuracy, but it involves non-negligible calculations and requires a good knowledge of system parameters [43]. The hysteresis current control (HCC) is based on the nonlinear control theory. The basic principle of HCC technique is that the switching signals are derived from the comparison of the current error signal with a fixed width hysteresis band [62, 64-66, 74]. Hysteresis control, on the other hand, provides fast response and good accuracy. It can be implemented with minimum numbers of hardware and, in principle, does not require knowledge of system parameters. However, the current control with a fixed hysteresis band has the disadvantage that the PWM frequency varies within a band because peak to peak current ripple is required to be controlled at all points of the fundamental frequency wave. In order to overcome these deficiencies, a variable width HBC was proposed in [43, 45, 46]..4 Research objectives The intensive use of nonlinear loads, especially power electronics equipment in a distribution network causes power quality distortion. Thus power quality assessment and its enhancement have become research challenges in recent years. For this reason, a cost-effective active filtering system along with fast and accurate harmonic estimation 3

41 Chapter : Introduction can be the most suitable approach in a distribution network connected to nonlinear loads. Therefore, the main objectives of present research can be outlined as follows: Develop a suitable adaptive algorithm for the power system harmonic parameter estimation and compare its performance with the conventional algorithm. Mathematical modeling and performance analysis of shunt APF using nonlinear control technique. Design and analysis of a low-rated shunt HPF for low- or medium-voltage applications. Design and analysis of a low-rated and low-voltage stress midpoint DC-link capacitor shunt HPF for medium- and high-voltage applications. The compensating performance of the active filters employing various control strategies is examined under critical conditions via MATLAB/Simulink environment. Establish a scaled laboratory prototype to validate the performance of HPFs employing proposed control strategy in the real-time application through DSP processor..5 Outline of the thesis The thesis is organized into six chapters as follows: Chapter : Introduction In this chapter, a brief introduction to power quality assessment and its enhancement in a distribution power system network connected with nonlinear loads are presented. This chapter specifically presents the review of prevailing techniques used for harmonic estimation as well as elimination. Furthermore, this chapter emphasizes the objectives of the present research. Finally, an outline of each chapter in the thesis is presented. Chapter 2: Power system harmonics estimation employing hybrid ADALINE-FXLMS algorithm This chapter proposes a fast and accurate estimation of the fundamental, harmonics, inter-harmonics, sub-harmonics and DC decaying function present in a distorted power 4

42 Chapter : Introduction signal using novel hybrid ADALINE-FXLMS algorithm. The mean square error (MSE), stability and computational burden of the proposed algorithm are mathematically evaluated. The results obtained from the simulation and experimental validation are presented and discussed subsequently. Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy In this chapter, the focus is on the design, modeling and analysis of three-phase shunt APF for power quality enhancement in a distribution system. The current controller used for APF is based on voltage decoupling along with pole-zero cancellation method to provide fast current harmonic compensation. Furthermore, a novel PWM control scheme is applied to produce the switching signals for insulated gate bipolar transistors (IGBTs) of the inverter. The performance of shunt APF under various operating scenarios is examined via MATLAB/Simulink to validate the effectiveness of the controller. Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF system This chapter elucidates the low-rated shunt HPF topology, which is configured as APF in series with shunt PPF. A novel ADALINE-VLLMS technique is incorporated to estimate the harmonics and reactive power component present in a distorted current signal. Simulation and experimental results are presented to validate the effectiveness of the proposed control algorithm in improving the power quality of a distribution system. Chapter 5: Harmonic elimination using SWFA based HPF system and evaluation of compensation effect employing ADALINE-DFFRLS algorithm This chapter presents a low-rated midpoint DC-link capacitor shunt HPF embedded with sliding window Fourier analysis (SWFA) based harmonic detection method for power quality enhancement in a medium-voltage distribution network. In addition, a novel ADALINE-DFFRLS estimation algorithm is employed to evaluate the compensation effect accurately. Simulation and experimental results are provided to show the efficacy of the proposed controller for power quality appraisal. Moreover, the 5

43 Chapter : Introduction comparative performance, inverter voltage ratings and the applications of three different APF topologies are described in the last section of this chapter. Chapter 6: Conclusions and future work The main conclusions and contributions of the research documented in this thesis are highlighted with suggestions for future work. 6

44 Chapter 2 Power System Harmonics Estimation Employing Hybrid ADALINE-FXLMS Algorithm 2. Introduction The increasing use of nonlinear loads in distribution power system network causes distortion in power signals (i.e. voltage/current signals). These signals contain harmonics, inter- and sub-harmonics; which create several problems related to power system operation, protection and control. This has necessitated research attention to develop a fast and accurate harmonic estimation technique for power quality assessment. Many research works are well documented in the application of an ADALINE for parameter estimation due to its low computational complexity, minimum tracking error and faster convergence rate. In general, the weight vector of ADALINE is updated by applying LMS algorithm. The standard LMS based weight updating rule does not show adequate convergence behaviour in many situations such as signals containing impulsive noise, time-varying signals, and real-time implementation. This is mainly due to the presence of an additional filter h(zz) in the cancellation path, i.e. between the adaptive filter and summing junction as shown in 7

45 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Fig. 2.. On the other hand, the secondary path immediately follows the adaptive filter [39]. Thus, the overall performance of the control system gets significantly degraded. To overcome such limitations, either an inverse filter is introduced in the cancellation path or a similar additional filter h(zz) in the reference path. The former method is termed as filtered error, while the latter is known as filtered reference. The filtered error approach requires a simple delay in the reference path to compensate the nonminimum-phase part, for which the circuit complexity increases. On the other hand, the filtered reference estimation approach avoids the use of such delay because it needs only one filter in the secondary path. Therefore, the filtered reference process is simple and cost effective solution for harmonic estimation [4, 4]. This chapter addresses an estimation algorithm based on ADALINE-FXLMS for fast and accurate measurement of fundamental, harmonics, sub- and inter-harmonics parameters of a distorted power system current signal. The step size parameter of the proposed algorithm can be updated to an upper bound limit (i.e. stability boundary) that results in further improvement of system stability [25, 42]. The simulated results obtained by employing proposed algorithm are compared with the results based on ADALINE-LMS algorithm to demonstrate better tracking capability. Finally, a scaled laboratory prototype is developed and the proposed hybrid algorithm is implemented to justify the efficacy of the analytical results. For real-time analysis, a distorted source current collected from the input of a single-phase thyristorised bridge rectifier feeding DC-motor is considered as a test signal. Even though the computational complexity of ADALINE-FXLMS algorithm is relatively higher than the ADALINE-LMS, it exhibits better stability, faster convergence and more robustness for analysing the signal in the presence of noise. 2.2 State-space model of a time-varying signal The non-sinusoidal power signal is constituted by the combination of harmonic components as well as a fundamental component. It is assumed that the frequency is known and constant during the estimation process. Considering a time-varying distorted current signal containing QQ number of harmonics, the Fourier series can be expressed as 8

46 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm ii(tt) = QQ qq= AA qq ssssss ωω qq tt + ΦΦ qq QQ = qq= (AA qq cccccc ΦΦ qq ssssss ωω qq tt + AA qq ssssss ΦΦ qq cccccc ωω qq tt) QQ = qq= (aa qq xx aaaa (tt) + bb qq xx bbbb (tt)) QQ = [aa qq bb qq ] xx aaaa (tt) qq= xx bbbb (tt) (2.) where ωω qq, AA qq and ΦΦ qq denote the angular frequency, amplitude and phase angle of qq tth component respectively. The unknown values aa qq = AA qq cccccc ΦΦ qq, bb qq = AA qq ssssss ΦΦ qq qq= QQ and aa qq, bb qq qq=2 describe the Fourier coefficients of the fundamental and harmonic components respectively. Furthermore, reference sine and cosine inputs xx aaaa (tt) = QQ ssssss ωω qq tt, xx bbbb (tt) = cccccc ωω qq tt} qq= are known signals [2, 23, 25, 4]. The discrete-time representation of ii(tt) can be expressed as follows. QQ ii(nn) = [aa qq (nn) bb qq (nn)] xx aaaa (nn) qq= xx bbbb (nn) (2.2) The control signal yy(nn) can be derived by summing filter outputs as QQ yy(nn) = qq= (yy qq (nn) ) QQ = qq=( aa (nn)xx qq aaaa (nn) + bb (nn)xx qq bbbb (nn)) QQ = aa (nn) qq bb (nn) qq xx aaaa (nn) qq= xx bbbb (nn) (2.3) QQ where aa (nn), qq bb (nn) qq qq= denote the estimated coefficients that can be updated by adaptive algorithm. By utilizing these coefficients, the estimated amplitude AA qq and phase ΦΦ qq can be written as follows. AA qq = aa (nn) 2 qq + bb (nn) 2 qq and ΦΦ qq = tttttt bb (nn) qq aa (nn) (2.4) qq 2.3 Architecture of ADALINE-LMS algorithm The functional block diagram of an ADALINE based harmonic parameter estimation is demonstrated in Fig. 2.. It is composed of 2QQ number of neurons whose weights 9

47 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm ssssss(ωω qq nn) cccccc(ωω qq nn) xx aaaa (nn) xx bbbb (nn) aa (nn) qq bb (nn) qq Σ yy (nn) yy qq (nn) Σ yy(nn) h(zz) ii (nn) ii(nn) Σ ee(nn) yy QQ (nn) LMS Adaptation Algorithm Fig. 2.: Functional block diagram of ADALINE-LMS algorithm. QQ aa (nn), qq bb (nn) qq qq= are updated by LMS algorithm. The sinusoidal reference inputs xx aaaa (nn) = ssssss ωω qq nn, xx bbbb (nn) = cccccc ωω qq nn qq= QQ of the ADALINE are generated from the PLL circuit. Likewise ii(nn), yy(nn) and ee(nn) are denoted as distorted current (i.e. sensed signal), output of the adaptive filter (i.e. control signal) and calculated residual error (i.e. error signal), respectively. QQ The estimated coefficients aa (nn), qq bb (nn) qq qq= updated by using the following expressions. at any sampling instant nn are aa (nn qq + ) = aa (nn) qq + ΔΔ aaaa (nn)xx aaaa (nn)ee(nn) bb (nn qq + ) = bb (nn) qq + ΔΔ bbbb (nn)xx bbbb (nn)ee(nn) (2.5) where ΔΔ aaaa (nn) = ΔΔ bbbb (nn) = ΔΔ qq (nn) represents the time-varying step size parameter that can be adapted as ΔΔ qq (nn + ) = cc ΔΔ qq (nn) + cc 2 pp 2 (nn) (2.6) ΔΔ qq (nn + ) = ΔΔ qqqqqqqq ΔΔ qqqqqqqq ΔΔ qq (nn + ) iiii ΔΔ qq (nn + ) > ΔΔ qqqqqqqq iiii ΔΔ qq (nn + ) < ΔΔ qqqqqqqq ooooheeeeeeeeeeee (2.7) where ( < cc < ) and (cc 2 > ) are constant values that control the convergence rate. ΔΔ qqqqqqqq and ΔΔ qqqqqqqq represent the minimum and maximum values of the step size parameter, respectively. The autocorrelation error pp(nn) can be expressed as pp(nn) = cc 3 pp(nn ) + ( cc 3 )ee(nn) ee(nn ) (2.8) 2

48 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm where ( < cc 3 < ) is an exponential weighting factor that controls the time average estimate. Referring Fig. 2., the prediction error ee(nn) is the difference between the sensed signal ii(nn) and the control signal yy(nn). Accordingly, we can write ee(nn) = ii(nn) yy(nn) = ii(nn) ww TT (nn)xx(nn) (2.9) The variable step size parameter ΔΔ qq (nn) increases with the increase of prediction error ee(nn), which in turn provides faster convergence. However, with the decrease of ee(nn), ΔΔ qq (nn) reduces to achieve low misadjustment level. Referring [37, 38], the necessary and sufficient condition for stability of the algorithm is satisfied by choosing ΔΔ qq (nn) as follows. < ΔΔ qq (nn) < 2 λλ mmmmmm (2.) where λλ mmmmmm is the largest eigenvalue of the input autocorrelation matrix RR. The upperbound limit for ΔΔ qq (nn) is defined as ΔΔ qqqqqqqq 2 3tttt (RR) (2.) where tttt(rr) represents the trace of the RR. The value of ΔΔ qqqqqqqq is selected to afford a minimum level of tracking capability. In general, the stability of the LMS algorithm is less sensitive to the choice of ΔΔ qqqqqqqq, but it is highly sensitive to ΔΔ qqqqqqqq. 2.4 Architecture of ADALINE-FXLMS algorithm Fig. 2.2 illustrates the functional block diagram of ADALINE-FXLMS algorithm applied for harmonic parameter estimation. In this figure, the impulse response of the secondary and cancellation path transfer functions are denoted as h (nn) and h(nn) respectively. The sinusoidal inputs xx aaaa (nn), xx bbbb (nn) are filtered by h (nn) to produce filtered inputs xx aaaa (nn), xx bbbb (nn), which are treated as reference signals for ADALINE- FXLMS algorithm [25]. The phase difference between h(zz) and h (zz) is less than 9. The transfer function of secondary and cancellation paths can be represented by an FIR system with their respective lengths MM and LL as h (nn) = h(nn) = MM mm= LL ll= h mm δδ(nn mm) h ll δδ(nn ll) (2.2) 2

49 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm ssssss(ωω qq nn) cccccc(ωω qq nn) xx aaaa (nn) xx bbbb (nn) aa (nn) qq bb (nn) qq Σ yy (nn) yy qq (nn) Σ yy(nn) h(zz) ii (nn) ii(nn) Σ ee(nn) h (zz) h (zz) yy QQ (nn) xx bbbb (nn) xx aaaa (nn) LMS Adaptation Algorithm Fig. 2.2: Functional block diagram of ADALINE-FXLMS algorithm. where δδ(nn) denotes Kronecker delta function. h mm and h ll are amplitude of the impulse response at time index mm and ll, respectively (generally LL > MM). xx aaaa (nn), xx bbbb (nn) are MM filtered by the FIR coefficients h mm mm= of the secondary path estimate h (zz) to calculate xx aaaa (nn), xx bbbb (nn). xx aaaa (nn) = h (nn) xx aaaa (nn) = xx bbbb (nn) = h (nn) xx bbbb (nn) = MM mm= MM mm= h mm xx aaaa (nn mm) h mm xx bbbb (nn mm) (2.3) QQ Then, the estimated Fourier coefficients aa (nn), qq bb (nn) qq qq= can be computed as aa (nn qq + ) = aa (nn) qq + ΔΔ aaaa (nn)xx aaaa (nn)ee(nn) bb (nn qq + ) = bb (nn) qq + ΔΔ bbbb (nn)xx bbbb (nn)ee(nn) (2.4) Similarly, the variable step size parameter ΔΔ aaaa (nn) = ΔΔ bbbb (nn) = ΔΔ qq (nn) of the ADALINE-FXLMS algorithm can be calculated using (2.6)-(2.8) Prediction error calculation The expression for the prediction error ee(nn) is given by ee(nn) = ii(nn) h(nn) yy(nn) = ii(nn) LL ll= h ll yy(nn ll) = ii(nn) LL ll= h ll ww TT (nn ll)xx(nn ll) (2.5) From the preceding equation, the optimal prediction error ee oooooo (nn) can be evaluated by setting yy(nn) = yy oooooo (nn) as follows. ee oooooo (nn) = ee(nn) yyoooooo (nn) = ii(nn) ww oooooo TT LL ll= h ll 22 xx(nn ll) = ii(nn) ww oooooo TT ff(nn) (2.6)

50 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm where, LL ff(nn) ll= h ll xx(nn ll) (2.7) The convergence of ADALINE-FXLMS algorithm is described in terms of rotated reference vector and rotated weight misalignment vector, instead of representing in original reference and weight vectors [25, 39, 42]. The rotated input vector ss(nn) can be expressed as ss(nn) BB TT xx(nn) (2.8) where BB is eigenvector matrix. The inverse of B is equal to its transpose. Similarly, the rotated weight error vector cc(nn) is computed as cc(nn) BB TT (ww(nn) ww oooooo ) (2.9) It is important to note that when ww(nn) converges to ww oooooo, cc(nn) approaches to the origin. Taking this advantage, the rotated weight error vector analysis of the ADALINE-FXLMS algorithm is more suitable for faster estimation. Similarly, the residual error ee(nn) in terms of the rotated variable is obtained using (2.5) ee(nn) = ii(nn) LL ll= h ll [ww TT (nn ll) ww oooooo TT + ww oooooo TT ]xx(nn ll) = ii(nn) ww TT oooooo LL ll= h ll xx(nn ll) LL ll= h ll [ww TT (nn ll) ww TT oooooo ]BBBB TT xx(nn ll) (2.2) By combining (2.7)-(2.2), we have LL ee(nn) = ii(nn) ww TT oooooo ff(nn) ll= h ll cc TT (nn ll)ss(nn ll) (2.2) On simplification of (2.2) using (2.6), the prediction error is expressed as LL ee(nn) = ee oooooo (nn) ll= h ll cc TT (nn ll)ss(nn ll) (2.22) MSE function The cost function JJ(nn) can be obtained by calculating the expectation of the square of the prediction error ee(nn) and is given by JJ(nn) = EE{ee 2 (nn)} = EE{ee(nn)ee TT (nn)} = EE ee oooooo (nn) LL ll= h ll cc TT (nn ll)ss(nn ll) ee oooooo (nn) LL ll= h ll cc TT (nn ll)ss(nn ll) TT 23

51 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm = EE ee oooooo (nn) LL ll= h ll cc TT (nn ll)ss(nn ll) ee oooooo (nn) LL pp= h pp = EE ee 2 LL oooooo (nn) EE ll= h ll LL ll= LL pp= +EE h ll h pp cc TT (nn ll)ss(nn ll)ee oooooo (nn) cc TT (nn ll)ss(nn ll)ss TT (nn pp)cc(nn pp) ss TT (nn pp)cc(nn pp) LL EE pp= h pp ss TT (nn pp)cc(nn pp)ee oooooo (nn) (2.23) In the preceding equation, ee oooooo (nn) is un-correlated with ss(nn) and cc(nn). Thus, the second and fourth terms are neglected. Now, the cost function becomes JJ(nn) = JJ oooooo + JJ eeeeee (nn) (2.24) where JJ oooooo and JJ eeeeee (nn) are the optimal- and excess-mse respectively that can be expressed as JJ oooooo = EE ee oooooo 2 (nn) (2.25) LL LL JJ eeeeee (nn) = EE ll= pp= h ll h pp cc TT (nn ll)ss(nn ll)ss TT (nn pp)cc(nn pp) (2.26) The minimum value of cost function for the second-order moment is expressed as follows. JJ(nn) mmmmmm = JJ oooooo JJ(nn) JJ oooooo JJ oooooo + JJ eeeeee (nn) JJ oooooo JJ eeeeee (nn) (2.27) The time difference of the excess-mse function is negative, which can be written as δδjj eeeeee (nn) = JJ eeeeee (nn + ) JJ eeeeee (nn) (2.28) On simplification of (2.28) using (2.26), we have δδjj eeeeee (nn) = ΔΔ qq (nn) 2 σσ h 4 σσ xx 4 KK JJ oooooo + ΔΔ qq (nn)σσ 2 xx [2 ΔΔ qq (nn)σσ 2 h σσ 2 xx (KK + 2DD eeee )] LL pp= h 2 pp JJ eeeeee (nn pp) (2.29) where KK and DD eeee are the filter length and secondary path equivalent delay, respectively. We can define σσ h 2 and DD eeee as follows. σσ 2 h = LL 2 ll= h ll (2.3) DD eeee = LL llh σσ 2 ll= ll 2 (2.3) h Equation (2.3) can be further reduced to δδjj eeeeee (nn) = ZZ (nn)jj oooooo ZZ 2 (nn)zz 3 (nn) (2.32) 24

52 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm where {ZZ (nn), ZZ 2 (nn)} and ZZ 3 (nn) are the time-varying parameters and scalar function respectively that can be defined as ZZ (nn) = ΔΔ qq (nn) 2 σσ 4 h σσ 4 xx KK (2.33) ZZ 2 (nn) = ΔΔ qq (nn)σσ 2 xx [2 ΔΔ qq (nn)σσ 2 h σσ 2 xx (KK + 2DD eeee )] (2.34) ZZ 3 (nn) = LL pp= h 2 pp JJ eeeeee (nn pp) (2.35) For stable adaptation process, we can write llllll nn δδjj eeeeee (nn) = (2.36) On the simplification of (2.36) using (2.32), we have ZZ 2 (nn) llllll nn ZZ 3 (nn) = ZZ (nn)jj oooooo (2.37) Finally, substituting (2.35) into (2.37) yields llllll nn JJ eeeeee (nn) = ZZ (nn)jj oooooo σσ h 2 ZZ 2 (nn) (2.38) Stability analysis From (2.27), it is concluded that the system is stable when JJ eeeeee (nn) is a finite and positive. The range of JJ eeeeee (nn) can be defined as < llllll nn JJ eeeeee (nn) < ii (2.39) where ii is a finite positive real number. Substituting (2.38) into (2.39), we can write < Z (n)j opt < ii (2.4) σ 2 h Z 2 (n) In the preceding equation, ZZ (nn), JJ oooooo and σσ h 2 are positive scalar quantities. A sufficient condition for stability of ADALINE-FXLMS algorithm can be defined as ZZ 2 (nn) > ΔΔ qq (nn)σσ xx 2 2 ΔΔ qq (nn)σσ h 2 σσ xx 2 KK + 2DD eeee > (2.4) Accordingly, the range of stability can be decided as < ΔΔ qq (nn) < 2 σσ xx 2 σσ h 2 (KK+2DD eeee ) (2.42) The upper-bound limit ΔΔ qqqqqqqq (i.e. stability bound) can be defined as ΔΔ qqqqqqqq = 2 σσ xx 2 σσ h 2 (KK+2DD eeee ) (2.43) 25

53 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm In other words, the system stability is proportional to ΔΔ qqqqqqqq and it improves with the reduction in equivalent delay DD eeee. At the time of estimation, the step size parameter of the proposed algorithm can be increased up to an upper-bound limit ΔΔ qqqqqqqq, beyond which the system becomes unstable [25, 42]. The optimum value of step size is chosen as.5δδ qqqqqqqq for faster convergence and minimum error Computational complexity and memory load The computational resources (i.e. number of additions/subtractions and multiplications/divisions) required for performing a single iteration using ADALINE- LMS and ADALINE-FXLMS algorithms are summarized in Table 2.. The computational resource required is directly proportional to the speed of convergence. It is noticed that the ADALINE-LMS algorithm needs 2QQ + 7 multiplications and 2QQ + 3 additions per iteration. Whereas the proposed ADALINE-FXLMS algorithm demands 2QQ + MM + 7 multiplications and 2QQ + MM + 2 additions for computation of each iteration. Therefore, ADALINE-FXLMS performs faster than ADALINE-LMS. On the other hand, the computational cost of the proposed algorithm is higher than the standard algorithm due to the requirement of more number of addition and multiplication operations. Table 2.: Computational resources needed for ADALINE-LMS and ADALINE-FXLMS algorithms ADALINE-LMS estimation algorithm ADALINE-FXLMS estimation algorithm Equations considered for computation Multiplication /Division Addition /Subtraction Equations considered for computation Multiplication /Division Addition /Subtraction Coefficients aa (nn), qq bb (nn) qq update, (2.5) QQ + QQ Coefficients aa (nn), qq bb (nn) qq update, (2.4) QQ + QQ Compute the filter output yy(nn), (2.9) QQ QQ Compute the filter output yy(nn), (2.5) QQ QQ Calculation of error ee(nn), (2.9) Calculation of error ee(nn), (2.5) Step size ΔΔ qq (nn) adaptation, (2.6) 3 Step size ΔΔ qq (nn) adaptation, (2.6) 3 Error correlation pp(nn) adjustment, (2.8) 3 2 Error correlation pp(nn) adjustment, (2.8) 3 2 Secondary path estimate h (nn), (2.3) MM MM Total 2QQ + 7 2QQ + 3 Total 2QQ + MM + 7 2QQ + MM

54 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm The number of memory locations required to store the signal samples, coefficients and variable parameters is termed as memory load of the algorithm. The ADALINE-LMS algorithm necessarily needs 2QQ + 7 memory locations, whereas the ADALINE-FXLMS algorithm needs 2QQ + mmmmmm{qq, MM + } + 7 memory locations for computation of a single iteration. The comprehensive characteristics of the ADALINE- LMS and ADALINE-FXLMS algorithms are summarized in Table 2.2. Table 2.2: Overall characteristics of ADALINE-LMS and ADALINE-FXLMS algorithms Algorithms System stability Computational complexity Multiplications Additions Memory load ADALINE-LMS estimation algorithm ADALINE-FXLMS estimation algorithm 2 < ΔΔ qq (nn) < λλ mmmmmm (RR) where ΔΔ qqqqqqqq = 2 3tttt (RR) 2 < ΔΔ qq (nn) < σσ 2 xx σσ 2 h KK + 2DD eeee 2 where ΔΔ qqqqqqqq = σσ xx 2 σσ h 2 (KK+2DD eeee ) 2QQ + 7 2QQ + 3 2QQ + 7 2QQ + MM + 7 2QQ + MM + 2 2QQ + mmmmmm{qq, MM + } + 7 Remarks ADALINE-FXLMS provides better stability ADALINE-FXLMS has more computational complexity. ADALINE-FXLMS has faster convergence rate. ADALINE-FXLMS requires more memory 2.5 Simulation results Extensive time-domain simulation is conducted to demonstrate the effectiveness of proposed hybrid ADALINE-FXLMS algorithm for power system harmonic estimation. The distorted non-sinusoidal current signal considered for the estimation contains odd harmonics of 3 rrrr, 5 tth, 7 tth, 9 tth, tth, 3 tth and 5 tth apart from the fundamental. The expression of assumed signal is described as follows. ii (tt) = 2.2 ssssss(ωωtt ) ssssss(3ωωtt + 89 ) ssssss(5ωωtt 32.6 ) +.5 ssssss(7ωωtt 62.7 ) +.2 ssssss(9ωωtt ) +.9 ssssss(ωωtt ) +.54 ssssss(3ωωtt ) +.2 ssssss(5ωωtt + 2 ) + NNNNNNNNNN(tt) (2.44) Simulation results are analysed with four different sets of random noise such as no noise, db, db and db signal to noise ratio (SNR) corresponding to NN =,.36227,.8925 and. The test signal is sampled with khz and the supply 27

55 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm frequency is assumed to be 5 Hz. The preferred initial values are aa qq = bb qq =.8 and ΔΔ qq =.. The optimum values of constant parameters cc, cc 2 and cc 3 are.97,. and.99, respectively Estimation in the presence of noise Fig. 2.3 depicts the actual versus estimated signal using ADALINE-LMS and ADALINE-FXLMS algorithms. With all values of the gain factors corresponding to different noise levels, estimated signals based on ADALINE-FXLMS are almost identical to the actual signals. Whereas estimation based on ADALINE-LMS exhibits a minor deviation. Signal with no noise Signal with db SNR 2 Actual ADALINE-LMS 2 Actual ADALINE-LMS Amplitude (amp) - ADALINE-FXLMS Amplitude (amp) - ADALINE-FXLMS Time (sec) Time (sec) Signal with db SNR Signal with db SNR 2 Actual ADALINE-LMS 2 Actual ADALINE-LMS Amplitude (amp) - ADALINE-FXLMS Amplitude (amp) - ADALINE-FXLMS Time (sec) Time (sec) Fig. 2.3: Actual and estimated waveforms for test signal with different SNR values. The graphical comparison of actual and reconstructed fundamental component of the test signal with no noise, db, db and db SNR is shown in Fig From these figures, it is observed that highly accurate estimation is achieved by applying the proposed ADALINE-FXLMS algorithm. With the increase of noise level, the estimation employing ADALINE-LMS algorithm shows more deviation and higher oscillation during first fundamental period. 28

56 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm 5 Fundamental with no noise Actual 5 Fundamental with db SNR Actual Amplitude (amp) 5-5 ADALINE-LMS ADALINE-FXLMS Amplitude (amp) 5-5 ADALINE-LMS ADALINE-FXLMS - - Amplitude (amp) Time (sec) Fundamental with db SNR 5 Actual ADALINE-LMS ADALINE-FXLMS Time (sec) Amplitude (amp) Time (sec) Fundamental with db SNR 5 Actual ADALINE-LMS ADALINE-FXLMS Time (sec) Fig. 2.4: Actual and estimated waveforms for fundamental with different SNR values. 2 Harmonics with no noise Actual 2 Harmonics with db SNR Actual ADALINE-LMS ADALINE-LMS Amplitude (amp) - ADALINE-FXLMS Amplitude (amp) - ADALINE-FXLMS Amplitude (amp) Time (sec) Harmonics with db SNR 2 Actual ADALINE-LMS ADALINE-FXLMS - Amplitude (amp) Time (sec) Harmonics with db SNR 2 Actual ADALINE-LMS ADALINE-FXLMS Time (sec) Time (sec) Fig. 2.5: Actual and estimated waveforms for the sum of all harmonics with different SNR values. Fig. 2.5 shows the sum of 3 rrrr, 5 tth, 7 tth, 9 tth, tth, 3 tth and 5 tth harmonic components of the actual and reconstructed waveforms with different SNR values. It is observed that the ADALINE-FXLMS based estimation catches the original value by taking time slightly more than half of the fundamental period, even with high SNR (i.e. db SNR) values. Whereas estimation based on ADALINE-LMS algorithm tracks the original value after three-fourth of the fundamental period. 29

57 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm 5 Fundamental amplitude 8 3rd harmonic amplitude Amplitude (amp) 5 ADALINE-LMS ADALINE-FXLMS Time (sec) 5th harmonic amplitude 5 4 Amplitude (amp) ADALINE-LMS ADALINE-FXLMS Time (sec) 7th harmonic amplitude 5 ADALINE-LMS 4 ADALINE-FXLMS Amplitude (amp) 3 2 Amplitude (amp) 3 2 ADALINE-LMS ADALINE-FXLMS Time (sec) Time (sec) 5 9th harmonic amplitude 5 th harmonic amplitude ADALINE-LMS ADALINE-LMS 4 ADALINE-FXLMS 4 ADALINE-FXLMS Amplitude (amp) 3 2 Amplitude (amp) Time (sec) Time (sec) 5 3th harmonic amplitude 6 5th harmonic amplitude 4 ADALINE-LMS ADALINE-FXLMS 5 ADALINE-LMS ADALINE-FXLMS Amplitude (amp) 3 2 Amplitude (amp) Time (sec) Time (sec) Fig. 2.6: Estimated amplitude of fundamental and harmonic components for 5 db SNR. Fig. 2.6 illustrates the amplitude estimation of fundamental as well as individual harmonic component present in a distorted signal added with random noise of 5 db SNR. On the other hand, Fig. 2.7 exhibits the phase estimation of fundamental as well as individual harmonic component. It is evident from these figures that estimation based on ADALINE-LMS tracks the actual value almost after.2 s. These estimated values are slightly oscillating in nature that degrades the power quality assessment. However, the estimation employing ADALINE-FXLMS algorithm catches the actual value by taking less than.3 s with a greater accuracy and zero oscillation. 3

58 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Fundamental phase 3rd harmonic phase 5 5 Phase (deg) Phase (deg) -5 ADALINE-LMS -5 ADALINE-LMS ADALINE-FXLMS Time (sec) ADALINE-FXLMS Time (sec) 5th harmonic phase 7th harmonic phase ADALINE-LMS ADALINE-LMS 5 ADALINE-FXLMS 5 ADALINE-FXLMS Phase (deg) Phase (deg) Time (sec) Time (sec) 9th harmonic phase th harmonic phase 5 5 Phase (deg) Phase (deg) -5 ADALINE-LMS -5 ADALINE-LMS ADALINE-FXLMS Time (sec) ADALINE-FXLMS Time (sec) 3th harmonic phase 5th harmonic phase ADALINE-LMS 5 5 ADALINE-FXLMS Phase (deg) Phase (deg) -5 ADALINE-LMS ADALINE-FXLMS Time (sec) Time (sec) Fig. 2.7: Estimated phase of fundamental and harmonic components for 5 db SNR. Fig. 2.8 shows the estimated MSE of a test signal with different values of SNR by applying proposed and standard algorithms. It is observed that with zero noise level (i.e. no noise condition), the MSE obtained by applying both algorithms becomes zero after.5 s. But with the decrease in SNR values (i.e. with the increase in noise level), the magnitude of MSEs employing ADALINE-LMS algorithm is much more than ADALINE-FXLMS algorithm. In fact, the higher order harmonic components are more problematic in tracking the original value with the help of ADALINE-LMS algorithm. However, the calculated MSE for the signal added with db SNR lies in the order of.2 A and it is well within the acceptable range. 3

59 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Amplitude (amp) 5 x MSE with no noise ADALINE-LMS ADALINE-FXLMS Amplitude (amp) MSE with db SNR ADALINE-LMS ADALINE-FXLMS Time (sec) Time (sec).2 MSE with db SNR ADALINE-LMS.2 MSE with db SNR ADALINE-LMS ADALINE-FXLMS ADALINE-FXLMS.5.5 Amplitude (amp)..5 Amplitude (amp) Time (sec) Time (sec) Fig. 2.8: ADALINE-FXLMS estimation performance of MSEs with different SNR values Estimation in the presence of sub- and inter-harmonics Inter-harmonics are the non-integer multiples of system fundamental frequency. Interharmonics are considered as sub-harmonics when the frequencies are less than the fundamental frequency. In order to validate the efficacy of the proposed algorithm for harmonic estimation, the distorted signal is considered as a combination of a test signal along with a sub-harmonic component of 27.9 Hz frequency and an inter-harmonic component of Hz frequency. Now, we can represent this distorted waveform as ii (tt) =.2 ssssss(.558ωωtt ) + ii(tt) +.35 ssssss(5.53ωωtt ) (2.45) For assessment of parameters present in a distorted signal, the reference signals xx aaaa (nn) = ssssss(kkkkkk) and xx bbbb (nn) = cccccc(kkkkkk) are applied to the ADALINE structure as inputs; where KK =.55 and 5.53 for sub-harmonic and inter-harmonic components, respectively. The estimated coefficients aa (nn), KK bb (nn) KK are shown in Fig Fig. 2. shows the estimation of sub- and inter-harmonic components present in a distorted power signal. The waveforms evidently justify the superior performance of the ADALINE-FXLMS algorithm in maintaining a better accuracy even with the signal containing 3 db SNR. The estimated value based on ADALINE-LMS algorithm attains a steady-state reference value by taking more than.5 s, whereas estimation employing ADALINE-FXLMS maintains the same value within.5 s or less. 32

60 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Reference inputs for decaying DC component xx aaaaaa (nn) aa DDDD (nn) Σ nn xx bbbbbb (nn) bb DDDD (nn) ii(nn) ssssss(kkkkkk) xx aaaa (nn) xx bbbb (nn) bb KK (nn) aa (nn) KK Σ Σ yy(nn) h(zz) ii (nn) Σ ee(nn) cccccc(kkkkkk) Reference inputs for sub- and interharmonics xx bbbb (nn) h (zz) xx aaaa (nn) h (zz) yy (nn) Σ yy QQ (nn) From Fig. 2.2 LMS Adaptation Algorithm Fig. 2.9: Estimation in the presence of decaying DC component, sub- and inter-harmonics components. Amplitude (amp) Amplitude (amp) Sub-harmonic amplitude ADALINE-LMS ADALINE-FXLMS Time (sec) Inter-harmonic amplitude ADALINE-LMS ADALINE-FXLMS Time (sec) Phase (deg) Phase (deg) 5-5 Sub-harmonic phase ADALINE-LMS ADALINE-FXLMS Time (sec) 5-5 Inter-harmonic phase ADALINE-LMS ADALINE-FXLMS Time (sec) Fig. 2.: Estimated amplitude and phase of sub- and inter-harmonics components for 3 db SNR. Table 2.3 exhibits the percentage error of fundamental, harmonics, sub- and inter-harmonics using ADALINE-LMS and ADALINE-FXLMS algorithms. The percentage error can be calculated as EEEEEEEEEE (%) = AAAAAAAAAAAA vvvvvvvvvv EEEEEEEEEEEEEEEEEE vvvvvvvvvv AAAAAAAAAAAA vvvvvvvvvv (2.46) In this study, the percentage error is evaluated for the signal containing 3 db SNR. It can be noticed that the highest error occurs in the fundamental amplitude of 8.76% and 4.2%, and lowest error in the 3 tth harmonic amplitude of.7% and.4%, by 33

61 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm applying standard and proposed estimation techniques, respectively. Similarly, phase estimation employing ADALINE-LMS and ADALINE-FXLMS algorithms show highest error of 7.9% and 8.54% in the 5 tth harmonic, and lowest error of.3% and.4% in inter-harmonic, respectively. These errors are evaluated by comparing estimated and reference values at tt =.2 s. The estimation employing proposed algorithm claims lesser percentage error and reduced computational time as compared to the standard one. Table 2.3: Percentage error in ADALINE-LMS and ADALINE-FXLMS algorithm at 3 db SNR Methods Parameters Sub Fund 3 rrrr 5 tth Inter 7 tth 9 tth tth 3 tth 5 tth Freq (Hz) Actual Amplitude (A) Phase (deg) Amplitude (A) ADALINE- LMS estimation algorithm Error (%) Phase (deg) Error (%) Amplitude (A) ADALINE- FXLMS estimation algorithm Error (%) Phase (deg) Error (%) Estimation in the presence of DC decaying function The distorted current signal ii 2 (tt) with the presence of decaying DC component can be expressed as ii 2 (tt) = ii(tt) + II DDDD ee ( BBBB) (2.47) The Taylor-series expansion of the exponential function is ee BBtt = + ( BBtt)! + ( BBtt)2 2! + ( BBtt)3 3! + (2.48) Considering the first two terms and neglecting the higher order terms, the DC decaying function can be simplified as II DDDD ee ( BBtt) = II DDDD II DDDD BBBB (2.49) 34

62 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Amplitude (amp) Estimation of IDC ADALINE-LMS ADALINE-FXLMS Time (sec) (a) Fig. 2.: Estimated parameter of the DC decaying component for 3 db SNR. (a) Magnitude II DDDD. (c) Time constant BB. Magnitude Estimation of B.5 ADALINE-LMS ADALINE-FXLMS Time (sec) (b) Hence for estimation, the reference inputs are {xx aaaaaa (nn) =, xx bbbbbb (nn) = nn} and the corresponding coefficients are aa DDDD (nn), bb DDDD (nn) as depicted in Fig After updating the ADALINE s weight vector using adaptive algorithms, the DC decaying parameters can be calculated as II DDDD = aa DDDD (nn) (2.5) BB = bb (nn) DDDD aa (nn) DDDD (2.5) For simulation study, II DDDD =.5 A and BB = 2 s are chosen. A quantitative assessment of the DC decaying function for SNR of 3 db is shown in Fig. 2.. It is observed that estimation of decaying parameter employing ADALINE-FXLMS algorithm is very much accurate and the required convergence time is. s. However, estimation utilizing ADALINE-LMS algorithm needs.5 s and.8 s to track II DDDD and BB, respectively. Furthermore, these estimated values employing ADALINE-LMS are not so much accurate and marginally fluctuating in behavior Steady-state performance comparison Figs. 2.2(a) and (b) show the comparison of robustness in estimating the 5 tth harmonic amplitude and 3 tth harmonic phase for different values of SNR (i.e. db SSSSSS 8 db). The simulation results reveal that the accuracies of parameter estimation employing both the algorithms for a distorted signal with SNR of 8 db are more accurate and nearly equal. But with the decrease in SNR value, the ADALINE-FXLMS based estimation performs better and there is a less variation between actual and estimated components as compared to ADALINE-LMS. 35

63 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm (a) Fig. 2.2: Comparison of robustness of estimation with different SNR values. (a) 5 tth harmonic amplitude. (b) 3 tth harmonic phase. (b) Estimation of time-varying amplitude and phase The estimation of 7 tth order harmonic amplitude and 3 rrrr order harmonic phase under sudden step changes (i.e. amplitude varies from.5 A to.7 A and phase from 89 to 69 ) at tt =.2 s are illustrated in Figs. 2.3(a) and (b) respectively. It is observed from the results that estimation based on ADALINE-LMS algorithm tracks the actual value within.4 s. Whereas ADALINE-FXLMS based estimation exhibits the tracking of original amplitude and phase within.5 s and.5 s, respectively. It is concluded from this study that estimation based on ADALINE-LMS algorithm has lost its capability to track the step changes while estimation employing ADALINE-FXLMS algorithm exactly follows these changes with a minor delay. Amplitude (amp) th harmonic amplitude drif t Time (sec) (a) Actual ADALINE-LMS ADALINE-FXLMS Time (sec) Fig. 2.3: Dynamic response of signal for 3 db SNR. (a) Estimation of time-varying 7 tth harmonic amplitude. (b) Estimation of time-varying 3 rrrr harmonic phase. Amplitude (amp) rd harmonic phase drif t (b) Actual ADALINE-LMS ADALINE-FXLMS Estimation in the presence of dynamic signal To certify the performance of the ADALINE-FXLMS based estimation algorithm under dynamic state condition, the time-varying distorted signal can be represented as 36

64 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Fundamental amplitude of a dy namic signal.6 Amplitude (amp) Actual. ADALINE-LMS ADALINE-FXLMS Time (sec) Fig. 2.4: Estimated time-varying fundamental amplitude for 3 db SNR. ii 3 (tt) = {.2 + ii 3 } ssssss(ωωtt ) ssssss(3ωωtt + 89 ) +.5 ssssss(7ωωtt 62.7 ) +.2 ssssss(9ωωtt ) +.54 ssssss(3ωωtt ) + NNrrrrrrrr(tt) (2.52) where ii 3 is the amplitude modulating parameter and NN =.36 for 3 db SNR. The modulating parameter can be defined as ii 3 =.97 ssssss.ωωtt +.3 ssssss.3ωωtt (2.53) Fig. 2.4 shows the estimation of time-varying fundamental amplitude present in a distorted signal added with random noise. From this waveform, it is observed that the estimation based on ADALINE-LMS technique exhibits a major amplitude deviation along with poor convergence rate. However, estimation employing ADALINE-FXLMS algorithm shows the faster convergence speed, more accurate and less percentage error. 2.6 Experimental results In this section, the estimation employing ADALINE-FXLMS algorithm is investigated through scaled laboratory hardware setup. In addition, the estimation based on proposed algorithm is compared with the estimation performance employing conventional ADALINE-LMS. The experimental setup comprises of a single-phase thyristorised bridge rectifier feeding a DC motor as a nonlinear load and a series combination of 56 mh inductor and Ω resistor as a linear load. Both the loads are connected in parallel to 23 V, 5 Hz, single-phase source through an autotransformer. This type of combinational load injects a maximum number of harmonics into the system. Fig. 2.5 shows the single-line diagram of a test system, whereas Fig

65 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Voltage Source Line Impedance ii LL PCC 23 V 5 Hz Thyristor Rectifier PC (X64 processor, 3.4 GHZ, 8 GB RAM, 64 bit) with Interfacing Software Tektronix TDS22C Digital Storage Oscilloscope ( MHz) Tektronix TCPA3 Current Probe Amplifier ( MHz) Motor Linear Load Nonlinear Load Fig. 2.5: Single-line diagram of the test system for real-time signal parameter estimation. Fig. 2.6: A photograph of the complete hardware setup. depicts a photograph of the hardware setup including personal computer (PC) and other measuring instruments. Two Tektronix DMM42 digital-multimeters are used for accurate measurement of load current and source voltage. The distorted load current waveform is sensed at the PCC by the help of Tektronix TCPA3 current probe amplifier. Then this current signal is captured and stored by the Tektronix TDS22C digital storage oscilloscope (DSO) in the form of discrete values. Here, both DSO and current probe amplifier are operated at one sampling frequency of khz. The DSO is interfaced with the HP desktop PC via DSO-PC communication software. By using this software, the discrete data are transferred to the PC (X-64 processor with 8 GB RAM and 64-bit operating system). The digital real-time discrete data collected in the PC are analyzed with the help of MATLAB by implementing the proposed algorithm. The experimental load current waveform and its spectrum recorded by the DSO are shown in Figs. 2.7(a) and (b) respectively. The measured load current is fully 38

66 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm (a) (b) Fig. 2.7: Experimental waveforms recorded by DSO. (a) Load current. (b) Spectrum of load current. distorted that contains fundamental, harmonics, sub-harmonics, inter-harmonics and additive noise. In Fig. 2.7(b), a sub-harmonic component of 25 Hz, an inter-harmonic component of 575 Hz and fundamental are represented as S, I and F respectively. Similarly, H 3, H 5, H 7, H and H 3 are denoted as 3 rrrr, 5 tth, 7 tth, tth and 3 tth harmonic components correspondingly Computation of estimated signals From the real-time data, a comparative estimation of the test signal, its fundamental, the signal comprising of harmonic components (sum of harmonics up to 99 tth order) and magnitude of the MSE as obtained by using ADALINE-LMS and ADALINE-FXLMS Amplitude (amp) 5-5 Actual and estimated signals Actual ADALINE-LMS ADALINE-FXLMS Amplitude (amp) Estimated f undamental ADALINE-LMS ADALINE-FXLMS Amplitude (amp) Time (sec) (a) 5-5 Estimated sum of harmonics ADALINE-LMS ADALINE-FXLMS Amplitude (amp) Time (sec) (b) MSE ADALINE-LMS ADALINE-FXLMS Time (sec) (c) Fig. 2.8: Estimation of signals from a real-time data. (a) Actual and estimated signals. (b) Estimated fundamentals. (c) Estimated sum of all harmonics. (d) Estimated MSEs Time (sec) (d)

67 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm algorithms are shown in Figs. 2.8(a)-(d), respectively. It is evident from these figures that the proposed algorithm completely filters out the additive noise generated from the hardware model and produces accurate estimation results. The tracking time is. s, which is same as the results obtained in the simulation. However, estimation based on the ADALINE-LMS algorithm suffers from wide oscillation before achieving the steady-state value. This algorithm takes more than.2 s for settling down to the actual value Computation of estimated amplitudes and phases By employing proposed and conventional algorithms, estimated amplitude and phase of the fundamental ( F ), harmonics ( H 3, H 5, H 7, H and H 3 ), sub-harmonic ( S ) and inter-harmonic ( I ) components are shown in Figs. 2.9 and 2.2 respectively. When the nonlinear load is connected to the distribution system, suddenly some amounts of sub- and inter-harmonic components are generated. After ten fundamental periods (i.e..2 s), the system achieves a steady-state and then their parameters reaches Amplitude (amp) Estimated f undamental amplitude ADALINE-LMS ADALINE-FXLMS Time (sec).8 Estimated 5th harmonic amplitude ADALINE-LMS ADALINE-FXLMS Amplitude (amp) Estimated 3rd harmonic amplitude ADALINE-LMS ADALINE-FXLMS Time (sec).5 Estimated 7th harmonic amplitude ADALINE-LMS ADALINE-FXLMS Amplitude (amp).6.4 Amplitude (amp) Time (sec) Time (sec) Estimated th harmonic amplitude ADALINE-LMS Estimated 3th harmonic amplitude ADALINE-LMS.8 ADALINE-FXLMS.8 ADALINE-FXLMS Amplitude (amp).6.4 Amplitude (amp) Time (sec) Time (sec) Fig. 2.9: Estimation of amplitude of fundamental and harmonic components from a real-time data. 4

68 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm Estimated sub-harmonic (25 Hz) amplitude ADALINE-LMS.5 Estimated inter-harmonic (575 Hz) amplitude ADALINE-LMS 8 ADALINE-FXLMS ADALINE-FXLMS Amplitude (amp) 6 4 Amplitude (amp) Time (sec) Time (sec) Fig. 2.9: (Continued) estimation of amplitude of sub- and inter-harmonics. Estimated f undamental phase ADALINE-LMS Estimated 3rd harmonic phase ADALINE-LMS ADALINE-FXLMS ADALINE-FXLMS 5 5 Phase (deg) Phase (deg) Time (sec) Time (sec) Estimated 5th harmonic phase ADALINE-LMS Estimated 7th harmonic phase ADALINE-LMS ADALINE-FXLMS ADALINE-FXLMS 5 5 Phase (deg) Phase (deg) Time (sec) Time (sec) Estimated th harmonic phase ADALINE-LMS Estimated 3th harmonic phase ADALINE-LMS ADALINE-FXLMS ADALINE-FXLMS 5 5 Phase (deg) Phase (deg) Time (sec) Time (sec) Estimated sub-harmonic (25 Hz) phase ADALINE-LMS Estimated inter-harmonic (575 Hz) phase ADALINE-LMS ADALINE-FXLMS ADALINE-FXLMS 5 5 Phase (deg) Phase (deg) Time (sec) Time (sec) Fig. 2.2: Estimation of phase of fundamental, harmonic, sub- and inter-harmonics components from a real-time data. 4

69 Chapter 2: Harmonics estimation employing hybrid ADALINE-FXLMS algorithm a constant or zero value. In general, at tt = + s, the signal parameter shows transient behaviour due to the initial interaction between the harmonic components. Therefore, for power quality assessment, we neglect three cycles for uncontrolled nonlinear loads and five cycles for controlled nonlinear loads. After the settling time, the system achieves a steady state and parameter maintains a fixed value, then it is considered for estimation. From figures, it is seen that estimation based on ADALINE-FXLMS algorithm takes iterations (i.e.. s) to track the actual value of each harmonic component, whereas estimation employing ADALINE-LMS algorithm requires 2 iterations (i.e..2 s) to catch the same value. The time of convergence for estimation using ADALINE-FXLMS is around half of the time taken by ADALINE-LMS based estimation. By introducing transfer functions in the primary and secondary path, the overall performance of the proposed algorithm is drastically improved for all types of noisy conditions. 2.7 Chapter summary In this chapter, a new hybrid ADALINE-FXLMS algorithm is proposed for fast and accurate measurement of harmonic amplitude and phase in a distorted current signal. Extensive simulation is carried out for different SNR values using MATLAB to appraise the speed of convergence and tracking capability of the proposed algorithm. It is clearly revealed from the simulation results that the highest amplitude and phase error by employing proposed algorithm are 4.2% and 8.54%, respectively. During estimation, the step size parameter can also be increased to the upper-bound limit without affecting the system stability. Moreover, the proposed algorithm is solid and robust to assess the distorted signal added with sub-harmonics, inter-harmonics, timevarying signal and decaying DC component. Finally, the proposed algorithm has been implemented in a real-time prototype model. The overall simulation and experimental results have demonstrated that the proposed ADALINE-FXLMS estimation algorithm is superior and more effective as compared to conventional ADALINE-LMS based scheme. 42

70 Chapter 3 Power Quality Enhancement Using Shunt APF with Nonlinear Control Strategy 3. Introduction The extensive use of nonlinear loads creates harmonic-related problems in the distribution power system network. To mitigate the harmonics present in a distorted power signal, many compensating methods were developed and described in the literature. Conventional passive filters are commonly used to compensate harmonics since they are simple and cost effective. However, these compensators have many drawbacks such as fixed compensation, large size and causing series/parallel resonance. In contrast, dynamic compensation employing APF is considered as a viable solution for power quality improvement. It is important to investigate the performance of APF with a suitable control strategy for improving the power quality of a system under various scenarios. The APF produces a compensating current having the same magnitude and opposite phase with the harmonics produced by the nonlinear load in a distribution system to make the source current sinusoidal and it contains only 43

71 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy fundamental active component [6-74]. The performance of APF mainly depends on the selection of suitable harmonic extraction method and PWM control strategy. This chapter is devoted to develop the system dynamic modeling and investigate the performance of shunt APF employing nonlinear control strategy for power quality enhancement in a distribution power system network connected to nonlinear loads. The harmonic detection circuit (i.e. known as current control loop) for estimation of reference signals and the self-charging circuit (i.e. known as voltage control loop) for DC-link voltage regulation are implemented in time-domain approach. This technique is used to achieve a stable operation under various operating scenarios. The shunt APF is modeled in the stationary abc reference frame and then it is transformed to the rotating dq reference frame with the aim of reducing the control complexity. The exact feedback linearization technique is used to decouple the current control loop variables, such that the d- and q-axis current dynamics are regulated independently [3, 67-7, 5]. Further, this control strategy boosts the tracking performance and improves the DC-link voltage regulation. The steady-state and dynamic responses of the APF using nonlinear control strategy are attained via MATLAB/Simulink based computer simulation. The performance is verified under various demanding situations of source and load. 3.2 Modelling of three-phase shunt APF Fig. 3. shows the main circuit configuration of three-phase shunt APF connected in parallel with the nonlinear load. The APF consists of three-phase VSI using six IGBTs, a DC-link capacitor of capacitance CC dddd, and three high-frequency inductors of inductance LL ff and resistance RR ff. The DC-link capacitor maintains a DC voltage vv dddd and regulates real power necessary to meet the losses of a system. On the other hand, inductors perform the voltage boost operation in combination with the capacitor, and at the same time act as the low pass filter. The source is assumed to be balanced with the input impedance of series connected resistance RR ff and inductance LL ss in each phase. A three-phase diode bridge rectifier with RRRR or RRRR load is considered as a current- or voltage-source type nonlinear load respectively. Whereas, single-phase diode bridge rectifier with RL load is connected to two phases (i.e. phase-b and c) to make the load 44

72 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Single-phase Nonlinear Load Inductive Load Switch vv ssss LL ss RR ss ii ssss PCC ii LLLL vv ssss ii ssss ii LLLL Inductive/ Capacitive Load vv ssss ii ssss ii LLLL Grid LL ff Three-phase Nonlinear Load RR ff ss cc ss bb ss aa ii dddd ii ffff ii ffff vv dddd CC dddd ii ffff vv aaaa vv bbbb vv cccc vv aa vv bb vv cc vv aa vv bb vv cc ss cc ss bb Active Power Filter ss aa VV MM Common Node MM vv MMMM VV NN = V Mains Neutral Point NN Fig. 3.: Main circuit configuration of three-phase shunt APF connected to nonlinear loads. current in the system unbalanced. In this figure, vv ssss, vv kk, vv kk, vv kkkk, ii ssss, ii LLLL and ii ffff represent three-phase source voltage, voltage measured at PCC with respect to neutral point NN, output voltage of VSI with respect to neutral point NN, output voltage of VSI with respect to common node MM, source current, load current and compensating current respectively. Where kk = aa, bb, cc for phase-a, b, and c correspondingly. vv dddd and ii dddd are denoted as DC-link voltage and current respectively. When vv kk > vv kk, APF generates leading reactive power or else it absorbs lagging reactive power. If both the voltages are equal, then the exchange of reactive power between APF and PCC will be zero Dynamic model of APF in abc reference frame In order to obtain the dynamic model of the APF, Kirchhoff s voltage and current laws are applied at the PCC of the distribution system as shown in Fig. 3.. Based on the 45

73 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy circuit analysis, the differential equations in the stationary abc frame may be expressed as vv aa = LL ff dddd ffff dddd vv bb = LL ff dddd ffff dddd vv cc = LL ff dddd ffff dddd + RR ff ii ffff + vv aaaa + vv MMMM (3.) + RR ff ii ffff + vv bbbb + vv MMMM (3.2) + RR ff ii ffff + vv cccc + vv MMMM (3.3) For three-phase three-wire system, it may be assumed that the supply voltages are balanced and thus zero sequence components are absent. Therefore, we can write vv aa + vv bb + vv cc = ii ssss + ii ssss + ii ssss = ii LLLL + ii LLLL + ii LLLL = (3.4) (3.5) (3.6) ii ffff + ii ffff + ii ffff = (3.7) By using (3.4) and (3.7), the summation of (3.)-(3.3) can be simplified as [vv aa + vv bb + vv cc ] = LL ff dddd ffff dddd + dddd ffff dddd + dddd ffff dddd + RR ff ii ffff + ii ffff + ii ffff + [vv aaaa + vv bbbb + vv cccc ] + 3vv MMMM vv MMMM = 3 [vv aaaa + vv bbbb + vv cccc ] (3.8) The switching functions QQ aa, QQ bb and QQ cc of the VSI are determined depending on the ON/OFF status of the switches ss aa, ss aa, ss bb, ss bb, ss cc and ss cc as follows. QQ aa =,, if ss aa is ON and ss aa is OFF if ss aa is OFF and ss aa is ON QQ bb =,, if ss bb is ON and ss bb is OFF if ss bb is OFF and ss bb is ON QQ cc =,, if ss cc is ON and ss cc is OFF if ss cc is OFF and ss cc is ON (3.9) (3.) (3.) Considering the switching status of leg-a, the equivalent circuit is shown in Fig. 3.2 and the associated equations are described as follows. vv aaaa = QQ aa vv dddd (3.2) 46

74 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy ii dddd ss aa (ON) ii dddd ss aa (OFF) ii ffff ii ffff vv dddd CC dddd vv dddd CC dddd ss aa (OFF) vv aaaa ss aa (ON) vv aaaa Condition-: When ss aa is on and ss aa is off, then QQ aa = vv aaaa = vv dddd = QQ aa vv dddd ii dddd = ii ffff = QQ aa ii ffff Condition-2: When ss aa is off and ss aa is on, then QQ aa = vv aaaa = = QQ aa vv dddd ii dddd = = QQ aa ii ffff Fig. 3.2: Calculation of inverter output voltage with respect to common node MM (vv aaaa ) and DC-link capacitor current (ii dddd ), in terms of switching function (QQ aa ). vv bbbb = QQ bb vv dddd vv cccc = QQ cc vv dddd (3.3) (3.4) By summing (3.2)-(3.4), we have [vv aaaa + vv bbbb + vv cccc ] = [QQ aa + QQ bb + QQ cc ]vv dddd (3.5) Using (3.5) and (3.8), vv MMMM can be modified as vv MMMM = vv dddd 3 [QQ aa + QQ bb + QQ cc ] (3.6) By re-writing (3.), the phase-a dynamic model of the APF is expressed by the following equation LL ff dddd ffff dddd = RR ff ii ffff vv aaaa vv MMMM + vv aa (3.7) On the simplification of (3.7) using (3.2) and (3.6), we have LL ff dddd ffff dddd = RR ff ii ffff QQ aa vv dddd + vv dddd 3 [QQ aa + QQ bb + QQ cc ] + vv aa = RR ff ii ffff (QQ aa [QQ aa +QQ bb +QQ cc ] )vv 3 dddd + vv aa (3.8) Similarly, the dynamic equations for phase-b and c can be expressed as follows LL ff dddd ffff dddd LL ff dddd ffff dddd = RR ff ii ffff (QQ bb [QQ aa +QQ bb +QQ cc ] )vv 3 dddd + vv bb (3.9) = RR ff ii ffff (QQ cc [QQ aa +QQ bb +QQ cc ] )vv 3 dddd + vv cc (3.2) In (3.8)-(3.2), three new equivalent switching state functions dd nnnn, dd nnnn and dd nnnn can be defined as 47

75 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy dd nnnn = QQ aa [QQ aa +QQ bb +QQ cc ] 3 dd nnnn = QQ bb [QQ aa +QQ bb +QQ cc ] 3 dd nnnn = QQ cc [QQ aa +QQ bb +QQ cc ] 3 = 2QQ aa QQ bb QQ cc = QQ aa + 2QQ bb QQ cc = QQ aa QQ bb + 2QQ cc (3.2) (3.22) (3.23) Equations (3.2)-(3.23) show that the values of dd nnnn, dd nnnn and dd nnnn depend on the switching state nn and the phase kk. In fact, the three-phase VSI has eight permissible switching states (i.e. nn =,, 2,, 7) [68]. The matrix of switching state functions can be expressed as dd nnnn 2 QQ aa dd nnnn = 2 QQ 3 bb (3.24) dd nnnn 2 QQ cc The transformation matrix in (3.24) is of rank 2 and the system [dd nnnn ] has no zerosequence components. The possible values for switching state functions dd nnnn, dd nnnn and dd nnnn are, ± and ± 2, respectively [7]. 3 3 Considering Fig. 3.2, the DC side of the inverter can be modeled with the following differential equation CC dddd dddd dddd dddd = ii dddd = QQ aa ii ffff + QQ bb ii ffff + QQ cc ii ffff = 3 [3QQ aaii ffff + 3QQ bb ii ffff + 3QQ cc ii ffff ] = 3 [QQ aa(3ii ffff ii ffff ii ffff ii ffff ) + QQ bb (3ii ffff ii ffff ii ffff ii ffff ) + QQ cc (3ii ffff ii ffff ii ffff ii ffff )] = 3 [QQ aa 2ii ffff ii ffff ii ffff + QQ bb ii ffff + 2ii ffff ii ffff + QQ cc ( ii ffff ii ffff + 2ii ffff )] = 3 [2QQ aaii ffff QQ aa ii ffff QQ aa ii ffff QQ bb ii ffff + 2QQ bb ii ffff QQ bb ii ffff QQ cc ii ffff QQ cc ii ffff + 2QQ cc ii ffff ] = 3 [(2QQ aa QQ bb QQ cc )ii ffff + ( QQ aa + 2QQ bb QQ cc )ii ffff + ( QQ aa QQ bb + 2QQ cc )ii ffff ] = [dd nnnn ii ffff + dd nnnn ii ffff + dd nnnn ii ffff ] (3.25) Furthermore, using the assumption dd nnnn + dd nnnn + dd nnnn = and (3.7), the preceding equation may be simplified to CC dddd dddd dddd dddd = [dd nnnn ii ffff + dd nnnn ii ffff + dd nnnn ii ffff ] 48

76 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy = [dd nnnn ii ffff + dd nnnn ii ffff + ( dd nnnn dd nnnn )( ii ffff ii ffff )] = [(2dd nnnn + dd nnnn )ii ffff + (dd nnnn + 2dd nnnn )ii ffff ] (3.26) The introduction of three inductor equations of the AC side and a DC-link capacitor equation of the DC side describe the complete state model in abc reference frame. In this model, only two independent AC currents are needed because the zero sequence components are nil. LL ff dddd ffff dddd = RR ff ii ffff dd nnnn vv dddd + vv aa (3.27) LL ff dddd ffff dddd = RR ff ii ffff dd nnnn vv dddd + vv bb (3.28) CC dddd dddd dddd dddd = [(2dd nnnn + dd nnnn )ii ffff + (dd nnnn + 2dd nnnn )ii ffff ] (3.29) Comparing (3.) with (3.27) and (3.2) with (3.28), we can express dd nnnn vv dddd = vv aaaa + vv MMMM = vv aa and dd nnnn vv dddd = vv bbbb + vv MMMM = vv bb, as the input voltages of VSI in phase-a and phase-b respectively Model transformation into dq reference frame To facilitate the controller design, the model can be transformed to the synchronous orthogonal frame rotating at the supply frequency ωω. With this time-varying transformation, the positive-sequence components become constant, and the effect of interaction between the phases is avoided at the switching state decision level. The general transformation from abc to dq is expressed as follows xx dd cccccc θθ cccccc(θθ 2ππ ) cccccc(θθ 4ππ ) 3 3 xx xx qq = 2 3 ssssss θθ ssssss(θθ 2ππ ) ssssss(θθ 4ππ ) 3 3 xx xx 2 (3.3) xx 3 where θθ is the Park s transformation angle of the rotating frame and xx denotes currents, voltages or switching functions. To simplify the analysis, the angle is determined by the angular position of the voltages first harmonic positive-sequence system i.e. θθ = ωωtt. From (3.27)-(3.3), the state space equations of shunt APF in the synchronous rotating frame can be expressed as LL ff dddd ffff dddd = RR ff ii ffff + ωωll ff ii ffff dd nnnn vv dddd + vv dd (3.3) 49

77 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy LL ff dddd ffff dddd = RR ff ii ffff ωωll ff ii ffff dd nnnn vv dddd + vv qq (3.32) CC dddd dddd dddd dddd = dd nnnn ii ffff + dd nnnn ii ffff (3.33) This state-space model is nonlinear because of the existence of multiplication terms between the state variables ii dd, ii qq, vv dddd and the switching state functions dd nnnn, dd nnnn. However, this model is time-invariant during a given switching state. Furthermore, the three-phase voltages measured at PCC are assumed to be sinusoidal and symmetrical, and can be expressed as vv aa = vv mm cccccc(ωωωω) (3.34) vv bb = vv mm cccccc(ωωωω 2ππ 3 ) (3.35) vv cc = vv mm cccccc(ωωtt 4ππ 3 ) (3.36) where vv mm is the amplitude of the phase voltages. Using (3.3), the transformation to the synchronous reference frame yields vv dd = 3 2 vv mm (3.37) vv qq = (3.38) 3.3 Implementation of control strategies The implementation of control strategy for power quality enhancement using APF requires three state variables, i.e. ii dd, ii qq, vv dddd that must be controlled independently. Therefore, two loops are considered, namely current control loop for generation of reference signals and voltage control loop for maintaining DC-link capacitor voltage vv dddd. Furthermore, the interaction between two loops can be avoided by separating their respective dynamics. Fig. 3.3 shows the overall control structure for shunt APF. The three-phase load and filter currents are sensed and transformed to the synchronous reference frame using (3.3). These transformed currents are used as feedback signals of proportional integral (PI) controllers to evaluate the reference values. A pole-zero cancellation theory (i.e. insertion of pre-filters) is proposed in the current control loop for providing fast current harmonic compensation and simplifies the control scheme. In 5

78 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy II 2 vv dddd 3 vv mm UU dddd GG vv (SS) vv dddd vv dddd Gain PI Controller Voltage Control Loop vv dddd vv dd = vv mm ii dd Pre-filter + TT dd SS ii dd PI Controller II dd UU dd dd nnnn vv dddd GG dd (SS) dd nnnn ss aa ss aa ii LLLL ii LLLL ii LLLL ωωtt Calculation of d- and q- axis Reference Currents (Fig. 3.4) ii ffff ii ffff ii ffff ωωtt abc-dq Sync. Frame Trans ii ffff ii ffff ωωll ff Mutual Interference Terms ωωll ff ωωll ff II ffff vv dddd vv dddd PWM Control System (Fig. 3.8) ss bb ss bb ωωll ff II ffff ii qq + TT qq SS ii qq II qq GG qq (SS) Current Control Loop UU qq vv qq = dd nnnn vv dddd dd nnnn ss cc ss cc Gating Signals Fig. 3.3: Control block diagram of shunt APF. addition, one PI controller is used in the voltage control loop to maintain the DC-link capacitor voltage to its reference level. Furthermore, the amplitude and phase of the VSI output voltage must be adjusted using PWM control strategy, which produces either leading or lagging reactive power. The calculation of d-q axis reference values, current control loop, voltage control loop and PWM control system are described in subsequent sub-sections as follows Calculation of d- and q-axis references The reference currents for current control loop are obtained by extracting the harmonic currents from the transformed load currents as shown in Fig The distorted load currents ii LLLL, ii LLLL and ii LLLL are sensed and transformed into ii LLLL and ii LLLL using Park s transformation. The d- and q-axis currents ii LLLL and ii LLLL are processed through two first order low pass filters (LPFs) to isolate their respective DC quantities ii LLLLLL, ii LLLLLL. The difference between ii LLLL, ii LLLL and ii LLLLLL, ii LLLLLL is referred as harmonic currents ii LLLLh, ii LLLLh. In this figure, TT dd = TT qq denotes the delay time between the transformed load currents and reference currents of an APF, and ωω dd = ωω qq represents the cutoff frequency of LPFs. These cutoff frequencies affect the APF compensation characteristics such as current harmonic elimination, settling time of the DC-link voltage and stability of the control scheme. In this study, the cutoff frequencies of each 5

79 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy II ii LLLL ii LLLL ii LLLL abc-dq Sync. Frame Trans ii LLLL ii LLLL + TT dd SS LPF + TT qq SS ii LLLLLL ii LLLLLL ii LLLLh ii LLLLh ii LLLLh ii LLLLh ii dd ii qq ωωtt Fig. 3.4: Block diagram of d- and q-axis references for current control loop. LPF are chosen as ωω dd = ωω qq = ωω 3. The references ii dd and ii qq for respective current control loop are obtained as follows ii dd = ii LLLLh + II (3.39) ii qq = ii LLLLh (3.4) Current control loop The d- and q-axis current control loop employed for the APF operation is illustrated in Fig In order to design the current control loop, (3.3) and (3.32) can be rewritten as follows RR ff ii ffff +LL ff dddd ffff dddd RR ff ii ffff +LL ff dddd ffff dddd = ωωll ff ii ffff dd nnnn vv dddd + vv dd (3.4) = ωωll ff ii ffff dd nnnn vv dddd + vv qq (3.42) It is seen from (3.4) and (3.42) that mutual interference terms ωωll ff ii ffff and ωωll ff ii ffff exist in the d- and q-axis dynamics, respectively. Therefore, the voltage decouplers are designed to decouple the current control loops and simplify the control scheme [3, 69, 5]. Let us define the new input variables UU dd and UU qq as voltage commands of the current regulators. From (3.4) and (3.42), we may represent UU dd = ωωll ff ii ffff dd nnnn vv dddd + vv dd (3.43) UU qq = ωωll ff ii ffff dd nnnn vv dddd + vv qq (3.44) The voltage commands for current regulation in (3.43) and (3.44) can be modified as follows UU dd = GG dd (ss)δδii dd (3.45) UU qq = GG qq (ss)δδii qq (3.46) 52

80 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Current Control Loop APF Model vv dd = vv mm vv dd = vv mm II dd II dd UU dd GG dd (SS) dd nnnn vv dddd dd nnnn dd nnnn dd nnnn vv dddd UU dd RR ff + SSLL ff II ffff ωωll ff II ffff vv dddd vv dddd II ffff ωωll ff II ffff ωωll ff ωωll ff II ffff ωωll ff ωωll ff vv dddd vv dddd ωωll ff II ffff ωωll ff II ffff II qq II qq GG qq (SS) UU qq dd nnnn vv dddd dd nnnn dd nnnn dd nnnn vv dddd UU qq RR ff + SSLL ff II ffff vv qq = vv qq = Fig. 3.5: Control block diagram of d- and q-axis current controller of the APF. where ΔΔII dd = II dd II ffff and ΔΔII qq = II qq II ffff, are the current errors in d- and q-axis respectively. The PI controllers adopted using (3.45) and (3.46) are described as follows GG dd (ss) = UU dd (ss) ΔΔII dd (ss) = KK PPPP + KK IIII SS GG qq (ss) = UU qq (ss) = KK ΔΔII qq (ss) PPPP + KK IIII SS (3.47) (3.48) where KK PPPP and KK IIII are proportional and integral gains of d-axis current control loop respectively. Similarly, KK PPPP and KK IIII are proportional and integral gains of q-axis current control loop respectively. The current control loop as demonstrated in Fig. 3.5 can be further simplified to Fig Using (3.4) and (3.42), we can write UU dd = RR ff ii ffff +LL ff dddd ffff dddd (3.49) UU qq = RR ff ii ffff +LL ff dddd ffff dddd (3.5) Applying Laplace transform on (3.49) and (3.5), the open-loop transfer functions of the APF s resistive-inductive branches can be derived as II ffff (SS) UU dd (SS) = RR ff +SSLL ff (3.5) II ffff (SS) UU qq (SS) = RR ff +SSLL ff (3.52) 53

81 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy II dd + TT KKKK SS II dd KK PPPP UU dd RR ff + SSLL ff II ffff Pre-filter II ffff KK IIII SS GG dd (SS) GG aa (SS) (a) II qq + TT KKKK SS II qq KK PPPP UU qq RR ff + SSLL ff II ffff Pre-filter II ffff KK IIII SS GG qq (SS) GG bb (SS) (b) Fig. 3.6: Equivalent control block diagram. (a) d-axis current loop. (b) q-axis current control loop. By multiplying (3.47) and (3.5), the open loop transfer function GG aa (SS) for d-axis current controller can be obtained as GG aa (ss) = II ffff (SS) = UU dd (ss) II ffff (SS) ΔΔII dd (ss) ΔΔII dd (ss) UU dd (SS) = KK PPPP + KK IIII SS RR ff +SSLL ff = SSKK PPPP +KK IIII SS 2 LL ff +SSRR ff (3.53) Referring Fig 3.6(b), the open loop transfer function GG bb (SS) for q-axis current control loop can be written as GG bb (ss) = SSKK PPPP +KK IIII SS 2 LL ff +SSRR ff For d-axis current control loop, the closed-loop transfer function II ffff (SS) as follows II dd (SS) (3.54) can be derived II ffff (SS) II dd (SS) = GG aa (ss) +GG aa (ss) = SSKK PPPP +KK IIII SS 2 LL ff +SSRR ff + SSKK PPPP +KK IIII SS 2 LL ff +SSRR ff = SSKK PPPP +KK IIII SS 2 LL ff +SS RR ff +KK PPPP +KK IIII = SSKK PPPP +KK IIII LL ff SS 2 +SS RR ff +KK PPPP + KK IIII LL ff LL ff 54

82 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy = SSKK PPPP +KK IIII LL ff KK IIII LL ff LL ff KK IIII SS KK IIII LL ff LL ff RR ff +KK PPPP KK IIII LL ff SS+ KK IIII LL ff 2 = + KK PPPP KK IIII SS 2 KK IIII LL ff SS LL ff RR ff +KK PPPP KK IIII LL KK IIII ff LL SS+ KK IIII ff LL ff 2 (3.55) Comparing the preceding equation with the standard second order transfer function ωω 2 nnnn SS 2 +2ζζωω nnnn SS+ωω 2 nnnn, the following design relations are obtained. ωω nnnn = KK IIII LL ff KK IIII = ωω nnnn 2 LL ff (3.56) ζζ = 2 LL ff KK IIII RR ff +KK PPPP LL ff KK PPPP = 2ζζωω nnnn LL ff RR ff (3.57) where ωω nnnn is the natural un-damped angular frequency and ζ is damping factor. For considering the optimal value of the damping factor as ζζ =.77, the theoretical overshoot is 2%. The transient response of (3.55) is affected due to the presence of zero i.e. SS = KK IIII KK PPPP. In order to eliminate this zero in the closed loop transfer function, a pre-filter GG PPPP (SS) is introduced before the current control loop as shown in Fig. 3.6(a). GG PPPP (SS) = +TT KKKK SS (3.58) where TT KKKK = KK PPPP KK IIII = ωω KKKK denotes the delay time constant of d-axis pre-filter. The current control loop with pre-filter becomes a second order system. Likewise, the design parameters KK PPPP and KK IIII for q-axis PI controller, and the transfer function of pre-filter GG PPPP (SS) can be expressed as KK IIII = ωω nnnn 2 LL ff (3.59) KK PPPP = 2ζζωω nnnn LL ff RR ff (3.6) GG PPPP (SS) = +TT KKKK SS (3.6) 55

83 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy From (3.43) and (3.44), the switching state functions known as reference inputs dd nnnn and dd nnnn of the VSI are computed from the input voltage commands UU dd and UU qq, and the system variables ii ffff, ii ffff and vv dddd as follows. dd nnnn = vv mm +ωωll ff ii ffff vv dddd UU dd vv dddd (3.62) dd nnnn = ωωll ffii ffff vv dddd UU qq vv dddd (3.63) In (3.62) and (3.63), the calculated control inputs dd nnnn and dd nnnn are constituted as the combination of nonlinear compensation parts vv mm +ωωll ff ii ffff vv dddd and ωωll ffii ffff, and linear vv dddd decoupling compensation parts UU dd vv dddd and UU qq vv dddd. The maximum order of current harmonics to be injected is imposed by the PWM switching frequency that is obtained by the current controller response. Thus a high value of ωω nn is desired. However, because of physical limitations, ωω nn must be kept below the switching angular frequency ωω ss. A value of ωω nnnn = ωω nnnn = ωω nn = ωω ss 5 is used during the simulation study. If the PWM switching frequency is sufficiently high, the delay between reference inputs of current controller and actual switching state functions of the APF will be reduced significantly. Hence, we have dd nnnn = dd nnnn dd nnnn = dd nnnn (3.64) (3.65) Voltage control loop Considering balanced three-phase supply voltage, the instantaneous real power pp LL and reactive power qq LL on the load side can be expressed as pp LL = 3 vv 2 mm ii LLLL (3.66) qq LL = 3 vv 2 mm ii LLLL (3.67) For a fully harmonic-current compensated system using APF, the instantaneous real power pp ss and reactive power qq ss on the source side can be written as pp ss = 3 vv 2 mm ii LLLLLL (3.68) 56

84 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy vv dddd vv dddd KK PPPP UU dddd SSCC dddd vv dddd vv dddd KK IIII SS GG vv (SS) GG cc (SS) Fig. 3.7: Equivalent control block diagram of voltage control loop. qq ss = (3.69) where ii LLLLLL denotes the fundamental component of the load current and it is obtained from the LPF is shown in Fig If the real power pp ss supplied from the source cannot fulfill the load demand pp LL, then the difference of these two real powers pp must be injected into or supplied from the DC-link capacitor. Thus it will result the variation of DC-link capacitor voltage. In addition, the losses occurred in the APF s resistiveinductive components could be compensated by producing an additional current component II as depicted in Fig The expression for pp to maintain unity power factor on the source side is formulated as pp = pp ss pp LL = 3 2 vv mm ii LLLLLL 3 2 vv mm ii LLLL = 3 2 vv mm (ii LLLLLL ii LLLL ) (3.7) The difference in real powers pp must be controlled and set to be zero under steadystate. Therefore, it is necessary to design a voltage control loop for charging and regulating the DC-link capacitor voltage at a fixed reference level [6, 69]. The closedloop control strategy of the DC-link voltage controller is shown in Fig Referring (3.33), the equivalent input UU dddd can be defined as UU dddd = dd nnnn ii ffff + dd nnnn ii ffff (3.7) where UU dddd is the current command of voltage controller. It can be modified by considering PI controller gain GG vv (SS) as follows UU dddd = GG vv (SS) vv dddd (3.72) where vv dddd = vv dddd vv dddd, vv dddd and vv dddd denote as error, reference and actual values of the DC-link voltage control loop respectively. The actual DC-link voltage is detected and compared with the reference voltage and then the difference is fed to the PI 57

85 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy controller. Based on the voltage difference, the PI controller decides how much active current is essential for unit power factor operation. If the two voltages are different, it means that the blocking voltages across upper and lower controlled switches are not equal. The simple PI controller gain is expressed as follows GG vv (SS) = UU dddd (SS) vv dddd (ss) = KK PPPP + KK IIII SS (3.73) where KK PPPP and KK IIII are the proportional and integral gain of DC-link voltage feedback control loop respectively. From (3.33) and (3.7), it can be written as UU dddd = CC dddd dddd dddd dddd (3.74) Applying Laplace transformation on (3.74), the open-loop transfer function of the APF s capacitive branch can be expressed as vv dddd (SS) = UU dddd (SS) SSCC dddd (3.75) By multiplying (3.73) and (3.75), the open loop transfer function GG cc (SS) for voltage control loop can be obtained as GG cc (ss) = VV dddd (SS) VV dddd (ss) = UU dddd (SS) vv dddd (SS) vv dddd (ss) UU dddd (SS) = (KK PPPP + KK IIII SS ) SSCC dddd = SSKK PPPP +KK IIII SS 2 CC dddd (3.76) The closed-loop transfer function vv dddd (SS) of Fig. 3.7 can be written as follows vv dddd (SS) vv dddd (SS) vv dddd (SS) = = = GG cc (ss) +GG cc (ss) SSKK PPPP +KK IIII SS 2 CC dddd + SSKK PPPP +KK IIII SS 2 CC dddd SSKK PPPP +KK IIII SS 2 CC dddd +SSKK PPPP +KK IIII = SSKK PPPP +KK IIII CC dddd SS 2 +SS KK PPPP CC dddd + KK IIII CC dddd = SSKK PPPP +KK IIII CC dddd KK IIII CC dddd CC dddd KK IIII SS KK IIII CC dddd CC dddd 2 CC dddd KK PPPP SS+ KK IIII KK IIII CC dddd 58

86 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy = + KK PPPP SS KK IIII KK 2 IIII CC dddd 2 CC dddd SS 2 +2 KK PPPP KK IIII SS+ KK IIII 2 CC dddd KK IIII CC dddd Equation (3.77) is compared with the second order transfer function that yields the following design relations for voltage control loop (3.77) ωω 2 nnnn SS 2 +2ζζωω nnnn SS+ωω 2 nnnn ωω nnnn = KK IIII CC dddd KK IIII = ωω nnnn 2 CC dddd (3.78) KK PPPP ζζ = KK 2 CC dddd KK PPPP = 2ζζωω nnnn CC dddd (3.79) IIII where ωω nnnn is the DC-link voltage regulator frequency. It must be smaller than the three-phase fundamental frequency. A value of ωω nnnn = ωω 5 is adopted in this simulation study. The controller output UU dddd has only d-axis component and its q-axis component is zero. Using (3.7), the control action of the DC-component current can be derived as II = UU dddd dd nnnn ii ffff dd nnnn = uu dddd vv dddd dd nnnn vv dddd ii ffff dd nnnn vv dddd (3.8) However, assuming the current control loops to be ideal and considering the APF operation is under normal condition, the following relations can be expressed as dd nnnn vv dddd = vv dd = 3 2 vv mm (3.8) dd nnnn vv dddd = vv qq = (3.82) Using (3.8) and (3.82), (3.8) can further be simplified as II = uu dddd vv dddd dd nnnn vv dddd ii ffff dd nnnn vv dddd = uu dddd vv dddd vv dd = 2 3 UU dddd vv dddd vv mm (3.83) The reference current obtained from (3.83) is added to the harmonic reference current of the d-axis current loop as shown in Fig. 3.4 to compensate the system loss and regulate vv dddd [67]. 59

87 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy PWM Control System The VSI output voltages vv aa, vv bb and vv cc are produced depending on the switching signals fed to the gate terminals of IGBTs [3, 7]. These output voltages are synchronous with their respective phase voltages by proper control of IGBTs. Its control variables are the modulation index II mm and the power angle δδ. This angle may be defined as the phase angle difference between the respective phase voltages of PCC and VSI output. The magnitude and phase of vv aa, vv bb and vv cc are decided by controlling II mm and δδ, respectively. The block diagram of a carrier-based PWM control system is presented in Fig The computed switching state functions dd nnnn and dd nnnn in the Park s rectangular coordinates can be represented as dd nnnn = II mm cccccc δδ 2 (3.84) dd nnnn = II mm ssssss δδ (3.85) 2 where II mm and δδ are the converter s input variables in Park s polar coordinates. The input variables II mm and δδ of the control circuit can be expressed as II mm = 2(dd nnnn 2 + dd nnnn 2 ) (3.86) δδ = tttttt dd nnnn dd nnnn (3.87) The reference voltages VV rrrrrrrr, VV rrrrrrrr and VV rrrrrrrr of the PWM control system can be expressed as follows VV rrrrrrrr = II mm vv dddd 3 cccccc(ωωtt + δδ) (3.88) vv dddd vv rrrrrrrr dd nnnn dd nnnn vv aa Rect to Polar PLL II mm δδ ωωωω II mm vv dddd xx 3 CCCCCC (xx) II mm vv dddd 3 2ππ 3 vv rrrrrrrr ss aa ss aa ss bb ss bb 4ππ 3 vv rrrrrrrr ss cc ss cc Gating signal Fig. 3.8: Block diagram of PWM control system. Triangular carrier 6

88 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy VV rrrrrrrr = II mm vv dddd cccccc ωωtt + δδ 2ππ (3.89) 3 3 VV rrrrrrrr = II mm VV dddd cccccc ωωtt + δδ 4ππ (3.9) 3 3 The reference voltages are compared with the high-frequency triangular carrier waves to generate the switching signals for IGBTs. 3.4 Simulation results To verify the efficacy of the proposed nonlinear control strategy, simulations are carried out via MATLAB/Simulink under various transient scenarios. The system parameters chosen for simulation study are described in Table 3.. The overall filtering performance of APF is analysed under following test cases. The load considered in test case- is a voltage-source type balanced nonlinear load; whereas other test cases are studied by considering current-source type balanced or unbalanced nonlinear load. Table 3.: List of parameters used in simulation tests System quantities Parameters Symbol Values Supply voltages (line to neutral) VV ss 23 V Source Load VSI Current control loop Voltage control loop System frequency ωω ππ rad/s Supply inductors LL ss.5 mh Supply resistors RR ss. Ω Three-phase current-source type of nonlinear load RR LL, LL LL 22 Ω, 2 mh Single-phase current-source type of nonlinear load RR LL2, LL LL2 22 Ω, 2 mh Three-phase voltage-source type of nonlinear load RR LL, CC LL 22 Ω, μf AC line inductors LL ff 3 mh AC line resistors RR ff. Ω DC-link capacitor CC dddd 34 μf DC-link capacitor voltage VV rrrrrr 66 V Switching frequency ωω ss 25ππ rad/s Natural un-damped frequencies ωω nnnn = ωω nnnn = ωω ss 5 5ππ rad/s Proportional gains KK PPPP = KK PPPP Ω - Integral gains KK IIII = KK IIII Ω - s - Cutoff frequency of pre-filters ωω KKKK = ωω KKKK 23.9 rad/s DC-link voltage regulator frequency ωω nnnn = ωω 5 2ππ rad/s Proportional gain KK PPPP.3 Ω - Integral gain KK IIII 3.42 Ω - s - 6

89 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy 3.4. Steady-state performance of APF in a system connected to voltage-source type nonlinear load The steady-state waveform of a system for harmonic elimination employing shunt APF with the proposed nonlinear control technique is shown in Figs. 3.9(a)-(i). In this figure, top-to-bottom waveforms represent the source voltage vv aa, load current ii LLLL, source current ii ssss, injected filter current ii ffff, inverter output voltage vv aa, DC-link capacitor voltage vv dddd, charging current II, d-axis source voltage vv dd and q-axis source voltage vv qq. It is observed that vv aa and ii ssss waveforms are almost sinusoidal and in same Va (Volt) (a) ila (Amp) isa (Amp) (b) (c) Ifa (Amp) Va' (Volt) Vdc (Volt) Io (Amp) (d) (e) (f) (g) Fig. 3.9: Harmonic compensation of a voltage-source type nonlinear load under steady-state condition. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II. 62

90 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Vd (Volt) Vq (Volt) (h) (i) Fig. 3.9: Continued. (h) d-axis source voltage vv dd. (i) q-axis source voltage vv qq. iq* (Amp) ifq (Amp) id* (Amp) ifd (Amp) (a) (b) (c) (d) Fig. 3.: Steady-state tracking performance of current control loop. (a) d-axis APF current ii ffff. (b) d- axis refence current ii dd. (c) q-axis APF current ii ffff. (d) q-axis reference current ii qq. phase. The voltage control loop maintained a constant voltage across the DC-link capacitor with an average value of 66 V. The steady-state maximum and minimum values of vv dddd are 66.5 V and V, respectively. The magnitude of II tends to zero, which indicates that PI controller is well regulated and the losses occurred in the APF s resistive-inductive branches are perfectly compensated. The THD of vv aa is calculated as 4.78%, thus after transformation, the waveforms of vv dd and vv qq are slightly oscillating in the range of 27 V to 29 V and 2 V to 2 V, respectively, which are shown in Fig. 3.9(h) and (i). The actual d- and q-axis APF currents ii ffff, ii ffff in steady-state operation are compared with their respective reference currents ii dd, ii qq as shown in Figs. 3.(a)- 63

91 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy PL (Watt) Ps (Watt) QL (Var) Qs (Var) Magnitude Magnitude (a) (b) (c) (d) (e) (f) Fig. 3.: Simulated waveforms of APF under steady-state with voltage-source type nonlinear load condition. (a) Instantaneous active power PP LL on load side. (b) Instantaneous active power PP SS on source side. (c) Instantaneous reactive power QQ LL on load side. (d) Instantaneous reactive power QQ SS on source side. (e) Power factor on load side. (f) Power factor on source side. (d). From these waveforms, it is noted that the APF generates oscillating current harmonics to track their respective reference templates with high accuracy. There is no time delay appeared between the reference currents and sensed transformed currents. Figs. 3.(a)-(f) demonstrate the characteristics of instantaneous active power PP, reactive power QQ and power factors on load and source. From figures, it is noticed that the waveforms of PP LL, QQ LL and load power factor are highly fluctuating. The presence of harmonic components in the load currents makes these waveforms oscillatory in nature. These parameters are oscillating in the range of (35 W to 86 W), ( 5 Var to 44 Var) and (.8 to ), respectively. On the other hand, with the application of shunt APF, oscillations of PP ss and QQ ss are almost negligible. Furthermore, the source power factor approaches towards unity because of effective compensation. The values 64

92 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Harmonic order Fig. 3.2: Harmonic spectra of a voltage-source type nonlinear load. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. of PP ss, QQ ss and source power factor under this test case are maintained around 6 W, 5 Var and.96 respectively. Fundamental (5Hz) = 228, THD= 4.78% Harmonic order Fundamental (5Hz) = 8.39, THD= 38.38% Fundamental (5Hz) = 8.46, THD= 5.76% Harmonic order The harmonic distortions of source voltage vv aa, load current ii LLLL and source current ii ssss with proposed compensation strategy are illustrated in Figs. 3.2(a)-(c) respectively. The corresponding total harmonic distortion (THD) values of vv aa, ii LLLL and ii ssss are found to be 4.78%, 38.38% and 5.76%. It is evident that the APF adequately suppress the harmonics and maintains a sinusoidal supply current under this situation. (a) (b) (c) Dynamic performance of APF in a system connected to current-source type nonlinear load Fig. 3.3 shows the waveforms of source voltage vv aa, load current ii LLLL, source current ii ssss, APF current ii ffff, inverter voltage vv aa, DC-link capacitor voltage vv dddd and charging current II. In this test case, the APF is in operation after tt.4 s. It is evident from these figures that there is no harmonic compensation till tt =.4 s because APF is in off state. During this off-period, ii ffff is zero and ii ssss is same as ii LLLL. After tt =.4 s, the APF 65

93 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Va (Volt) ila (Amp) isa (Amp) ifa (Amp) Va' (Volt) Vdc (Volt) Io (Amp) (a) (b) (c) (d) (e) (f) (g) Fig. 3.3: Response of APF under the start operation, i.e. APF is switched on at tt =.4 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II. is switched on, by which the compensation process begins. The system demands approximately 4 ms to catch the steady-state value. With this time delay, the APF maintains ii ssss almost sinusoidal and in phase with vv aa. The steady-state maximum and minimum values of vv dddd are 66.5 V and V, respectively. Figs. 3.4(a)-(f) show the waveforms of instantaneous active power PP, reactive power QQ and power factor on the load and source side. It is evident from these figures that during s tt.4 s, the magnitudes of PP ss, QQ ss and source power factor are extremely oscillating in the range of (5 W to 69 W), ( 75 Var to 67 Var) 66

94 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy PL (Watt) Ps (Watt) QL (Var) Qs (Var) Magnitude Magnitude (a) (b) (c) (d) (e) (f) Fig. 3.4: Simulated waveforms under transient state, i.e. APF startup. (a) Instantaneous active power PP LL on load side. (b) Instantaneous active power PP SS on source side. (c) Instantaneous reactive power QQ LL on load side. (d) Instantaneous reactive power QQ SS on source side. (e) Power factor on load side. (f) Power factor on source side. and (.82 to ), respectively. However, the APF takes 5 ms after the instant of switching on to catch the nominal values 6 W, Var and.97 of these parameters respectively. Figs. 3.5(a) and (b) show the corresponding harmonic spectra of load current ii LLLL and source current ii ssss. The THD of ii LLLL and ii ssss are computed as 25.27% and 5.4%, respectively. It is seen that the shunt APF with proposed control technique effectively eliminates the current harmonics and maintains a sinusoidal source current. 67

95 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Mag (% of Fundamental) Mag (% of Fundamental) Harmonic order Fundamental (5Hz) = 8.27, THD= 25.27% Fundamental (5Hz) = 8.23, THD= 5.4% Harmonic order Fig. 3.5: Harmonic spectra of a current-source type nonlinear load. (a) Load current ii LLLL. (b) Source current ii ssss. (a) (b) Response of APF to current-source type nonlinear load variation In this case, the dynamic performance of a system is investigated under the variation of current-source type nonlinear load employing shunt APF with the proposed controller. Figs. 3.6(a)-(m) show the dynamic performance under the temporary load change at tt =.4 s. Due to this load change, the peak value of load current is almost double and maintains the same value till tt =.5 s. It is observed that the source current ii ssss follows the change of load current ii LLLL, and the DC-link capacitor voltage vv dddd fluctuates during this transition. However, both ii ssss and vv dddd exhibit fast transient response and stable operation. When ii LLLL is increased (decreased), vv dddd decreases (increases), to compensate the real power supplied by the source. vv dddd has an undershoot voltage of 65 V (i.e..36%) and overshoot voltage of 669 V (i.e..36%) following a step increase and decrease of load current. During.4 s tt <.5 s, the magnitude of active power PP and reactive power QQ increases with the increase in load current. But the system power factor remains unchanged. As seen in Fig 3.6(m), a unity power factor is maintained on the source side during the system operation. The dynamic performance of the system employing shunt APF with nonlinear control strategy found to be satisfactory and the steady-state condition is achieved within two fundamental cycles (i.e. 4 ms). 68

96 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy PL (Watt) Va (Volt) ila (Amp) isa (Amp) ifa (Amp) Va' (Volt) Ps (Watt) QL (var) Vdc (Volt) Io (Amp) (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) Fig. 3.6: Dynamic performance of APF for harmonic compensation with a current-source type nonlinear load variation during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II. (h) Instantaneous active power PP LL on load side. (i) Instantaneous active power PP SS on source side. (j) Instantaneous reactive power QQ LL on load side. 69

97 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Qs (Var) Magnitude Magnitude (k) (l) (m) Fig. 3.6: Continued. (k) Instantaneous reactive power QQ SS on source side. (l) Power factor on load side. (m) Power factor on source side Response of APF under temporary disconnection of current-source type nonlinear load In this test case, the dynamic performance of the system employing APF is evaluated under on- and off-load switching condition as shown in Figs. 3.7(a)-(m). The load current is decreased from its nominal value of % to % at tt =.4 s and then it is back to the full load current at tt =.5 s. During no-load condition (i.e..4 s tt.5 s, load current ii LLLL is zero. It is evident from these figures that the voltage vv dddd across DC-link capacitor is well regulated and reaches the reference value within 4 ms from the instant of ON/OFF load. vv dddd has an overshoot voltage of 67 V (i.e..5%) at the sudden removal of load and an undershoot voltage of 54 V (i.e. 8.8%) with the reapplication of the same load. Under the off-load condition, the source and load power factors exhibit some errors due to the small current flows from APF to PCC or vice versa. After the re-application of the same load at tt.5 s, the source current, active power and reactive power achieve the steady-state value within two fundamental cycles. The load change does not produce any other undesirable response (i.e. unstable operation), thus shunt APF with nonlinear control strategy manages this transient situation smoothly. 7

98 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Va (Volt) (a) ila (Amp) isa (Amp) (b) (c) PL (Watt) Ps (Watt) QL (Var) ifa (Amp) Va' (Volt) Vdc (Volt) Io (Amp) (d) (e) (f) (g) (h) (i) (j) Fig. 3.7: Dynamic performance of APF for harmonic compensation with a temporarily disconnected current-source type of nonlinear load during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) Charging current II. (h) Instantaneous active power PP LL on load side. (i) Instantaneous active power PP SS on source side. (j) Instantaneous reactive power QQ LL on load side. 7

99 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Qs (Var) Magnitude Magnitude (k) (l) (m) Fig. 3.7: Continued. (k) Instantaneous reactive power QQ SS on source side. (l) Power factor on load side. (m) Power factor on source side Steady-state performance of APF: unbalanced source voltages and balanced nonlinear load In this test case, the unbalanced three-phase supply voltages are expressed as follows vv ssss = 22 cccccc(ωωωω) (3.9) vv ssss = 23 cccccc(ωωωω 2ππ ) 3 (3.92) vv ssss = 24 cccccc(ωωtt 4ππ ) (3.93) 3 This type of supply also introduces a non uniform current flow among three phases. Figs. 3.8(a)-(t) illustrate the waveforms of unbalanced source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), source currents (ii ssss, ii ssss, ii ssss ), APF currents ii ffff, ii ffff, ii ffff, DC-link capacitor voltage (vv dddd ), charging current (II ), active powers (PP LL, PP SS ), reactive powers (QQ LL, QQ SS ), and power factors. It is evident from these figures that the load currents became unbalanced due to the unbalanced mains. The shunt APF takes care this unbalanced situation and monitors fully balanced sinusoidal source currents. The ripple content in vv dddd is very small (i.e. from. V to.3 V). The PI controller used in voltage control loop carefully regulates the charging current II. On the source side, the oscillation of the active power is reduced and the reactive power is compensated effectively by APF with a current control loop so that the power factor is around unity. 72

100 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Vc (volt) Vb (volt) Va (Volt) (a) (b) (c) ifa (Amp) isc (Amp) isb (Amp) isa (Amp) ilc (Amp) ilb (Amp) ila (Amp) (d) (e) (f) (g) (h) (i) (j) Fig. 3.8: Harmonic compensation of unbalanced source voltages under steady-state condition. (a)-(c) Three-phase source voltage vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (j) APF current in phase-a ii ffff. 73

101 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy ifb (Amp) (k) PL (Watt) Ps (Watt) QL (Var) Qs (Amp) ifc (Amp) Vdc (Amp) Io (Amp) Magnitude Magnitude (l) (m) (n) (o) (p) (q) (r) (s) (t) Fig. 3.8: Continued. (k) APF currents in phase-b ii ffff. (l) APF currents in phase-c ii ffff. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side. 74

102 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Figs. 3.9(a)-(i) demonstrate the harmonic spectra of source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), and source currents (ii ssss, ii ssss, ii ssss ). The peak values of fundamental voltages measured at PCC are 28 V, V and V respectively, and corresponding THD are 5.%, 4.79% and 4.6%. The amplitudes of fundamental components of ii LLLL, ii LLLL and ii LLLL are 7.88 A, 8.28 A and 8.64 A respectively, and their subsequent THD values are 26.33%, 25.24% and 24.3%. Further, the THD of ii ssss, ii ssss and ii ssss are reduced to 5.35%, 5.2% and 5.36% respectively and their corresponding fundamental peaks are 9.36 A, 9.37 A and 9.39 A, which indicate the balanced characteristics of the source currents. Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 28, THD= 5.% Harmonic order Fundamental (5Hz) = 227.9, THD= 4.79% Harmonic order (a) (b) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 237.9, THD= 4.6% Harmonic order Fundamental (5Hz) = 7.88, THD= 26.33% Harmonic order Fig. 3.9: Harmonic spectra under unbalanced power supply and balanced nonlinear load. (a)-(c) Threephase source voltages vv aa, vv bb, vv cc, respectively. (d) Load current in phase-a ii LLLL. (c) (d) 75

103 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 8.28, THD= 25.24% Harmonic order Fundamental (5Hz) = 8.64, THD= 24.3% Harmonic order Fundamental (5Hz) = 9.36, THD= 5.35% Harmonic order Fundamental (5Hz) = 9.37, THD= 5.2% Harmonic order (e) (f) (g) (h) Mag (% of Fundamental) Fundamental (5Hz) = 9.39, THD= 5.36% Harmonic order Fig. 3.9: Continued. (e) Load current in phase-b ii LLLL. (f) Load current in phase-c ii LLLL. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (i) Steady-state performance of APF: distorted source voltages and balanced nonlinear load The unbalanced and distorted three-phase supply voltages are considered as vv ssss = 23 cccccc(ωωωω) + 4 cccccc(3ωωωω + 3 ) + 7 cccccc(7ωωωω + ) (3.94) 76

104 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Vc (Volt) Vb (Volt) Va (Volt) (a) (b) (c) ifa (Amp) isc (Amp) isb (Amp) isa (Amp) ilc (Amp) ilb (Amp) ila (Amp) (d) (e) (f) (g) (h) (i) (j) Fig. 3.2: Harmonic compensation of distorted source voltages under steady-state condition. (a)-(c) Three-phase source voltage vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (j) APF current in phase-a ii ffff. 77

105 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy ifb (Amp) (k) PL (Watt) Ps (Watt) QL (Var) Qs (Var) ifc (Amp) Vdc (Volt) Io (Amp) Magnitude Magnitude (l) (m) (n) (o) (p) (q) (r) (s) (t) Fig. 3.2: Continued. (k) APF currents in phase-b ii ffff. (l) APF currents in phase-c ii ffff. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side. 78

106 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy vv ssss = 23 cccccc(ωωωω 2ππ 3 ) + 5 cccccc(5ωωωω + 7 ) + 3 cccccc(ωωωω + 5 ) (3.95) vv ssss = 23 cccccc(ωωtt 4ππ ) cccccc(7ωωωω ) cccccc(9ωωωω + 67 ) (3.96) These voltages are applied to the current-source type nonlinear load. Now the harmonics present in the load currents are utility-generated as well as customergenerated harmonic components. Figs. 3.2(a)-(t) depict the waveforms of source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), source currents (ii ssss, ii ssss, ii ssss ), APF currents ii ffff, ii ffff, ii ffff, DC-link capacitor voltage (vv dddd ), charging current (II ), active powers (PP LL, PP SS ), reactive powers (QQ LL, QQ SS ), and power factors. The waveforms of source currents are sinusoidal and in phase with their respective fundamental phase voltages. The proposed compensation strategy performs effectively under such type of critical condition. The ripples in vv dddd are very small. The source reactive power is compensated with a minor oscillation, thus the measured power factor approaches unity. It is concluded that the shunt APF takes care only current harmonics, not voltage harmonics. Thus, for voltage related power quality issues, researchers are preferred series APF. Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 227.9, THD= 8.39% Harmonic order Fundamental (5Hz) = 227.9, THD= 8.9% Harmonic order (a) (b) Mag (% of Fundamental) Fundamental (5Hz) = 227.9, THD= 7.84% Harmonic order Fig. 3.2: Harmonic spectra under distorted power supply and balanced nonlinear load. (a)-(c) Threephase source voltages vv aa, vv bb, vv cc, respectively. 79 (c)

107 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 7.82, THD= 27.23% Harmonic order Fundamental (5Hz) = 8.3, THD= 25.4% Harmonic order Fundamental (5Hz) = 8.3, THD= 25.4% Harmonic order (d) (e) (f) Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 9.34, THD= 5.5% Harmonic order Fundamental (5Hz) = 9.26, THD= 5.4% Harmonic order Fundamental (5Hz) = 9.34, THD= 5.44% Harmonic order Fig. 3.2: Continued. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (g) (h) (i) 8

108 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Figs. 3.2(a)-(i) exhibit the harmonic spectra of source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), and source currents (ii ssss, ii ssss, ii ssss ) from top-to-bottom proportionately. Due to the utility-generated harmonics, the THD of PCC voltages vv aa, vv bb and vv cc are increased to 8.39%, 8.9% and 7.84% for phase-a, b and c, respectively. Similarly, because of utility-generated and customer generated harmonics, the THD of ii LLLL, ii LLLL and ii LLLL are increased to 27.23%, 25.4% and 25.4% respectively. By employing APF compensation strategy, the corresponding THD values of ii ssss, ii ssss and ii ssss reduces to 5.5%, 5.4% and 5.44% Steady-state performance of APF: balanced source voltages and unbalanced nonlinear loads In this test case, the unbalanced nonlinear load is a combination of three-phase diode bridge rectifier with an inductive load (RR LL, LL LL ) and single-phase diode bridge rectifier feeding another inductive load (RR LL2, LL LL2 ) as shown in Fig. 3.. The single-phase nonlinear load is connected between phase-b and c to make the load current unbalanced. The waveforms of source voltage (vv aa ), load currents (ii LLLL, ii LLLL, ii LLLL ), source currents (ii ssss, ii ssss, ii ssss ), APF currents ii ffff, ii ffff, ii ffff, DC-link capacitor voltage (vv dddd ) charging current (II ), active powers (PP LL, PP SS ), reactive powers (QQ LL, QQ SS ), and power factors are shown in Figs. 3.22(a)-(r), respectively. It is seen that the load currents in phase-b and c are equally distributed due to the homogeneous loading action, but phase-a load current ii LLLL totally diverges. Due to the effective compensation, the waveforms of supply current exhibit sinusoidal and balanced. By analysing the waveforms, it can be concluded that the APF system not only compensates harmonic and reactive components but also make the power system operate in balanced mode. The voltage across DC-link capacitor is well regulated with a minor deviation of ±2 V. The losses occurred in APF s resistive-inductive branches are perfectly compensated by monitoring the magnitude of charging current II. The waveforms of PP LL, QQ LL and load power factor are highly oscillating in the range between (475 W to 32 W), ( 3 Var to 74 Var) and (.67 to ) respectively. Using shunt APF with compensation strategy, oscillation of PP ss is effectively damped in the range of (775 W to 65 W) and QQ ss is compensated in the range of ( Var to 36 Var) such that the power factor lies within a range of (.93 to.99). 8

109 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Va (Volt) ila (Amp) ilb (Amp) ilc (Amp) isa (Amp) isb (Amp) isc (Amp) ifa (Amp) ifb (Amp) ifc (Amp) (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) Fig. 3.22: Harmonic compensation of unbalanced nonlinear loads under steady-state condition. (a) Source voltage vv aa. (b)-(d) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (e)-(g) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (h)-(j) Three-phase APF currents ii ffff, ii ffff, ii ffff, respectively. 82

110 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy PL (Watt) Ps (Watt) QL (Var) Qs (Var) Vdc (Volt) Io (Amp) Magnitude Magnitude (k) (l) (m) (n) (o) (p) (q) (r) Fig. 3.22: Continued. (k) DC-link capacitor voltage vv dddd. (l) Charging current II. (m) Instantaneous active power PP LL on load side. (n) Instantaneous active power PP SS on source side. (o) Instantaneous reactive power QQ LL on load side. (p) Instantaneous reactive power QQ SS on source side. (q) Power factor on load side. (r) Power factor on source side. Figs. 3.23(a)-(g) show the harmonic spectra of source voltage (vv aa ), load currents (ii LLLL, ii LLLL, ii LLLL ), and source currents (ii ssss, ii ssss, ii ssss ) from top-to-bottom respectively. In this simulation study, the three-phase supply is balanced and the THD of source voltage in all phases are almost equal to 4.78%. Furthermore, the fundamental peak values of ii LLLL, ii LLLL and ii LLLL are 8.8 A, A and A 83

111 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy respectively, and their corresponding THDs are 24.84%, 3.52% and 4.4%. Because of compensation based on APF system, the supply currents are forced to balance. The THDs of ii ssss, ii ssss and ii ssss are 3.92%, 3.78% and 4.29% respectively, and their subsequent peak values are A, 3.7 A and 27.4 A, which shows the validity of the proposed current control loop under unbalanced load condition. Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 226.9, THD= 4.78% Harmonic order Fundamental (5Hz) = 8.8, THD= 24.84% Harmonic order (a) (b) Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 33.99, THD= 3.52% Harmonic order Fundamental (5Hz) = 32.62, THD= 4.4% Harmonic order Fundamental (5Hz) = 28.74, THD= 3.92% Harmonic order Fig. 3.23: Harmonic spectra under balanced power supply and unbalanced load condition. (a) Source voltage vv aa. (b)-(d) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (e) Source current in phase-a ii ssss. 84 (c) (d) (e)

112 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Mag (% of Fundamental) Mag (% of Fundamental) Harmonic order Fundamental (5Hz) = 3.7, THD= 3.76% Fundamental (5Hz) = 27.4, THD= 4.29% Harmonic order Fig. 3.23: Continued. (f) Source current in phase-b ii ssss. (g) Source current in phase-c ii ssss. (f) (g) Steady-state performance of APF: unbalanced source voltages and unbalanced nonlinear loads In this test case, the performance of proposed controller in a system with unbalanced three-phase mains as expressed in (3.9)-(3.93) connected to unbalanced nonlinear loads. Figs. 3.24(a)-(t) from top-to-bottom waveforms depict source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), source currents (ii ssss, ii ssss, ii ssss ), APF currents ii ffff, ii ffff, ii ffff, DC-link capacitor voltage (vv dddd ), charging current (II ), active powers (PP LL, PP SS ), reactive powers (QQ LL, QQ SS ), and power factors. In this mode, both supply voltages and load currents are highly unbalanced in nature. The APF carefully monitors this situation and produces compensating currents such that the system turns into balanced. As seen in Figs. 3.24(g)-(i), the three-phase source currents are completely balanced and sinusoidal using the nonlinear control strategy. vv dddd is also well regulated at 66 V under this loading condition. The unstable active power, reactive power and power factor on the load side are in the range of (455 W to 3666 W), ( 34 Var to 75 Var) and (.665 to ), respectively. However, with the help of APF based compensation, the magnitudes of source side active power, reactive power and power factor are maintained in the range of (78 W to 8 W), (5 Var to 38 Var) and (.92 to.998), respectively. 85

113 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Va (Volt) Vb (Volt) Vc (Volt) ila (Amp) ilb (Amp) ilc (Amp) isa (Amp) isb (Amp) isc (Amp) ifa (Amp) (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) Fig. 3.24: Harmonic compensation of unbalanced supply voltages and unbalanced nonlinear loads under steady-state condition. (a)-(c) Three-phase source voltage vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (j) APF current in phase-a ii ffff. 86

114 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy PL (Watt) Ps (Watt) QL (Var) Qs (Var) ifb (Amp) ifc (Amp) Vdc (Volt) Io (Amp) Magnitude Magnitude (k) (l) (m) (n) (o) (p) (q) (r) (s) (t) Fig. 3.24: Continued. (k) APF currents in phase-b ii ffff. (l) APF currents in phase-c ii ffff. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side. 87

115 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Figs. 3.25(a)-(i) depict the harmonic spectra of source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), and source currents (ii ssss, ii ssss, ii ssss ), respectively. In these figures, the THD of ii LLLL, ii LLLL and ii LLLL are obtained as 25.9%, 3.36% and 3.85%, respectively, and their corresponding fundamental peaks are 7.78 A, A and A. However, the THD of ii ssss, ii ssss and ii ssss are reduced to 3.97%, 3.73% and 2.29%, respectively, and their subsequent fundamental peak values are maintained at 29.9 A, 3.68 A and A because of effective compensation. It is observed that the source currents are almost balanced though the supply voltages and load currents are unbalanced in nature, thus the performance of the system is not degraded. Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 26.9, THD= 5.% Harmonic order Fundamental (5Hz) = 226.7, THD= 4.77% Harmonic order Fundamental (5Hz) = 237, THD= 4.57% Harmonic order Fundamental (5Hz) = 7.78, THD= 25.9% Harmonic order (a) (b) (c) (d) Fig. 3.25: Harmonic spectra under unbalanced power supply and unbalanced loads. (a)-(c) Three-phase source voltages vv aa, vv bb, vv cc, respectively. (d) Load current in phase-a ii LLLL. 88

116 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 34.39, THD= 3.36% Harmonic order Fundamental (5Hz) = 33.47, THD= 3.85% Harmonic order Fundamental (5Hz) = 29.9, THD= 3.97% Harmonic order Fundamental (5Hz) = 3.68, THD= 3.73% Harmonic order (e) (f) (g) (h) Mag (% of Fundamental) Fundamental (5Hz) = 27.74, THD= 4.29% Harmonic order Fig. 3.25: Continued. (e) Load current in phase-b ii LLLL. (f) Load current in phase-c ii LLLL. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. (i) Steady-state performance of APF: distorted source voltages and unbalanced nonlinear loads In this scenario, the three-phase power supply is assumed to be unbalanced and distorted as expressed in (3.94)-(3.96). Further, the load is composed of a three-phase 89

117 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Va (Volt) Vb (Volt) Vc (Volt) ila (Amp) ilb (Amp) ilc (Amp) isa (Amp) isb (Amp) ilc (Amp) ifa (Amp) (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) Fig. 3.26: Harmonic compensation of distorted supply voltages and unbalanced nonlinear loads under steady-state condition. (a)-(c) Three-phase source voltage vv aa, vv bb, vv cc, respectively. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssaa, ii ssss, ii ssss, respectively. (j) APF current in phase-a ii ffff. 9

118 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy PL (Watt) QL (Var) Ps (Watt) Qs (Var) ifb (Amp) ifc (Amp) Vdc (Volt) Io (Amp) Magnitude Magnitude (k) (l) (m) (n) (o) (p) (q) (r) (s) (t) Fig. 3.26: Continued. (k) APF currents in phase-b ii ffff. (l) APF currents in phase-c ii ffff. (m) DC-link capacitor voltage vv dddd. (n) Charging current II. (o) Instantaneous active power PP LL on load side. (p) Instantaneous active power PP SS on source side. (q) Instantaneous reactive power QQ LL on load side. (r) Instantaneous reactive power QQ SS on source side. (s) Power factor on load side. (t) Power factor on source side. 9

119 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy current-source type nonlinear load and a single-phase current-source type nonlinear load to represent as unbalanced nonlinear load condition. Therefore, the obtained load currents contain source- and load-generated harmonics. Under this condition, the simulation results of source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), source currents (ii ssss, ii ssss, ii ssss ), APF currents ii ffff, ii ffff, ii ffff, DC-link capacitor voltage (vv dddd ), charging current (II ), active powers (PP LL, PP SS ), reactive powers (QQ LL, QQ SS ), and power factors are shown in Figs. 3.26(a)-(t) respectively. It is observed from these figures that the APF system employing proposed nonlinear controller maintains the source currents balanced and sinusoidal. The self-charging circuit, i.e. voltage control loop monitors the vv dddd to its reference voltage. The active power, reactive power and power factor on the source side are little oscillating, which are within the acceptable range. Mag (% of Fundamental) Fundamental (5Hz) = 227, THD= 8.43% Harmonic order (a) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 226.7, THD= 8.2% Harmonic order Fundamental (5Hz) = 227, THD= 7.85% Harmonic order Fig. 3.27: Harmonic spectra under distorted power supply and unbalanced nonlinear loads. (a)-(c) Threephase source voltages vv aa, vv bb, vv cc, respectively. (b) (c) 92

120 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 7.78, THD= 26.59% Harmonic order Fundamental (5Hz) = 34.43, THD= 3.3% Harmonic order (d) (e) Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 32.7, THD= 3.8% Harmonic order Fundamental (5Hz) = 28.69, THD= 3.88% Harmonic order Fundamental (5Hz) = 3.4, THD= 3.65% Harmonic order Fundamental (5Hz) = 27.3, THD= 4.2% Harmonic order Fig. 3.27: Continued. (d)-(f) Three-phase load currents ii LLLL, ii LLLL, ii LLLL, respectively. (g)-(i) Three-phase source currents ii ssss, ii ssss, ii ssss, respectively. 93 (f) (g) (h) (i)

121 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Figs. 3.27(a)-(i) indicate the harmonic spectra of source voltages (vv aa, vv bb, vv cc ), load currents (ii LLLL, ii LLLL, ii LLLL ), and compensated source currents (ii ssss, ii ssss, ii ssss ), subsequently. The THD of the unbalanced currents generated by the load is observed to be approximately 26.59%, 3.3% and 3.8% for phase-a, b and c, respectively; and their corresponding fundamental peak values are 7.78 A, A and 32.7 A. After compensation with the shunt APF, the source currents ii ssss, ii ssss and ii ssss have THD of 3.88%, 3.65% and 4.2% respectively, and these are well within the limit of 5% (i.e. recommended by IEEE standard). The analogous source current fundamental peaks are A, 3.4 A and 27.3 A, which are deemed to be equal. This clearly shows that the proposed compensation technique is robust under unbalanced and distorted condition. The overall summary of simulation results under different test cases is presented in Table 3.2. The THDs and fundamental peaks of PCC voltages, load currents and source currents of above described nine test cases are reported in this table to evaluate the effectiveness shunt APF with nonlinear control technique. From simulated results of test cases and 2, it is observed that the voltage-source type nonlinear load introduces more harmonics than the current-source type nonlinear load. However, after compensation, the THDs of source currents in these two cases are approximately equal. Thus the performance of proposed nonlinear compensation strategy is independent on the type of load. It is seen from test case 3 that the THD of source current is lesser than the rated source current due to the increase in load current (i.e. a higher value of fundamental peak). Under test case 4, both load and source currents are zero during no load condition. It is evident from the simulated results of test cases 5 and 6 that the distorted source voltage does not affect the compensating performance of shunt APF. From analysis of test cases 5-9, it is observed that the THD values of load currents in phase-b and c of test cases 7, 8 and 9 are reduced due to the parallel connection of additional nonlinear load in the system. However, the compensated source currents under these test cases are almost balanced and sinusoidal with reduced THD values as compared to test cases 5 and 6. 94

122 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy Table 3.2: Summary of the simulation results Test cases Supply/nonlinear load conditions APF status Items PCC voltages (during.4 s < tt <.5 s) Load currents (during.4 s < tt <.5 s) Source currents (during.4 s < tt <.5 s) Phase-a Phase-b Phase-c Phase-a Phase-b Phase-c Phase-a Phase-b Phase-c Balanced supply, balanced nonlinear RC load (steadystate response of APF) ON at tt = s Fund Peak 228 V 228 V 228 V 8.39 A 8.39 A 8.39 A 8.46 A 8.46 A 8.45 A THD 4.78% 4.75% 4.77% 38.38% 38.38% 38.4% 5.76% 5.7% 5.74% Fund Balanced supply, balanced 228 V 228 V 228 V 8.27 A 8.27 A 8.27 A 8.23 A 8.27 A 8.22 A ON at Peak nonlinear RL load tt =.4 s (dynamic response of APF) THD 4.78% 4.8% 4.77% 25.27% 25.29% 25.27% 5.4% 5.46% 5.38% Balanced supply, balanced nonlinear RL load (during.4 ss tt <.5 ss load current increased to %) Balanced supply, balanced nonlinear RL load (during.4 ss tt <.5 ss load is removed) Unbalanced supply, balanced nonlinear RL load (steady-state response of APF) Unbalanced and distorted supply, balanced nonlinear RL load (steady-state response of APF) Balanced supply, unbalanced nonlinear RL loads (steady-state response of APF) Unbalanced supply, unbalanced nonlinear RL loads (steady-state response of APF) Unbalanced and distorted supply, unbalanced nonlinear RL loads (steadystate response of APF) ON at tt = s ON at tt = s ON at tt = s ON at tt = s ON at tt = s ON at tt = s ON at tt = s Fund Peak V V V A A A A 34.7 A A THD 4.84% 4.82% 4.83% 23.46% 23.46% 23.46% 3.87% 3.83% 3.89% Fund Peak V V V THD 5.3% 5.4% 5.3% Fund Peak 28 V V V 7.88 A 8.28 A 8.64 A 9.36 A 9.37 A 9.39 A THD 5.% 4.79% 4.6% 26.33% 25.24% 24.3% 5.35% 5.2% 5.36% Fund Peak V V V 7.82 A 8.3 A 8.3 A 9.34 A 9.26 A 9.34 A THD 8.39% 8.9% 7.84% 27.23% 25.4% 25.4% 5.5% 5.4% 5.44% Fund Peak V V 227 V 8.8 A A A A 3.7 A 27.4 A THD 4.78% 4.75% 4.78% 24.84% 3.52% 4.4% 3.92% 3.76% 4.29% Fund Peak 26.9 V V 237 V 7.78 A A A 29.9 A 3.68 A A THD 5.% 4.77% 4.57% 25.9% 3.36% 3.85% 3.97% 3.73% 4.29% Fund Peak V V 227 V 7.78 A A 32.7 A A 3.4 A 27.3 A THD 8.43% 8.2% 7.85% 26.59% 3.3% 3.8% 3.88% 3.65% 4.2% 3.5 Chapter summary In this chapter, a nonlinear current control technique for evaluation of reference signals and a new PWM control scheme for generation of switching signals required to operate the shunt APF effectively in a system are presented. The nonlinear control structure is composed of voltage decouplers, rotating frame transformation, high-pass filtering and pole-zero cancellation. The shunt APF utilizing this compensation strategy reduces the 95

123 Chapter 3: Power quality enhancement using shunt APF with nonlinear control strategy THD of the source current significantly, and enables the power system to operate under various transient scenarios without deteriorating the power quality. The shunt APF adapts to different demanding scenarios and makes the system stable. In addition, it maintains power factor around unity by controlling the reactive power. It is observed from preceding section that the shunt APF employed with the proposed nonlinear control scheme is dynamic and cost-effective solution for solving harmonic related issues in the distribution power system network. 96

124 Chapter 4 Power Quality Improvement Using ADALINE-VLLMS Based HPF System 4. Introduction The substantial increase in the use of power electronic devices in domestic, commercial, and industrial environments produces harmonics that degrade power quality of the system. The increased severity of harmonic pollution and reactive power burden in a distribution network causes low system efficiency and poor power factor. These power quality issues became significant in a system connected to nonlinear loads. Thus research attention is made to develop an effective filtering solution. An HPF topology along with ADALINE-VLLMS detection algorithm is suggested in this chapter to achieve excellent compensation performance. The HPF is formed by connecting an APF in series with a PPF. The PPF absorbs the harmonic currents injected by the nonlinear loads and suppresses the switching ripples generated from the APF [85, 96-, 3]. The APF eliminates harmonic components and improves the filtering performance of the PPF under both transient and steady-state. This type of configuration significantly reduces the rating of the APF as compared to that of a 97

125 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF conventional standalone APF as presented in chapter-3. This topology avoids the use of transformers, reactors and switching-ripple filters. For the operation of HPF in the system, ADALINE-VLLMS based detection technique is employed. An ADALINE based time-domain approach is used to extract the harmonic and reactive power components from the sensed load current [24-39]. In general, weights of ADALINE are updated by the conventional LMS algorithm because of its simplicity and ease of implementation. However, the convergence and stability of the LMS algorithm can be problematic under non-ideal situations such as insufficient spectral excitation, finite precision effect and stalling phenomenon [43]. In these cases, the ADALINE weights may drift away from their optimum values and thus don t converge. To overcome these limitations, a time-varying leakage factor is introduced in the weight updating equation of the LMS algorithm. The variable leakage factor improves the tracking capability, enhances the convergence rate and stabilizes the system [, 44-46, 3]. Extensive simulations are conducted to validate the efficacy of the proposed ADALINE-VLLMS control algorithm for an effective operation of HPF. Finally, the results are verified by implementing the proposed control algorithm in a real-time prototype using a SPARTAN-3A DSP processor. 4.2 System configuration with control structure Fig. 4.(a) shows the circuit configuration of HPF topology. A three-phase source with line impedance comprising of an inductance LL ss and a resistance RR ss feeds power to a nonlinear load. The nonlinear load is constituted by a diode bridge rectifier with a parallel combination of a ripple capacitor CC rr and an inductive load (i.e. series combination of RR LL and LL LL ). The smoothing inductors of each value LL ssss are installed at the AC side of the rectifier that plays an important role in the stable operation of APF. A low-rated APF is connected in series with a high-rated 7 tth tuned PPF to form an HPF configuration suited for the system. In this study, APF is considered as a threephase VSI having six IGBTs ( ss aa, ss aa, ss bb, ss bb, ss cc and ss cc ) and a DC-link capacitor CC dddd. The HPF is connected in parallel with the load without using a coupling transformer. To reduce the size and cost of the HPF, high-rated passive filters are preferred instead of using a combinational low-rated passive filter with coupling transformer. Furthermore, the advantages of selecting the 7 tth tuned PPF are as follows [56]. 98

126 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF vv ssss LL ss RR ss ii ssss PCC ii LLLL LL ssss LL LL vv ssss ii ssss ii LLLL CC rr RR LL vv ssss ii ssss ii LLLL Grid Ground vv aa vv bb vv cc LL PP RR PP PPF Nonlinear Load ss cc ss bb ss aa vv aa vv bb vv cc CC PP ii ffff ii ffff CC dddd ii ffff Active Power Filter (a) ss cc ss bb ss aa VV dddd PI II vv aa ii LLLL II ADALINE- VLLMS [Fig. 4.2] ii rrrrrrrr ii rrrrrrrr R vv rrrrrrrr gg aa gg aa VV rrrrrr vv bb ii LLLL II ADALINE- VLLMS ii rrrrrrrr ii rrrrrrrr R vv rrrrrrrr gg bb gg bb vv cc ii LLLL II ADALINE- VLLMS ii rrrrrrrr ii rrrrrrrr R V dc 2 vv rrrrrrrr gg cc Gating signal gg cc +V dc 2 Triangular carrier DC-link Voltage Control Loop Current Control Loops PWM Control Loops (b) Fig. 4.: Main circuit configuration and control block diagrams. (a) Structure of three-phase HPF topology. (b) A DC-link voltage control loop, current control loops and PWM control loops. The 7 tth tuned PPF provides a lower impedance path for tth and 3 tth harmonic frequencies than a 5 tth tuned PPF, thus provides better filtering performance. The designing of 5 tth tuned PPF is heavy, bulky and expensive as compared to 7 tth tuned PPF due to its larger capacitance value CC pp. The control block diagram for HPF operation is shown in Fig. 4.(b). It is composed of three loops such as current control loop, DC-link voltage control loop and PWM control loop. The proposed ADALINE-VLLMS control scheme is designed to detect harmonics and reactive power components from the sensed load currents (ii LLLL, ii LLLL, ii LLLL ), and these signals are fed to the PWM controller to produce switching signals for VSI. A PI controller is employed to charge the DC-link capacitor to the desired voltage level. 99

127 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF The HPF injects filter currents (ii. ee. ii ffff, ii ffff, ii ffff ), which are equal in magnitude and opposite phase of the extracted components. Therefore, the source currents (ii ssss, ii ssss, ii ssss ) become almost sinusoidal. The three-phase source voltages measured at PCC and output voltages of VSI are denoted as (vv aa, vv bb, vv cc ) and (vv aa, vv bb, vv cc ) respectively. 4.3 Harmonic detection technique Assuming three-phase source voltages are of pure sinusoidal and balanced, phase voltages can be expressed as vv aa (tt) = VV mm ssssss(ωωωω) (4.) vv bb (tt) = VV mm ssssss(ωωωω + 2ππ 3) (4.2) vv cc (tt) = VV mm ssssss(ωωωω 2ππ 3) (4.3) where VV mm and ωω are the maximum phase voltage and angular frequency respectively. The instantaneous phase-a current drawn by nonlinear load can be decomposed into Fourier series as ii LLLL (tt) = qq= AA qq ssssss ωω qq tt + ΦΦ qq = AA ssssss(ωωωω + ΦΦ ) + qq=2 AA qq ssssss ωω qq tt + ΦΦ qq = ii xxxx (tt) + ii haa (tt) (4.4) where ωω qq, AA qq and ΦΦ qq denote the angular frequency, peak amplitude and phase angle of the qq tth order harmonic component of the load current respectively. The currents ii xxxx (tt) and ii haa (tt) represent the fundamental and total harmonic components of the load current respectively. ii xxxx (tt) can further be modified as ii xxxx (tt) = AA cccccc ΦΦ ssssss ωωωω + AA ssssss ΦΦ cccccc ωωωω = ii aaaa (tt) + ii rrrr (tt) (4.5) where ii aaaa (tt) and ii rrrr (tt) are the active and reactive components of the fundamental load current respectively. Combining (4.4) and (4.5) yields the following expression ii LLLL (tt) = ii aaaa (tt) + ii rrrr (tt) + ii haa (tt) (4.6) Using (4.6), the current references can be calculated based on two cases as follows.

128 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Case-: If the APF monitors harmonic components only [28-34, 37, 38], then load current becomes ii LLLL (tt) = ii uuuu (tt) + ii ffff (tt) (4.7) where ii uuuu (tt) = ii aaaa (tt) + ii rrrr (tt) and ii ffff (tt) = ii haa (tt) are useful current and compensating current components respectively. Then ii ffff (tt) can be expressed as ii ffff (tt) = ii LLLL (tt) ii uuuu (tt) = ii LLLL (tt) [AA cccccc ΦΦ AA ssssss ΦΦ ssssss ωωωω ] (4.8) cccccc ωωωω where AA cccccc ΦΦ and AA ssssss ΦΦ are the unknown values that need to be estimated. The known values, i.e., unity magnitude sinusoidal components ssssss ωωωω and cccccc ωωωω are generated from the phase-a source voltage. Case-2: If the APF compensates both harmonic and reactive power components simultaneously [24, 25, 35], then ii uuuu (tt) = ii aaaa (tt) and ii ffff (tt) = ii rrrr (tt) + ii haa (tt). The current ii ffff (tt) can be written as ii ffff (tt) = ii LLLL (tt) ii uuuu (tt) = ii LLLL (tt) [AA cccccc ΦΦ ][ssssss ωωωω] (4.9) Here, AA cccccc ΦΦ and ssssss ωωωω are the unknown and known parameters respectively. To achieve both unity power factor and sinusoidal waveforms at the source side, this case study is generally adopted. In this chapter, the unknown coefficient is estimated by using ADALINE-VLLMS based technique An ADALINE based detection technique Fig. 4.2 shows the block diagram of the ADALINE-VLLMS control algorithm for reference signal generation. It is composed of LL number of neurons whose weight vector WW(nn) is updated by applying the novel VLLMS adaptive algorithm. The input of each neuron is composed of unit magnitude sinusoidal input xx(nn) and its delay time values. For an effective harmonic elimination and reactive power compensation, the information of xx(nn) can be fully utilized for accurate estimation of ii uuuu (nn). The input vector UU(nn) and weight vector WW(nn) of the ADALINE are UU(nn) = [xx(nn) xx(nn ) xx(nn 2) xx(nn LL + )] TT (4.)

129 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF ii LLLL (nn) = ii uuuu (nn) + ii ffff (nn) II (nn) ZZ LL+ xx(nn LL + ) ww LL II (nn)xx(nn) ZZ 2 ZZ xx(nn 2) xx(nn ) ww 3 ww 2 Σ JJ ww jj (nn)uu jj (nn) jj = Σ ii uuuu (nn) Σ ii rrrrrrrr (nn) vv aa (nn) PLL xx(nn) ww VLLMS Weight Updating Rule ee aa (nn) Fig. 4.2: Functional block diagram of ADALINE-VLLMS based reference signal generation. WW(nn) = [ww (nn) ww 2 (nn) ww 3 (nn) ww LL (nn)] (4.) Referring Fig. 4.2, the estimated fundamental active component ii uuuu (nn) can be expressed as follows. ii uuuu JJ (nn) = jj = ww jj (nn)uu jj (nn) + II (nn)xx(nn) (4.2) where II (nn) is known as the loss component of VSI and calculated by DC-link voltage control loop. The difference between the actual load current ii LLLL (nn) and the estimated current ii uuuu (nn) induces an error signal ee aa (nn). The prediction error ee aa (nn), which is also considered as reference current ii rrrrrrrr (nn) for PWM control loops as depicted in Fig. 4.(b). This error signal can be expressed as ee aa (nn) = ii LLLL (nn) ii uuuu (nn) = ii ffff (nn) + [ii uuuu (nn) ii uuuu (nn)] (4.3) The MSE JJ(n) can be obtained by calculating the expectation of square of the prediction error ee aa (nn), and is given by JJ(nn) = EE{ee aa 2 (nn)} = EE ii ffff (nn) + [ii uuuu (nn) ii uuuu (nn)] 2 = EE ii 2 ffff (nn) + EE{[ii uuuu (nn) ii uuuu (nn)] 2 } + 2EE ii ffff (nn)ii uuuu (nn) ii ffff (nn)ii uuuu (nn) (4.4) 2

130 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF where EE{. } is the statistical expectation operator. ii ffff (nn) is uncorrelated with ii uuuu (nn) and ii uuuu (nn) because of the orthogonality of trigonometric functions. So the third term of (4.4) is neglected. Now, the cost function becomes JJ(nn) = EE ii 2 ffff (nn) + EE{[ii uuuu (nn) ii uuuu (nn)] 2 } (4.5) The objective of the VLLMS algorithm is to find the optimal weight vector WW(nn) of ADALINE that is evaluated by minimizing the MSE. In (4.5), EE ii ffff 2 (nn) is to be compensated and considered as a fixed value under a particular operating condition [24, 29, 3]. When ww jj (nn) is adjusted iteratively to make JJ(nn) minimal, the minimum value of cost function JJ(nn) mmmmmm is defined as JJ(nn) mmmmmm = EE ii 2 ffff (nn) + mmmmmm EE{[ii uuuu (nn) ii uuuu (nn)] 2 } (4.6) When ii uuuu (nn) ii uuuu (nn), JJ(nn) mmmmmm = EE ii 2 ffff (nn) (4.7) In the preceding equation, ii uuuu (nn) is the best least squares estimate of ii uuuu (nn). When this condition is achieved, the current reference ii rrrrrrrr (nn) is determined successfully. Similarly, the current references for phase-b and c can be calculated VLLMS weight adaptation rule The weights of ADALINE can be recursively updated using VLLMS learning rule as ww jj (nn + ) = ΔΔΔΔ(nn) ww jj (nn) + ΔΔee aa (nn)uu jj (nn) (4.8) where ΔΔ is a user-defined step size parameter, and γγ(nn) is the time-varying leakage factor. When γγ(nn) =, the aforementioned algorithm behaves as a conventional LMS, and for γγ(nn) >, the weights slowly decay towards the optimum values that avoids the parameter drift. The leakage factor is set to be large enough in the transient state to expedite the rate of convergence, but it is reduced at the steady-state. The weights update equation is based on minimizing an augmented instantaneous cost function [44, 45], which is given by JJ(nn) = ee 2 aa (nn) + γγ(nn)ww jj (nn) TT ww jj (nn) (4.9) Since the norm of the coefficient vector is minimized along with the error squared, the algorithm ensures that the weights don t drift. The variable leakage factor γγ(nn) can be adjusted by the following recursive expression 3

131 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF γγ(nn + ) = γγ(nn) ΔΔΔΔee aa (nn) uu jj (nn) TT ww jj (nn ) (4.2) where ρρ is a positive constant to be chosen by the designer. A sufficient condition that ensures convergence of the VLLMS algorithm is satisfied by choosing the step size parameter ΔΔ as limited by < ΔΔ < 2 γγ(nn)+λλ mmmmmm (4.2) where λλ mmmmmm is the maximum eigenvalue of the input autocorrelation matrix RR [44] DC-link voltage control loop To maintain a constant DC-link capacitor voltage under various operating conditions and compensate the system losses, the DC-link voltage control loop is used [6, 35]. Referring Fig. 4.(b), the voltage error VV eeeeee (nn) can be expressed as VV eeeeee (nn) = VV rrrrrr VV dddd (nn) (4.22) where VV rrrrrr and VV dddd (nn) are the fixed reference and feedback voltages respectively. The error voltage VV eeeeee (nn) is processed in the PI controller that yields the output current II (nn) as II (nn) = II (nn ) + KK PP {VV eeeeee (nn) VV eeeeee (nn )} + KK II VV eeeeee (nn) (4.23) where KK PP and KK II are the proportional and integral gains respectively. According to the voltage difference, the PI controller decides how much active current is needed to regulate the desired DC-link capacitor voltage. The output current II (nn) is multiplied with the reference signal xx(nn) and the resultant component is added to the output of the digital filter that produces the total useful components ii uuuu (nn) as expressed in (4.2). 4.4 Simulation results To evaluate the efficacy of the proposed ADALINE-VLLMS based detection algorithm, the system is modeled and analysed in the time-domain via MATLAB/Simulink environment. The parameters employed in the simulation studies are given in Table 4.. In this study, the performance of the HPF system equipped with proposed algorithm is verified under various operating conditions. 4

132 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Table 4.: List of parameters used in simulation tests System quantities Parameters Symbol Values Supply voltages (line to neutral) VV ss 4 V Source System frequency ωω ππ rad/s Supply inductors LL ss.5 mh Supply resistors RR ss. Ω Current-source type of nonlinear load RR LL, LL LL 25 Ω, 2 mh Load Ripple capacitor CC rr μf Smoothing inductors LL ssss 2.5 mh DC-link capacitor CC dddd μf VSI Passive filters Voltage control loop Initial values DC-link capacitor voltage VV rrrrrr 2 V Switching frequency ωω ss 2ππ rad/s Filter inductors LL pp 2.5 mh Filter capacitors CC pp 82.7 μf Filter resistors RR pp. Ω Proportional gain KK PPPP.2 Ω - Integral gain KK IIII 2 Ω - s - Leakage factor γγ. ADALINE s weights WW Steady-state performance of HPF The steady-state waveforms for harmonic elimination employing HPF with ADALINE- VLLMS algorithm are shown in Figs. 4.3(a)-(m). This test case is studied with balanced three-phase supply connected to balanced nonlinear load and the HPF is in operation at tt = s. In figures, top-to-bottom waveforms represent the source voltage vv aa, load current ii LLLL, source current ii ssss, HPF current ii ffff, inverter output voltage vv aa, DC-link capacitor voltage vv dddd, DC-link reference current II, active powers (PP LL, PP SS ), reactive powers (QQ LL, QQ SS ), and power factors. It is noticed that vv aa and ii ssss waveforms are pure sinusoidal with phase shift. The voltage across the capacitor is well regulated with an average value of 2 V. The maximum and minimum values of vv dddd are 8.5 V and 22.8 V respectively. The magnitude of II is zero. From Figs. 4.3(h)-(m), it is clearly observed that the waveforms of PP LL, QQ LL and power factor of load are of oscillating in nature because of nonlinear characteristics of the load current. These parameters oscillate in the range of (.6 kw to 2.6 kw), ( 2.4 kvar to.67 kvar) and (.825 to ), respectively. By employing HPF along with proposed controller, the waveforms of PP ss, QQ ss and power factor on the source side are maintained constant value of around 6.2 kw,.8 kvar and.994, respectively. 5

133 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Va (Volt) ila (Amp) isa (Amp) ifa (Amp) Va' (Volt) Vdc (Volt) Io (Amp) PL (Watt) Ps (Watt) QL (Var) x x x (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) Fig. 4.3: Waveforms of HPF under steady-state. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) Inverter voltage vv aa. (f) DC-link capacitor voltage vv dddd. (g) DC-link reference current II. (h) Instantaneous active power PP LL on load side. (i) Instantaneous active power PP SS on source side. (j) Instantaneous reactive power QQ LL on load side. 6

134 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Qs (Var) Magnitude Magnitude 2 x (k) (l) (m) Fig. 4.3: Continued. (k) Instantaneous reactive power QQ SS on source side. (l) Power factor on load side. (m) Power factor on source side. Vrefa (Volt) Vtri (Volt) (a) (b) ga (Volt) (c) ga' (Volt) (d) Fig. 4.4: Steady-state waveforms of HPF. (a) Reference voltage vv rrrrrrrr. (b) Triangular carrier wave vv tttttt. (c) Switching signal gg aa for IGBT SS aa. (d) switching signal gg aa for IGBT SS aa. Fig. 4.(b) illustrates the carrier-based PWM control technique to produce the switching signals for the operation of APF. The reference current of phase-a, i.e. ii rrrrrrrr is amplified by a resistive gain RR, which is compared with a khz triangular carrier wave vv tttttt to produce switching signal gg aa and its complement gg aa for pair of IGBTs in the same leg-a (i.e. SS aa and SS aa ) respectively as shown in Figs. 4.4(a)-(d). Similarly, other switching signals gg bb, gg bb, gg cc and gg cc can be produced for triggering the corresponding IGBTs SS bb, SS bb, SS cc and SS cc present in leg-b and c. 7

135 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Mag (% of Fundamental) Mag (% of Fundamental) Harmonic order 3 2 Fundamental (5Hz) = 28.6, THD= 32.44% Fundamental (5Hz) = 27.2, THD= 2.24% Harmonic order Fig. 4.5: Harmonic spectra. (a) Load current ii LLLL. (b) Source current ii ssss. (a) (b) Table 4.2: Harmonics content in load and source currents Order of harmonics Load currents Source currents ii LLLL ii LLLL ii LLLL ii ssss ii ssss ii ssss Fundamental 28.6 A 28.7 A 28.7 A 27.2 A A A 3 rd (5 Hz). A. A. A. A.2 A. A 5 th (25 Hz) 8.5 A 8.5 A 8.5 A.25 A.25 A.24 A 7 th (35 Hz) 2.43 A 2.42 A 2.42 A.9 A.8 A.8 A 9 th (45 Hz). A. A. A. A. A. A th (55 Hz).7 A.7 A.7 A.22 A.23 A.23 A 3 th (65 Hz).96 A.96 A.96 A.6 A.5 A.5 A 5 th (75 Hz). A. A. A. A. A. A 7 th (85 Hz).6 A.6 A.6 A.8 A.9 A.9 A 9 th (95 Hz).53 A.53 A.53 A.8 A.9 A.9 A 2 st (5 Hz). A. A. A. A. A. A 23 th (5 Hz).29 A.29 A.29 A.4 A.8 A.4 A 25 th (25 Hz).28 A.28 A.28 A.4 A.4 A.4 A THD 32.44% 32.43% 32.43% 2.24% 2.23% 2.23% The harmonic distortions of the load current ii LLLL and source current ii ssss with the application of HPF are depicted in Figs. 4.5(a) and (b), respectively. The load current ii LLLL is fully distorted and it has a THD of 32.44%. Whereas the THD of ii ssss is brought down to 2.24% by employing the proposed controller. This value is well below the restriction imposed by the IEEE standard Table 4.2 presents the comparative assessment of major harmonic components (both peak value and THD) of three-phase load and source currents using HPF system. 8

136 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF It is clearly observed that individual amplitude and THD of the harmonic components present in source current are minimized effectively by employing HPF with ADALINE-VLLMS controller Response of HPF under load current variation Figs. 4.6(a)-(k) depict the dynamic performance of HPF under a load current variation. In this study, the nonlinear load current amplitude is increased to nearly % at tt =.4 s, and maintained constant during tt =.4 s to.5 s. Then it comes down to the initial value. From figures, it is observed that the source current ii ssss is almost sinusoidal and follows the variation of load current ii LLLL. The DC-link capacitor voltage vv dddd fluctuates due to the variation of load current. The voltage vv dddd decreases with the increase of load current or vice versa to compensate the variation in real power supplied by the source. The DC-link voltage vv dddd has an undershoot of 7 V (i.e..83%) and overshoot of 55 V (i.e. 29.6%) following an increase and decrease of load current respectively. Additionally, ii ssss and vv dddd exhibit fast transient response (i.e. settling time around 3 ms) and stable operation under the load variation. The increased load current during.4 s tt <.5 s demands more active and reactive power. However, the system power factor remains unchanged and it is maintained with almost unity value by using HPF. Va (Volt) (a) ila (Amp) isa (Amp) ifa (Amp) (b) (c) (d) Fig. 4.6: Dynamic performance of HPF with a % increase in load current during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. 9

137 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Vdc (Volt) (e) PL (Watt) Ps (Watt) 4 x x (f) (g) QL (Var) 3 x (h) Qs (Var) Magnitude Magnitude 3 x (i) (j) (k) Fig. 4.6: Continued. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side Response of HPF under temporary disconnection of load Figs. 4.7(a)-(k) show the dynamic response under on- and off-load switching condition. During tt =.4 s to.5 s, load is completely disconnected from the system. When the load is removed (i.e. off-load) at tt =.4 s, the load current ii LLLL becomes zero. However, the passive filter provides a path for current flow from the inverter to source or vice-versa. During this off-load period, it is observed that both source and HPF currents are equal in magnitude as well as phase. However, there is a phase difference

138 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Va (Volt) ila (Amp) isa (Amp) ifa (Amp) (a) (b) (c) (d) Vdc (Volt) (e) PL (Watt) Ps (Watt) 3 x x (f) (g) QL (Var) Qs (Var) 2 x x (h) (i) Fig. 4.7: Dynamic performance of HPF under no-load condition during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side.

139 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Magnitude Magnitude (j) (k) Fig. 4.7: Continued. (j) Power factor on load side. (k) Power factor on source side. of 9 between ii ssss and vv aa. The vv dddd has an overshoot of 48 V (i.e %) and an undershoot of 2 V (i.e. 6.66%) at the instant of removal and re-application of load respectively. During.4 s tt <.5 s, PP ss = PP LL = W, QQ LL = Var and power factor on source side is zero. But, it is evident from Fig. 4.7(i) that QQ ss = 6.4 kvar during this off period because of ii ssss value. The load change does not produce any other undesirable behaviour and the proposed controller manages this transient situation effectively. At the instants of load changes, the steady-state values are achieved within two fundamental periods Response of HPF under voltage sag Figs. 4.8(a)-(k) show the response of HPF system to voltage sags. The supply voltages were subjected to dip of 25% (i.e. from 4 V to 3 V) at tt =.4 s and ends at tt =.5 s. The source current ii ssss is distorted for a period of 4 ms from the instants of transient occurrence. Then it becomes sinusoidal and THD is almost same as before transient. vv dddd is well regulated to 2 V by the voltage control loop. It is observed from figures that the active and reactive powers decrease at the instant of voltage dip. However, the source power factor is unaffected and maintained near unity value. Va (Volt) (a) ila (Amp) (b) Fig. 4.8: Dynamic performance of HPF under supply voltage sag during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. 2

140 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF isa (Amp) ifa (Amp) Vdc (Volt) (c) (d) (e) PL (Watt) Ps (Watt) x x x 4 (f) (g) QL (Var) x 4 (h) Qs (Var) Magnitude Magnitude (i) (j) (k) Fig. 4.8: Continued. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side. 3

141 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Dynamic performance of HPF to step increase in DC-link reference voltage In this study, the performance of HPF is evaluated under step increase of DC-link reference voltage and the relevant characteristics are shown in Figs. 4.9(a)-(k). The system is analysed under the increase of DC-link reference voltage from 2 V to 5 V at tt =.4 s and back to 2 V at tt =.5 s. It can be observed that the HPF equipped with proposed control techniques regulates the DC-link voltage vv dddd towards its new set points (i.e. 2 V for tt.4 s, 5 V for.4 s tt <.5 s and 2 V for tt.5 s) within one cycle. vv dddd has an overshoot of 65 V (i.e. 37.5%) and undershoot of V (i.e. 7.5%) at the instants of step increase and decrease of the DC-link reference voltage, respectively. During.4 s tt <.5 s, the values of PP ss, QQ ss and power factor remain unchanged. The waveform of ii ssss is slightly affected for a half cycle just after the transition of DC-link voltage. The THD of ii ssss is calculated during the transient period as.78%. The results strongly confirm that the proposed ADALINE-VLLMS technique works effectively in eliminating the harmonics, compensating the reactive currents and maintaining the DC-link capacitor voltage. Va (Volt) ila (Amp) isa (Amp) ifa (Amp) (a) (b) (c) (d) Vdc (Volt) 5 Fig. 4.9: Response of HPF with increase in DC-link reference voltage during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF currentii ffff. (e) DC-link capacitor voltage vv dddd (e)

142 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF PL (Watt) Ps (Watt) QL (Var) Qs (Var) Magnitude Magnitude 3 x x x x (f) (g) (h) (i) (j) (k) Fig. 4.9: Continued. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side Steady-state performance of HPF in a system with non sinusoidal supply In this case, the three-phase supply voltages are distorted by introducing harmonic voltages with the balanced supply system and their expressions are as follows. vv ssss = 4 cccccc(ωωωω) + 4 cccccc(3ωωωω) + 2 cccccc(5ωωωω) (4.24) vv ssss = 4 cccccc(ωωtt 2ππ ) + 4 cccccc(3ωωωω) + 2 cccccc(5ωωωω) (4.25) 3 vv ssss = 4 cccccc(ωωtt 4ππ ) + 4 cccccc(3ωωωω) + 2 cccccc(5ωωωω) (4.26) 3 These voltages are applied to the nonlinear loads in a distribution network with HPF system. Now the harmonics are produced in the load currents due to the combined 5

143 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF effect of utility- as well as customer-generated harmonic components. Figs. 4.(a)-(k) present the waveforms of distorted source voltage vv aa, load current ii LLLL, source current ii ssss, APF current ii ffff, DC-link capacitor voltage vv dddd, active power (PP LL, PP SS ), reactive power (QQ LL, QQ SS ) and power factors, respectively. It is evident from the figure that the waveform of ii ssss is pure sinusoidal and in phase with the fundamental of vv aa. The ADALINE-VLLMS based detection algorithm performs satisfactorily under this critical condition. The ripples appear in vv dddd is very small (i.e. within 2 V). PP ss is maintained with a constant value of 6 kw and QQ SS is correctly compensated with a minor oscillation of 2 Var to 5 Var. Thus the source power factor is maintained near unity value. Va (Volt) ila (Amp) isa (Amp) ifa (Amp) (a) (b) (c) (d) Vdc (Volt) (e) PL (Watt) 3 x (f) Ps (Watt) 3 x Fig. 4.: Steady-state performance of HPF with non sinusoidal source voltages. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) HPF current ii ffff. (e) DC-link capacitor voltage vv dddd. (f) Instantaneous active power PP LL on load side. (g) Instantaneous active power PP SS on source side. 6 (g)

144 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF QL (Var) Qs (Var) Magnitude Magnitude 2 x x (h) (i) (j) (k) Fig. 4.: Continued. (h) Instantaneous reactive power QQ LL on load side. (i) Instantaneous reactive power QQ SS on source side. (j) Power factor on load side. (k) Power factor on source side. Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) 5 Fundamental (5Hz) = 397.4, THD=.28% Harmonic order 3 2 Fundamental (5Hz) = 28.7, THD= 32.44% Harmonic order 3 2 Fundamental (5Hz) = 27.2, THD= 2.25% Harmonic order Fig. 4.: Harmonic spectra. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (a) (b) (c) The harmonic distortions of source voltage vv aa, load current ii LLLL and source current ii ssss with proposed compensation strategy are illustrated in Figs. 4.(a)-(c), 7

145 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF respectively. The corresponding THD values are computed as.28%, 32.44% and 2.25%. It is evident that the HPF with ADALINE-VLLMS algorithm compensates harmonics and maintains a sinusoidal source current. The comparative results obtained under various test cases is illustrated in Table 4.3. The THDs and fundamental peaks of source voltages, load currents and source currents of above described six test cases are presented. It is observed from test case 2 that there is a minor change in THDs of source currents as compared to the nominal values due to the increase of load current (i.e. a higher value of fundamental peak). Under the test case 3, current flows either from VSI to source or vice versa as the load is disconnected from the system and this current is maintained sinusoidal with very small THD value. Analysing test cases, 4 and 6, it is evident that the compensating performance of HPF with proposed ADALINE-VLLMS control strategy is unaffected under voltage dip as well as supply voltage distortion. However, the THDs of source currents are further decreased from nominal values due to the increase in DC-link reference voltage as described in test case 5. Table 4.3: Summary of the simulation results Test cases Supply/nonlinear load conditions Items PCC voltages (during.4 ss < tt <.5 ss) Load currents (during.4 ss < tt <.5 ss) Source currents (during.4 ss < tt <.5 ss) Phase-a Phase-b Phase-c Phase-a Phase-b Phase-c Phase-a Phase-b Phase-c 2 3 Sinusoidal balanced supply with balanced nonlinear load (steadystate performance of HPF) Sinusoidal balanced supply with balanced nonlinear load (during.4 s tt <.5 s load current is increased to %) Sinusoidal balanced supply with balanced nonlinear load (during.4 ss tt <.5 ss load is disconnected) Fund Peak V V V 28.6 A 28.7 A 28.7 A 27.2 A A A THD.6%.6%.6% 32.44% 32.43% 32.43% 2.24% 2.23% 2.23% Fund Peak V V V A A A 5.9 A 5.2 A 5.4 A THD.64%.64%.64% 24.78% 24.77% 24.79%.83%.84%.86% Fund Peak 4.5 V 4.5 V 4.5 V.75 A.76 A.76 A THD.2%.2%.2%.69%.73%.67% 4 Sinusoidal balanced supply with balanced nonlinear load (during.4 ss tt <.5 ss supply voltage is decreased by 25%) Fund Peak 298 V 298. V 298 V 2.6 A 2. A 2.8 A 2.33 A 2.34 A 2.48 A THD.27%.78%.52% 32.4% 32.48% 32.37% 2.28% 2.27% 2.6% 5 6 Sinusoidal balanced supply with balanced nonlinear load (during.4 ss tt <.5 ss DC-link reference voltage is increased to 25%) Non sinusoidal balanced supply with balanced nonlinear load (steady-state response of HPF) Fund Peak V V V 28.6 A 28.7 A 28.6 A 27.2 A 27.2 A 27.2 A THD.72%.7%.72% 32.45% 32.44% 32.44%.78%.76%.82% Fund Peak V V V 28.7 A 28.7 A 28.6 A 27.2 A A A THD.28%.27%.27% 32.44% 32.43% 32.44% 2.25% 2.2% 2.24% 8

146 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF 4.5 Experimental results To evaluate the performance of proposed ADALINE-VLLMS control algorithm applied for HPF, a prototype is developed and tested in the laboratory under various operating conditions such as steady-state and dynamic load conditions. The test setup developed for the experimental study is shown in Fig In this test set-up, the nonlinear load is obtained by an SKKD /6 diode bridge rectifier supplying inductive load. The VSI consists of six PM25RSB2 IGBTs. Reduced balanced power supply is fed to the load through an autotransformer. A sampling frequency of khz has been selected for the entire system operation. Three current sensors of model LEM LV25-P are used to track the three-phase load currents. Similarly, four voltage sensors of model LEM LTS25-NP are used to measure the three-phase source voltages at PCC and a DC-link capacitor voltage. The system parameters used for real-time analysis are presented in Table 4.4. The specifications used in the experimental setup are basically considered with low rated values, whereas high rated system parameters are used for the simulation study. The proposed ADALINE-VLLMS algorithm is implemented in the SPARTAN-3A XC3SD8A DSP processor via Xilinx ISE 2. software. A signal conditioning circuit is designed to amplify and provide the necessary offset required by the ADC. The device utilization summary is described in Table 4.5. The waveforms are captured and stored by the Tektronix TPS22B DSO and the harmonic distortions are evaluated by TPS2PWR software. Table 4.4: List of parameters used in experimental tests System quantities Parameters Symbol Values Supply voltages (line to neutral) VV ss V Source System frequency ωω ππ rad/s Supply inductors LL ss.2 mh Load Current-source type of nonlinear load RR LL, LL LL 5 Ω, 36 mh DC-link capacitor CC dddd 22 μf VSI Passive filters Voltage control loop DC-link capacitor voltage VV rrrrrr 5 V Switching frequency ωω ss 2ππ rad/s Filter inductors LL pp.5 mh Filter capacitors CC pp 4 μf Proportional gain KK PPPP.2 Ω - Integral gain KK IIII 2 Ω - s - 9

147 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF Fig. 4.2: Photograph of experimental setup for implementing the proposed algorithm. Table 4.5: Device utilization summary Logic utilization Used Available Utilization Number of slice flip flops,639 33,28 4% Number of 4 input LUTs 4,486 33,28 3% Number of occupied slices 2,89 6,64 6% Number of slices containing only related logic 2,89 2,89 % Number of slices containing unrelated logic 2,89 % Total number of 4 input LUTs 4,996 33,28 5% Number used as logic 4,453 Number used as a route-thru 5 Number used as shift registers 33 Number of bonded IOBs 6 59 % Number of BUFGMUXs % Number of DSP48As % Average fanout of non-clock nets Steady-state performance of HPF Figs. 4.3(a)-(e) show the steady-state waveforms of three-phase source voltages (vv aa, vv bb, vv cc ), three-phase load currents (ii LLLL, ii LLLL, ii LLLL ), three-phase source currents 2

148 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF vv aa ii LLLL vv bb (a) ii LLLL (b) vv cc ii LLLL ii ssss ii ffff ii ssss (c) ii ffff (d) ii ssss ii ffff vv aa vv dddd ii ssss (e) (f) II ii LLLL ii ffff Fig. 4.3: Experimental waveforms under steady-state condition (all plots XX aaaaaaaa =. ss/dddddd). (a) Source voltages (vv aa, vv bb, vv cc ) YY aaaaaaaa = VV/dddddd. (b) Load currents (ii LLLL, ii LLLL, ii LLLL ) YY aaaaaaaa = 5 AA/ dddddd. (c) Source currents (ii ssss, ii ssss, ii ssss ) YY aaaaaaaa = 5 AA/dddddd. (d) Compensating currents (ii ffff, ii ffff, ii ffff ) YY aaaaaaaa = 5 AA/dddddd. (e) DC-link capacitor voltage (VV dddd ) YY aaaaaaaa = 25 VV/dddddd and DC-link reference current (II ) YY aaaaaaaa = 5 AA/dddddd. (f) Top-to-bottom plots source voltage (vv aa ) YY aaaaaaaa = 2 VV/dddddd, source current (ii ssss ) YY aaaaaaaa = 5 AA/dddddd, load current (ii LLLL ) YY aaaaaaaa = AA/dddddd, HPF current (ii ffff ) YY aaaaaaaa = 5 AA/dddddd, with HPF. (ii ssss, ii ssss, ii ssss ), three-phase compensating currents (ii ffff, ii ffff, ii ffff ), and DC-link parameters (vv dddd, II ), respectively. From figures, it is noticed that {ii ssss, ii ssss, ii ssss } are almost pure sinusoidal. In addition, DC-link capacitor voltage vv dddd is regulated to its reference value with a minor ripple of V, and the magnitude of PI controller output (II ) is set to zero. The reactive power and harmonic components of the load currents are almost compensated by the HPF currents. Therefore, system power factor has increased from.853 to.93 with the utilization of HPF system. Fig. 4.3(f) shows the experimental waveforms under steady-state with the application of HPF. In this figure, the top-to- 2

149 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF (a) (b) (c) (d) Fig. 4.4: Harmonic spectra. (a) FFT of load current (ii LLLL ). (b) THD of load current (ii LLLL ). (c) FFT of source current (ii ssss ). (d) THD of source current (ii ssss ). bottom waveforms represent the source voltage vv aa, source current ii ssss, load current ii LLLL and compensating currents ii ffff, respectively. From these waveforms, it is observed that phase angle between ii ssss and vv aa is decreased from to 2.6, with the application of HPF. A comparative result of the harmonic spectrum (both FFT and THD) of load current ii LLLL and source current ii ssss are obtained from an experimental setup as depicted in Fig It is observed from Fig. 4.4(a) that ii LLLL is fully distorted with the maximum number of harmonics. The THD of ii LLLL is 27.8% as shown in Fig. 4.4(b). However, ii ssss has a negligible amount of harmonics with a THD of 7.3% as illustrated in Fig. 4.4(d). It is evident from these figures that the individual harmonic amplitude of ii ssss is reduced significantly by employing HPF in a system. THDs are captured by Tektronix TPS22B DSO externally connected with a TPS2PWR software module Dynamic performance of HPF to a load variation Fig. 4.5 demonstrates the experimental waveforms under the dynamic load change. In Figs. 4.5(a) and (b), top-to-bottom waveforms represent source voltage vv aa, source current ii ssss, load current ii LLLL and compensating currents ii ffff in phase-a respectively. 22

150 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF vv aa vv aa ii ssss ii ssss (a) (b) ii LLLL ii LLLL ii ffff ii ffff ii LLLL ii LLLL vv dddd (c) vv dddd (d) ii ssss ii ssss Fig. 4.5: Experimental waveforms under transient condition (all plots XX aaaaaaaa =.25 ss/dddddd). (a) and (b) Top-to-bottom plots source voltage (vv aa ) YY aaaaaaaa = 2 VV/dddddd, source current (ii ssss ) YY aaaaaaaa = AA/dddddd, load current (ii LLLL ) YY aaaaaaaa = AA/dddddd, filter current (ii ffff ) YY aaaaaaaa = AA/dddddd with increase the load from.5 kw to kw and vice versa, respectively.(c)-(d) Top-to-bottom plots load current (ii LLLL ) YY aaaaaaaa = AA/dddddd, source current (ii ssss ) YY aaaaaaaa = AA/dddddd, DC-link capacitor voltage (VV dddd ) YY aaaaaaaa = VV/dddddd, with increase the load from.5 kw to kw and vice versa, respectively. Figs. 4.5(c) and (d) depict the waveforms from top-to-bottom as load current ii LLLL, source current ii ssss and DC-link capacitor voltage vv dddd, respectively. Figs. 4.5(a) and (c) show the compensating waveforms under sudden increases of a load from.5 kw to kw, whereas Fig. 4.5(b) and (d) depict the characteristics under load decreases from kw to.5 kw. It is very much evident from these figures that under dynamic load change, the ii ssss waveform is almost sinusoidal in nature with a minor distortion. Moreover, the proposed controller adapts to the updated current value based on the dynamic load change within a fundamental period. The percentage of overshoot and undershoot occurs in vv dddd is limited within 5%. 4.6 Chapter summary A novel ADALINE-VLLMS control scheme is applied to generate the reference signal for HPF. A low rated and small size HPF topology employing proposed control 23

151 Chapter 4: Power quality improvement using ADALINE-VLLMS based HPF algorithm has ability to compensate harmonics and reactive power drawn by a nonlinear load. To validate the efficacy of the proposed controller in the real-time application, a prototype is developed and tested under both steady-state as well as transient conditions. The findings reveal that combined ADALINE-VLLMS approach is accurate, faster in convergence and more stable under the load variation. Because of these advantages, the proposed control strategy is a viable and effective solution for HPF system in improving the power quality of a distribution network. 24

152 Chapter 5 Harmonic Elimination Using SWFA Based HPF System and Evaluation of Compensation Effect Employing ADALINE-DFFRLS Algorithm 5. Introduction Contemporary power electronics devices have enormously participated to the advancement of modern applications and industrial solutions. These developments have simultaneously augmented the current harmonic pollution in the distribution power network. These harmonic currents degrade the power quality of the system. Thus it has necessitated research interest in current harmonic studies, which includes dynamic filtering and evaluation of compensation effect. The objective of this research work is to design a low rated and small size APF topology with a novel composite control strategy for effective elimination of harmonics. In addition, a high-performance estimation algorithm is employed for fast and accurate measurement of the compensation effect. APFs have attracted significant attention and are expected to be an appropriate remedy for harmonic elimination and reactive power compensation. The major 25

153 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS disadvantage is that the required DC-link voltage across the capacitor used for standalone APFs must be more than 5% of the supply voltage, which is used in chapter 3. In consideration of the cost and limited power rating of the semiconductor devices used for designing inverter, it is very much difficult for implementing the standalone APF in high- and medium-voltage applications. For reducing the rating of an APF, an enhanced HPF topology is proposed in chapter 4. Considering HPF topology, the required DC-link capacitor voltage in medium and high power applications reduces significantly. However, a midpoint DC-link capacitor topology is adopted in this chapter to suppress the voltage stress of IGBTs additionally [66, 74, 82]. The neutral line of the AC source is directly connected to the midpoint of two capacitors, thus the voltage across the individual capacitor is equal to half of the conventional DC-link capacitor voltage. Therefore, the adopted HPF topology has low cost, low voltage stress, low rating and high system performance, which leads to practical implementation in high- and medium-voltage applications. To enhance the compensation performance of HPF system, an SWFA technique is utilized in this study [75, 5]. The novel composite current control technique employs SWFA based high pass filtering for determining the reference voltages and SWFA based low pass filtering for absorbing the 5 tth harmonic negative sequence currents. In addition, PI controller is used for maintaining the required DC-link capacitor voltage. To evaluate the compensation effect employing HPF in a system, an ADALINE-DFFRLS based estimation algorithm is utilized in this research work. Several past pieces of literature have concentrated towards the application of an ADALINE for parameter estimation. This technique is widely used because of its simple structure, minimum tracking error and faster convergence rate. In general, the weights of the ADALINE are updated by standard LMS and RLS algorithms. Though RLS based weight updating rule is fast and accurate in a steady-state condition, but its overall performance is degraded in time-varying as well as noisy environments because of the constant forgetting factor [47, 48]. Therefore, the RLS algorithm requires some modification to enhance the performance competently in such situations. To evaluate the parameters effectively, a dynamic forgetting factor (DFF) mechanism is adopted with the conventional RLS. The DFF mechanism adjusts the value of forgetting factor either high (low) depending on the estimation error small (large) to achieve faster convergence [47-5]. The performance of the proposed ADALINE-DFFRLS 26

154 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS estimation algorithm is compared with the ADALINE-RLS algorithm in order to exemplify its faster-tracking capability. Extensive simulation is carried out to show the compensating performance of the HPF system employing SWFA based proposed controller under different critical conditions. Additionally, an experimental setup is developed for validation of the proposed control technique in the real-time using a Spartan 3A DSP processor. ADALINE-DFFRLS based estimation algorithm is utilized to evaluate the compensation effect of HPF system by analyzing both load and source currents. 5.2 System description Fast dynamic response and high-frequency switching make APF a strong candidate for compensation of low power quality events such as harmonic, reactive and negative sequence currents. The configuration of HPF system for improving the power quality in a distribution network is presented in Fig. 5.. This system consists of a three-phase nonlinear load fed from a three-phase AC supply. The source impedance comprises of resistance (RR ss ) and inductance (LL ss ). APF is a three-phase VSI using six IGBT switches ( ss aa, ss aa, ss bb, ss bb, ss cc, ss cc ) and a DC-link capacitor (CC dddd ). The APF is connected in parallel CC LL RR LL Nonlinear Load ss aa ss bb ss cc vv ssss RR ss LL ss ii ssss ii LLLL ii LLLL ii LLLL vv aa RR PP LL PP CC PP ii ffff vv aa CC dddd vv ssss ii ssss vv bb ii ffff vv bb vv ssss ii ssss vv cc Passive Filter ii ffff vv cc CC dddd 2 3-Φ 4-Wire AC Mains (a) PLL vv dddd vv dddd 2 ss aa ss bb ss cc Active Power Filter ii ssss ii ssss ii ssss ii LLLL ii LLLL ii LLLL ADALINE-DFFRLS Algorithm for Source Current Parameter Estimation [Fig. 5.4] ADALINE-DFFRLS Algorithm for Load Current Parameter Estimation ii ssss ii ssss ii ssss ii LLLL ii LLLL ii LLLL Control Technique for Voltage References Generation [Fig. 5.2] vv rrrrrrrr vv rrrrrrrr vv rrrrrrrr Triangular Carrierbased PWM Control Technique gg aa gg aa gg bb gg bb gg cc gg cc Gating Signals for IGBTs Harmonic Estimation Current and Voltage Control Loops (b) Fig. 5.: Main circuit description and control block diagrams. (a) Configuration of three-phase four-wire midpoint DC-link capacitor HPF topology. (b) Harmonic parameter estimation, reference signal calculation and switching signal generation. 27 PWM Control Loops

155 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS with the nonlinear loads through high-rated 7 tth order tuned PPF (RR PP, LL PP, CC PP ) at PCC. The nonlinear load is a three-phase diode bridge rectifier with a parallel RC branch (CC LL RR LL ) on the DC side. The nonlinear load currents (ii LLLL, ii LLLL, ii LLLL ) drawn from source contain fundamental and harmonic components. By utilizing HPF system, the compensated source currents (ii ssss, ii ssss, ii ssss ) become nearly sinusoidal and in-phase with the PCC voltages (vv aa, vv bb, vv cc ), respectively. 5.3 Control techniques for harmonic and reactive currents extraction The control technique used for HPF operation comprises of three main parts. In the first part, the feedback signals are sensed using current and voltage sensors. In the second part, the sum of all harmonic currents is extracted by using SWFA based control strategy to evaluate the reference signals. Then the switching signals used for turning on/off the IGBTs are generated by feeding the reference signals to the PWM control system. Fig. 5.2 illustrates the proposed control strategy employed to extract the reference signals for the HPF system. The collected three-phase source currents (ii ssss, ii ssss, ii ssss ), three-phase load currents (ii LLLL, ii LLLL, ii LLLL ) and DC-link capacitor voltages (vv dddd, vv dddd2 ) are fed to the harmonic current control loop, 5 tth harmonic control loop, and DC voltage control loop respectively. {ii ssss, ii ssss, ii ssss } are sensed and transformed into the synchronous reference frame with the fundamental frequency ωω that yields the currents {ii ssss, ii ssss } in dq frame. The general transformation from abc to dq is expressed as follows xx dd cccccc θθ cccccc(θθ 2ππ ) cccccc(θθ 4ππ ) 3 3 xx aa xx qq = 2 3 ssssss θθ ssssss(θθ 2ππ ) ssssss(θθ 4ππ ) xx bb (5.) 3 3 xx xx cc 2 2 where θθ = ωωtt is the transformation angle and xx denotes current or voltage variable. In this reference frame, the fundamental frequency appears as DC components and harmonics considered as AC-components [96-98]. Two first order LPFs are used in d- and q-axis for extracting the DC components {ii ssss,dddd, ii ssss,dddd } from the transformed 2 28

156 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS RR pp ii LLLL ii LLLL ii LLLL abc-dq Sync. Frame Trans ii LLLL ii LLLL,DDDD 5 tth Harmonic Control Loop ii LLLL LPF/SWFA LPF/SWFA ii LLLL,DDDD 5ωωLL pp 5ωωCC pp 5ωωLL pp + 5ωωCC pp vv LLLL vv LLLL dq-abc Sync. Frame Trans vv LLLL vv LLLL vv LLLL 5ωωωω RR pp 5ωωωω ii ssss ii ssss ii ssss abc-dq Sync. Frame Trans LPF/SWFA ii ssss ii ssss,dddd ii ssss,aaaa Harmonic Current Control Loop ii ssss ii ssss,dddd ii ssss,aaaa LPF/SWFA ii hdd ii hqq dq-abc Sync. Frame Trans ii haa ii hbb ii hcc RR RR RR vv haa vv hbb vv hcc vv rrrrrrrr vv rrrrrrrr vv rrrrrrrr ωωωω ωωωω vv dddd PI Controller II vv dddd 2 VV rrrrrr DC Voltage Control Loop vv dddd PI Controller II 2 Fig. 5.2: Block diagram of LPF based conventional and SWFA based proposed control techniques for voltage references generation. source currents {ii ssss, ii ssss }, respectively. In this study, the cutoff frequency of each LPF is chosen as ff cc = ff 3. The AC components {ii ssss,aaaa, ii ssss,aaaa } are determined by high pass filtering method as follows: ii ssss,aaaa = ii ssss ii ssss,dddd = ii ssss LLLLLL [ii ssss ] ii ssss,aaaa = ii ssss ii ssss,dddd = ii ssss LLLLLL [ii ssss ] (5.2) For compensating the system loss and maintaining the exact equal voltages across each DC-link capacitor, II and II 2 dynamics are obtained from the voltage control loop as shown in Fig The reference currents {II, II 2 } can be evaluated as II = KK PP + KK II (vv SS dddd2 vv dddd ) II 2 = KK PP2 + KK II2 (VV SS rrrrrr (vv dddd + vv dddd2 )) (5.3) where KK PP,2 and KK II,2 are the proportional and integral gains respectively. Using (5.2) and (5.3), the total harmonic components {ii hdd, ii hqq } can be expressed as ii hdd = ii ssss,aaaa + II ii hqq = ii ssss,aaaa + II 2 (5.4) Then, the total harmonic currents {ii haa, ii hbb, ii hcc } present in the source currents can be obtained using the inverse transformation as 29

157 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS ii haa ii hbb ii hcc cccccc θθ ssssss θθ 2 = 2 3 cccccc(θθ 2ππ ) ssssss(θθ 2ππ ) cccccc(θθ 4ππ ) ssssss(θθ 4ππ ) 3 3 The above harmonic currents are amplified by a resistive gain RR as vv haa vv hbb vv hcc 3 2 ii hdd ii hqq (5.5) ii ii haa = RR ii hbb (5.6) ii hcc During this extraction process, the fundamental active component is still contaminated with 5 tth order negative sequence component due to the poor filtering performance of 7 tth tuned passive filter. To overcome this limitation, an additional 5 tth harmonic control loop is utilized in the control system. This control loop is introduced to make the passive filter absorb all amounts of 5 tth harmonic negative sequence currents. {ii LLLL, ii LLLL, ii LLLL } are transformed into the dq rotating frame with 5 tth order harmonic frequency (i.e. 25 Hz) by using (5.) [96]. Similarly, the d- and q-axis of load currents {ii LLLL, ii LLLL } are processed through two first order LPFs to extract their DC components {ii LLLL,DDDD = LLLLLL [ii LLLL ], ii LLLL,DDDD = LLLLLL [ii LLLL ]}. The voltage references {vv LLLL, vv LLLL } to compensate the 5 tth harmonic negative sequence currents in a steady-state can be calculated as vv LLLL = RR pp ii LLLL,DDDD + 5ωωLL pp ii 5ωωCC LLLL,DDDD pp (5.7) vv LLLL = RR pp ii LLLL,DDDD + 5ωωLL pp + ii 5ωωCC LLLL,DDDD pp Using inverse transformation, the three-phase reference voltages {vv LLLL, vv LLLL, vv LLLL } can be computed in the similar manner as (5.5). The voltage commands {vv rrrrrrrr, vv rrrrrrrr, vv rrrrrrrr } of the LPF based controller can be obtained as vv rrrrrrrr vv rrrrrrrr vv rrrrrrrr vv LLLL = vv LLLL vv LLLL vv haa + vv hbb (5.8) vv hcc These voltage commands are compared with a high-frequency triangular carrier wave to generate the gating pulses for the respective IGBTs. In the conventional control scheme, the LPFs are used to track the fundamental components from the measured currents and applied to the closed-loop current control strategy. However, the LPF based filtering approach results in slow transient response

158 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS tt (NNii+PP) tt (NNii +PP ) tt (NNii) tt (NNii ) Insert Remove ii ssss,dddd (tt mm ), ii ssss,dddd (tt mm ) ii ssss,dddd (tt mm ), ii ssss,dddd (tt mm ) 2 PP {AA dd, AA qq } Fig. 5.3: SWFA based fundamental component extraction. due to the limited controller gain at higher harmonic frequencies [92]. The filtering performance can be enhanced by using higher-order LPF. But, the higher-order LPF provides more delay and phase shift. Thus the use of higher order filter is not an effective solution. Additionally, the idea of selecting the cutoff frequency of LPF plays a vital role in filtering performance appraisal. To overcome these limitations, an SWFA method is employed in this study to extract the fundamental DC components from the transformed currents with less delay. The DC components of the source currents ii ssss,dddd (tt mm ), ii ssss,dddd (tt mm ) for mm =, 2,, (PP ), can be expressed as ii ssss,dddd (tt mm ) = AA dd 2 ii ssss,dddd (tt mm ) = AA qq 2 (5.9) The SWFA method is presented in Fig The fundamental coefficients {AA dd, AA qq } can be computed as AA dd = 2 NN ii +PP ii PP kk=nn ii ssss,dddd(tt mm ) AA qq = 2 NN ii +PP ii PP kk=nn ii ssss,dddd(tt mm ) (5.) where NN ii is the initial point for the computation. The values of {AA dd, AA qq } for the first period can be calculated by using (5.), which are considered as initial values for the SWFA algorithm [75, 5]. For the next period onwards, {AA dd, AA qq } can be estimated as follows AA dd,nnnnnn = AA dd,oooooo 2 AA qq,nnnnnn AA ii ssss,dddd(tt (NNii )) qq,oooooo PP ii ssss,dddd (tt (NNii )) + 2 ii ssss,dddd(tt (NNii +PP)) (5.) PP ii ssss,dddd (tt (NNii +PP)) 3

159 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Then the AC components {ii ssss,aaaa, ii ssss,aaaa } are obtained using (5.2). Similarly, the DC components {ii LLLL,DDDD, ii LLLL,DDDD } of the 5 tth harmonic control loops can be computed by using (5.9)-(5.). 5.4 Algorithms for parameter estimation A periodic and distorted load current ii LLLL (tt) can be represented by the sum of fundamental frequency and harmonic components. During amplitude and phase estimation, the fundamental frequency of the signal is assumed to be constant. The Fourier series expansion of ii LLLL (tt) can be written as ii LLLL (tt) = AA + NN AA 2 nn= nn ssssss(nnωωtt + ΦΦ nn ) (5.2) where ωω is the angular frequency, AA nn and ΦΦ nn are the amplitude and phase angle of the nn tth order component respectively, NN is the total number of harmonic components including fundamental. Since distorted current signal ii LLLL (tt) is symmetrical in nature, the average value (i.e. DC component AA ) is zero. Equation (5.2) can be expressed in the matrix form as ii LLLL (tt) = NN nn= (AA nn cccccc ΦΦ nn ssssss nnωωtt + AA nn ssssss ΦΦ nn cccccc nnωωtt) = NN [ssssss nnωωtt cccccc nnωωtt] AA nncccccc ΦΦ nn nn= (5.3) AA nn ssssss ΦΦ nn For real-time implementation, this continuous time signal is discretized with a uniform sampling rate of TT ss. Considering ii LLLL (tt mm ) represents a discrete current signal at an arbitrary sampling time tt mm with mm =, 2,, (PP ); ii LLLL (tt ), ii LLLL (tt 2 = tt + TT ss ), ii LLLL (tt 3 = tt + 2TT ss ),, ii LLLL (tt PP = tt + (PP )TT ss ) denote the discrete current signals at various sampling instants respectively [3]. Here PP is the total number of sampled points in one cycle. Equation (5.3) can be rewritten as follows. ii LLLL (tt mm ) = [ssssss ωωtt mm cccccc ωωtt mm ssssss NNωωtt mm cccccc NNωωtt mm ] AA cccccc ΦΦ AA ssssss ΦΦ AA NN cccccc ΦΦ NN AA NN ssssss ΦΦ NN (5.4) Assuming tt mm = kk, the preceding equation can be written in vector form as 32

160 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS cccccc(nnnnnn) xx(2nn)aa (kk) ww(2nn) ii LLLL (kk) ssssss(nnnnnn) xx(2nn )aa (kk) ww(2nn ) ii LLLL (kk) cccccc(ωωωω) xx 2aa (kk) ww 2 ssssss(ωωωω) xx aa (kk) ww DFFRLS Algorithm ee aa (kk) Fig. 5.4: ADALINE-DFFRLS for estimation of fundamental and harmonic components. ii LLLL (kk) = xx aa (kk)ɵ (5.5) During the simulation study, the fundamental and sampling frequencies are set by the user and the input vector xx aa (kk) can be generated via PLL. The unknown vector Ɵ needs to be estimated by using ADALINE method. The functional block diagram of ADALINE for estimation of fundamental as well as harmonic parameters is presented in Fig It is composed of 2NN number of neurons whose weight vector is represented as ww(kk) = [ww (kk) ww 2 (kk) ww (2NN ) (kk) ww (2NN) (kk)] TT. The estimated signal ii LLLL (kk) can be constructed by the multiplication of the unit magnitude input vector xx aa (kk) and an adjustable weighting vector ww(kk). Hence ii LLLL (kk) = xx aa (kk)ww(kk ) (5.6) The difference between the actual signal ii LLLL (kk) and estimated signal ii LLLL (kk) yields the error signal ee aa (kk) as ee aa (kk) = ii LLLL (kk) ii LLLL (kk) = ii LLLL (kk) xx aa (kk)ww(kk ) (5.7) The objective is to find out the optimal weight vector by utilizing the adaptation rule that minimizes the error ee aa (kk). After updating the ADALINE s weight vector ww(kk) using DFFRLS algorithm, the estimates [AA, AA 2,, AA NN ] and [ΦΦ, ΦΦ 2,, ΦΦ NN ] are computed as AA nn = (ww 2 (2nn) + ww 2 (2nn ) ) (5.8) ΦΦ nn = tttttt ww (2nn) ww(2nn ) (5.9) 33

161 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS 5.4. DFFRLS weight updating rule Though the required computational resources of RLS algorithm are high, but it exhibits the fastest convergence rate and robustness. Therefore, it is widely used in signal processing and control applications. The weight vector ww(kk), gain vector GG(kk) and the inverse of the input correlation matrix RR(kk) at each sampling instant, are updated as ww(kk) = ww(kk ) + GG(kk)ee aa (kk) (5.2) GG(kk) = RR(kk )xx aa (kk) λλ+xx TT aa (kk)rr(kk )xx aa (kk) (5.2) RR(kk) = λλ [RR(kk ) GG(kk)xx aa TT (kk)rr(kk )] (5.22) where λλ is the fixed forgetting factor that ranges within ( < λλ ) [-3]. The performance, i.e. convergence rate, tracking and stability of the RLS algorithm are enhanced with the appropriate value of forgetting factor. When λλ, the algorithm achieves better stability, low misadjustment level and slow convergence rate. With λλ, it provides faster convergence rate, large misadjustment level, and poor stability. Thus RLS cannot afford satisfactory performance in time-varying environment by considering constant forgetting factor value. To overcome this limitation, the RLS algorithm with DFF implementation is necessary. The proposed control theory is to adjust the forgetting factor automatically to minimize the MSE and boost the estimation performance [47-5]. The updating equation of the DFF λλ(kk) can be expressed as λλ(kk) = λλ + +zz(kk) λλ (5.23) λλ where [ ] + λλ denotes the truncation to the limits of the range [λλ+, λλ ]. λλ + and λλ represent an upper and lower level of truncation. The variable component zz(kk) can be adjusted as zz(kk) = CC zz(kk ) + CC 2 χχ 2 (kk) (5.24) where CC and CC 2 are constant values within ( < CC < ) and (CC 2 > ). The time average estimate χχ(kk) is associated with the correlation of ii LLLL (kk) ww TT (kk)xx aa (kk) and ii LLLL (kk ) ww TT (kk )xx aa (kk ). It can be updated as χχ(kk) = CC 3 χχ(kk ) +( CC 3 ) ii LLLL (kk ) ww TT (kk )xx aa (kk ) ii LLLL (kk) ww TT (kk)xx aa (kk) (5.25) 34

162 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS where ( < CC 3 < ) is a constant value that controls the time average estimate. At the starting stage, the large estimate error correlation χχ 2 (kk) will cause the higher value of variable component zz(kk) that suppresses the DFF λλ(kk) and favors to achieve faster convergence rate. When the steady-state is achieved, the estimate error correlation χχ 2 (kk) reaches to a small value that yields the decrease in variable component zz(kk); thereby the DFF λλ(kk) is increased and provides faster convergence. In this way, the DFF mechanism performs weight adaptation of ADALINE effectively under steadystate as well as transient conditions Computational complexity The resource requirement of the ADALINE-RLS algorithm is 3NN 2 + 5NN + number of matrix multiplications and 5 2 NN2 + 3 NN number of matrix additions for computation of 2 a single iteration. Whereas ADALINE-DFFRLS algorithm needs three additional operations. Calculate the DFF λλ(kk) using (5.23), which requires one matrix multiplication and one matrix addition. Update the variable component zz(kk) as expressed in (5.24), which demands three matrix multiplications and one matrix addition. Update the time average estimate χχ(kk) in (5.25), which needs three matrix multiplications and two matrix additions. Therefore, the total computational complexity of the proposed algorithm is 3NN 2 + 5NN + 8 number of matrix multiplications and 5 2 NN2 + 3 NN + 4 number of matrix 2 additions per iteration. 5.5 Simulation results To investigate the dynamic compensation using the HPF system with proposed control strategy, the system is modelled and analysed under the following critical conditions via MATLAB/Simulink environment. The parameters used in the simulation study are given in Table 5.. The THDs and harmonic parameters estimation of the source currents before and after filtering assess the power quality of the proposed system. 35

163 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Table 5.: List of parameters used in simulation tests System quantities Parameters Symbol Values Supply voltages (line to neutral) VV ss.5 kv Source System frequency ωω ππ rad/s Supply inductors LL ss.5 mh Supply resistors RR ss. Ω Load Voltage-source type of nonlinear load RR LL, CC LL 5 Ω, 5 μf DC-link capacitors CC dddd = CC dddd2 5 μf VSI DC-link capacitor voltage VV rrrrrr 33 V Switching frequency ωω ss 2ππ rad/s Filter inductors LL pp 5 mh Passive filters Filter capacitors CC pp 4 μf Filter resistors RR pp. Ω Voltage control loop Proportional gains KK PP = KK PP2.2 Ω - Integral gains KK II = KK II2 2 Ω - s - Initial values ADALINE s weights WW.8 CC.99 Constant values Controlling parameters CC 2. CC 3.99 Truncation operator Upper level of truncation λλ Lower level of truncation λλ Steady-state performance of HPF system The comparative steady-state waveforms of HPF for harmonic elimination using conventional and proposed control techniques are shown in Figs. 5.5(a)-(n). First two waveforms from the top of Fig. 5 represent the source voltage vv aa and distorted load current ii LLLL of a system. The remaining waveforms from top-to-bottom depict the source current ii ssss, injected filter current ii ffff, DC-link capacitor voltages vv dddd and vv dddd2, DClink currents II and II 2, by utilising conventional and proposed controllers, respectively. It is observed that ii ssss waveform employing SWFA based controller is pure sinusoidal and in-phase with vv aa. However, the waveform of ii ssss with LPF based controller is not purely sinusoidal that still contains some amount of harmonics. The voltage control loop maintains a constant voltage across the DC-link capacitors with an average value of 65 V in each case. However, there is a minor ripple of ±2 V using the proposed controller as compared to ±3 V as obtained by applying the conventional. The magnitude of II exactly equals to zero that indicates both capacitors share equal voltages. The APF losses are mainly compensated by II 2. 36

164 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Va (Volt) (a) ila (Amp) isa (Amp) isa (Amp) (b) (c) (d) ifa (Amp) ifa (Amp) Vdc (Volt) Vdc (Volt) Vdc2 (Volt) Vdc2 (Volt) Fig. 5.5: Steady-state performance of HPF using LPF and SWFA based extraction methods. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) and (d) Source current ii ssss with conventional and proposed controllers respectively. (e) and (f) HPF current ii ffff with conventional and proposed controllers respectively. (g) and (h) DC-link capacitor voltage vv dddd with conventional and proposed controllers respectively. (i) and (j) DC-link capacitor voltage vv dddd2 with conventional and proposed controllers respectively. 37 (e) (f) (g) (h) (i) (j)

165 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Ido (Amp) Ido (Amp) Ido2 (Amp) Ido2 (Amp) Fig. 5.5: Continued. (k) and (l) DC balance current II with conventional and proposed controllers respectively. (m) and (n) DC loss current II 2 with conventional and proposed controllers respectively. (k) (l) (m) (n) isd (Amp) isd,dc (Amp) isd,dc (Amp) isq,dc (Amp) isq (Amp) (a) (b) (c) (d) (e) isq,dc (Amp) Fig. 5.6: Response of HPF under steady-state. (a) d-axis transformed source current (ii ssss ). (b) and (c) d- axis fundamental DC current (ii ssss,dddd ) with conventional and proposed controllers respectively. (d) q-axis transformed source current (ii ssss ). (e) and (f) q-axis fundamental DC current (ii ssss,dddd ) with conventional and proposed controllers respectively. 38 (f)

166 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS The waveforms of d- and q-axis source currents {ii ssss, ii ssss } and its corresponding DC components ii ssss,dddd, ii ssss,dddd employing both conventional LPF and proposed SWFA filtering methods are depicted in Figs. 5.6(a)-(f). From Figs. 5.6(b) and (e), it is clearly observed that due to the poor filtering characteristics of the first order LPF, some amount of AC components (i.e. harmonic currents) still present. These measured DC currents are oscillating in between (58.79 A to 59.4 A) and (3.6 A to 3.5 A), respectively. However, it is evident from Figs 5.6(c) and (f) that the SWFA based filtering approach allows the DC component and blocks the AC components in the desired manner. The values of ii ssss,dddd, ii ssss,dddd are calculated as A and 2.8 A, respectively. Figs. 5.7(a)-(i) depict the instantaneous active power PP, reactive power QQ and power factor on the load and source sides by applying both compensation techniques. It is observed from these plots that the waveforms of PP LL, QQ LL and load power factor are highly fluctuating. These parameters oscillate in the range of (87.6 kw to 27.8 kw), ( 8.82 kvar to kvar) and (.862 to ), respectively. By employing LPF based conventional compensation technique, there is a little fluctuation in PP ss, QQ ss and power factor with a range of (95.4 kw to 8 kw), ( 4.6 kvar to 3 kvar) and (.99 to ), respectively. On the other hand, the PP ss, QQ ss and source power factor are well maintained of constant values 8 kw, 6 kvar and.999, respectively by applying the proposed controller. It is seen that both the controllers compensate QQ ss effectively to achieve the source power factor near unity. PL (Watt) Ps (Watt) Ps (Watt).5 x x x (a) (b) (c) Fig. 5.7: Response of HPF under steady-state. (a) Instantaneous active power PP LL on the load side. (b) and (c) Instantaneous active power PP SS on source side with conventional and proposed controllers respectively. 39

167 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS QL (Var) Qs (Var) Qs (Var) Magnitude Magnitude Magnitude 4 68 x x x (d) (e) (f) (g) (h) (i) Fig. 5.7: Continued. (d) Instantaneous reactive power QQ LL on load side. (e) and (f) Instantaneous reactive power QQ SS on source side with conventional and proposed controllers respectively. (g) Power factor on the load side. (h) and (i) Power factor on source side with conventional and proposed controllers respectively. Mag (% of Fundamental) Mag (% of Fundamental) 3 2 Fundamental (5Hz) = 5.7, THD= 25.44% Harmonic order 3 2 Fundamental (5Hz) = 48.22, THD= 6.4% Harmonic order (a) (b) Fig. 5.8: Harmonic spectra. (a) Load current ii LLLL. (b) Source current ii ssss with conventional controller. 4

168 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Mag (% of Fundamental) 3 2 Fundamental (5Hz) = 48.2, THD= 2.85% Harmonic order (c) Fig. 5.8: Continued. (c) Source current ii ssss with proposed controller. Fig. 5.8 exhibits the harmonic distortion of load current ii LLLL and source current ii ssss in a system. Fig. 5.8(a) shows the THD of ii LLLL is found to be 25.44%. By employing both LPF and SWFA based compensation strategy as shown in Figs. 5.8(b) and (c) respectively, the corresponding THD values of ii ssss are scaled down to 6.4% and 2.85%. It is evident that the proposed controller suppresses the harmonics significantly, i.e. below IEEE 59:992 standard. Using the parameter estimation technique, one can easily analyze the exact characteristic of any harmonic component. A graphical comparison of amplitude estimation for fundamental, 5 tth, 7 tth, tth and 3 tth harmonics of load current ii LLLL and source current ii ssss is obtained by employing conventional ADALINE-RLS and proposed ADALINE-DFFRLS algorithms as shown in Fig The figures in the left column represent the estimated amplitude of individual harmonic component from the uncompensated source current (i.e. load current ii LLLL ), whereas, the estimation of the compensated source current ii ssss is depicted in the right column. From figures, it is clearly observed that HPF with proposed controller suppresses the harmonic magnitudes of ii ssss effectively. Similarly, a comparative analysis of phase estimation for fundamental along with major harmonics of ii LLLL and ii ssss are shown in Fig. 5.. Both the algorithms are tested under steady-state with zero noise condition. Thus the overall performance of estimation using both the algorithms is almost similar. However, the proposed algorithm exhibits slightly faster convergence than the conventional algorithm. The ADALINE-RLS algorithm attains the steady-state reference value after.8 s, whereas ADALINE-DFFRLS algorithm attains the same value within.5 s, i.e. less than one-fourth of the fundamental period. 4

169 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS 8 Estimated fundamental amplitude ADALINE-RLS ADALINE-DFFRLS 8 Estimated fundamental amplitude ADALINE-RLS ADALINE-DFFRLS ila (Amp) 6 4 isa (Amp) Estimated 5th harmonic amplitude ADALINE-RLS ADALINE-DFFRLS Estimated 5th harmonic amplitude ADALINE-RLS ADALINE-DFFRLS ila (Amp) 3 2 isa (Amp) Estimated 7th harmonic amplitude ADALINE-RLS ADALINE-DFFRLS Estimated 7th harmonic amplitude ADALINE-RLS ADALINE-DFFRLS ila (Amp) ila (Amp) Estimated th harmonic amplitude Estimated 3th harmonic amplitude ADALINE-RLS ADALINE-DFFRLS ADALINE-RLS ADALINE-DFFRLS isa (Amp) isa (Amp) Estimated th harmonic amplitude ADALINE-RLS ADALINE-DFFRLS Estimated 3th harmonic amplitude ADALINE-RLS ADALINE-DFFRLS ila (Amp) 3 2 isa (Amp) Fig. 5.9: Estimated amplitudes of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column), by using ADALINE-RLS and ADALINE-DFFRLS estimation algorithms. 42

170 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS 5 Estimated fundamental phase ADALINE-RLS ADALINE-DFFRLS 5 Estimated fundamental phase ADALINE-RLS ADALINE-DFFRLS ila (Deg) isa (Deg) Estimated 5th harmonic phase ADALINE-RLS ADALINE-DFFRLS Estimated 5th harmonic phase ADALINE-RLS ADALINE-DFFRLS 5 ila (Deg) isa (Deg) Estimated 7th harmonic phase ADALINE-RLS ADALINE-DFFRLS Estimated 7th harmonic phase ADALINE-RLS ADALINE-DFFRLS 5 ila (Deg) isa (Deg) Estimated th harmonic phase ADALINE-RLS ADALINE-DFFRLS Estimated th harmonic phase ADALINE-RLS ADALINE-DFFRLS 5 ila (Deg) isa (Deg) Estimated 3th harmonic phase ADALINE-RLS ADALINE-DFFRLS Estimated 3th harmonic phase ADALINE-RLS ADALINE-DFFRLS 5 ila (Deg) isa (Deg) Fig. 5.: Estimated phases of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column), by using ADALINE-RLS and ADALINE-DFFRLS estimation algorithms. 43

171 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Transient performance of HPF in a system with variation of load In this section, the dynamic performance of the conventional and proposed controller with HPF system is investigated under nonlinear load variation. To facilitate the load dynamics as shown in Figs. 5.(a)-(w), the nonlinear load current is subjected to % step increase at tt =.4 s and remains the same till tt =.5 s. Then it comes back to the nominal load current. It can be noticed that the source current ii ssss follows the change of load current ii LLLL. The DC-link capacitor voltages vv dddd and vv dddd2 fluctuate when ii LLLL is either increased or decreased. Additionally, both ii ssss and vv dddd exhibit fast transient response and stable operation at the instant of load change. When ii LLLL is increased (decreased), vv dddd and vv dddd2 decreases (increases) to compensate the additional real power supplied by the source. vv dddd and vv dddd2 have equal undershoots of 44 V (i.e. 2.72%) and 43 V (i.e. 3.33%) respectively, and their corresponding overshoot values are 2 V (i.e %) and 24 V (i.e %) under the following step increase and decrease of load current. The DC current II balances the DC voltages vv dddd and vv dddd2 equally at the time of load change. During.4 s tt <.5 s, the magnitude of active power PP and reactive power QQ on both source and load sides are increased due to the increase of load current. However, the system power factor remains unchanged and maintains to near unity. The dynamic performance of both the control strategies found to be satisfactory and the steady-state condition is achieved within one fundamental period (i.e. 2 ms). Va (Volt) ila (Amp) isa (Amp) (a) (b) (c) Fig. 5.: Transient performance of HPF to a % increase in load current during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss with conventional controller. 44

172 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS isa (Amp) ifa (Amp) ifa (Amp) (d) (e) (f) Ido2 (Amp) Ido (Amp) Ido (Amp) Vdc2 (Volt) Vdc2 (Volt) Vdc (Volt) Vdc (Volt) (g) (h) (i) (j) (k) (l) (m) Fig. 5.: Continued. (d) Source current ii ssss with proposed controller. (e) and (f) HPF current ii ffff with conventional and proposed controllers respectively. (g) and (h) DC-link capacitor voltage vv dddd with conventional and proposed controllers respectively. (i) and (j) DC-link capacitor voltage vv dddd2 with conventional and proposed controllers respectively. (k) and (l) DC balance current II with conventional and proposed controllers respectively. (m) DC loss current II 2 with conventional controller. 45

173 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Ido2 (Amp) x 5 PL (Watt) Ps (Watt) Ps (Watt) QL (Var) Qs (var) Qs (Var) Magnitude Magnitude Magnitude x x x x x Fig. 5.: Continued. (n) DC loss current II 2 with proposed controller. (o) Instantaneous active power PP LL on load side. (p) and (q) Instantaneous active power PP SS on source side with conventional and proposed controllers respectively. (r) Instantaneous reactive power QQ LL on load side. (s) and (t) Instantaneous reactive power QQ SS on source side with conventional and proposed controllers respectively. (u) Power factor on load side. (v) and (w) Power factor on source side with conventional and proposed controllers. 46 (n) (o) (p) (q) (r) (s) (t) (u) (v) (w)

174 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Mag (% of Fundamental) Mag (% of Fundamental) Mag (% of Fundamental) Fundamental (5Hz) = 95.67, THD= 8.26% Harmonic order Fundamental (5Hz) = 89.9, THD= 4.8% Harmonic order Fundamental (5Hz) = 89.8, THD= 2.6% Harmonic order (a) (b) (c) Fig. 5.2: Harmonic spectra. (a) Load current ii LLLL. (b) and (c) Source current ii ssss with conventional and proposed controllers, respectively. In addition, the THD values of ii ssss after reaching the steady-state are 4.8% and 2.6% as obtained in Fig. 5.2 using conventional and proposed compensation techniques respectively. The THD values are comparatively reduced because of increased load current Transient performance of HPF in a system with a temporary disconnection of load In this section, the performance of the HPF with proposed controller is tested under a realistic example of load disconnection and the associated waveforms are shown in Figs. 5.3(a)-(n). In this study, a three level variation such as nominal load (i.e. CC LL = 5 μf, RR LL = 5 Ω) during.3 ss tt <.4 ss, no-load (i.e. i.e. CC LL = μf, RR LL = Ω) during.4 ss tt <.5 ss and regain to nominal during.5 ss tt <.6 ss is considered. When the load is switched off at tt =.4 s, the passive filter provides a path for current flow from the inverter to source or vice-versa. Under this condition, ii LLLL = A, ii ssss = ii ffff = 2.2 A, PP ss = PP LL = W, QQ LL = Var and QQ ss = 44.5 kvar. 47

175 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS ifa (Amp) isa (Amp) ila (Amp) Va (Volt) (a) (b) (c) (d) Ido2 (Amp) Ido (Amp) Vdc2 (Volt) Vdc (Volt) (e) (f) (g) (h) Ps (Watt) PL (Watt) 2 x x (i) (j) Fig. 5.3: Response of HPF under temporarily disconnected load during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) and (f) DC-link capacitor voltages vv dddd and vv dddd2, respectively. (g) DC balance current II. (h) DC loss current II 2. (i) Instantaneous active power PP LL on load side. (j) Instantaneous active power PP SS on source side. 48

176 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS QL (Var) Qs (Var) Magnitude Magnitude x x (k) (l) (m) (n) Fig. 5.3: Continued. (k) Instantaneous reactive power QQ LL on load side. (l) Instantaneous reactive power QQ SS on source side. (m) Power factor on load side. (n) Power factor on source side. The DC-link capacitor voltages vv dddd and vv dddd2 are well regulated, and reach to the reference value within 4 ms. The waveforms of vv dddd and vv dddd2 show equal over-shoot of 2 V (i.e. 2.2%) when the load is removed and an under-shoot voltage of 2 V (i.e %) with the re-application of nominal load. The load change does not produce any other undesirable behaviour and the proposed controller manages this transient situation effectively Response of HPF with a voltage sag Figs. 5.4(a)-(n) show the compensation capability of the HPF system under voltage sag. The supply voltages are subjected to 33.33% of dip (i.e. from.5 kv to kv) at tt =.4 s and persist till tt =.5 s. The ii ssss became distorted for a period of 3 ms from the occurrence of sudden voltage change. After the training period, it attains almost sinusoidal and its THD is 3.%. It is observed from figures that the settling times for vv dddd, vv dddd2, PP SS, QQ SS and source power factor under this test case are equal, i.e. 4 ms. vv dddd and vv dddd2 are well regulated with a 33 V reference DC supply by the voltage control loop. A minor ripple of V occurs in these DC-link voltages. During.4 ss tt <.5 ss, PP ss is reduced from (8 kw to 48 kw) and QQ ss is decreased from ( 6 kvar to 3 kvar), but the power factor on the source side still maintained near unity value. 49

177 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Va (Volt) ila (Amp) isa (Amp) ifa (Amp) (a) (b) (c) (d) Ido2 (Amp) Ido (Amp) Vdc2 (Volt) Vdc (Volt) (e) (f) (g) (h) PL (Watt) Ps (Watt) 3 x x (i) (j) Fig. 5.4: Transient performances of HPF under supply voltage sag during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) and (f) DC-link capacitor voltages vv dddd and vv dddd2, respectively. (g) DC balance current II. (h) DC loss current II 2. (i) Instantaneous active power PP LL on load side. (j) Instantaneous active power PP SS on source side. 5

178 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS QL (Var) Qs (Var) Magnitude Magnitude 2 x x (k) (l) (m) (n) Fig. 5.4: Continued. (k) Instantaneous reactive power QQ LL on load side. (l) Instantaneous reactive power QQ SS on source side. (m) Power factor on load side. (n) Power factor on source side Response of HPF with a step change of DC-link reference voltage In this test case, the performance of the HPF with SWFA based controller is evaluated under a step change of DC-link reference voltage as shown in Figs. 5(a)-(n). This test case is achieved by increasing the reference value of the DC-link voltage from 33 V to 53 V at tt =.4 s and it comes back to the initial reference value at tt =.5 s. It is observed that the DC-link voltages vv dddd and vv dddd2 change towards their new set points (i.e. 265 V for.4 s tt <.5 s) within 3 ms. vv dddd and vv dddd2 have overshoots of 36 V (i.e. 5.47%) and 38 V (i.e. 6.22%) respectively, and corresponding undershoots are 3 V (i.e. 2.6%) and 33 V (i.e. 9.39%) under the following step increase and decrease of DC-link reference value. The current II balances vv dddd and vv dddd2 equally at the time of step change. During.4 s tt <.5 s, the values of PP ss, QQ ss and power factor remain unchanged. The waveform of ii ssss is slightly affected for one cycle after the instant of transition. The percentage of THD associated with ii ssss is found to be 3.29%. The results strongly confirm the efficacy of proposed SWFA control technique in eliminating the presence of harmonics, compensating the reactive currents and maintaining the DC-link capacitor voltages for an HPF application. 5

179 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Va (Volt) ila (Amp) isa (Amp) ifa (Amp) (a) (b) (c) (d) Vdc (Volt) (e) Vdc2 (Volt) Ido (Amp) Ido2 (Amp) PL (Watt) Ps (Watt) x x (f) (g) (h) (i) (j) Fig. 5.5: Transient performances of HPF under step increase in DC-link voltage during.4 s tt <.5 s. (a) Source voltage vv aa. (b) Load current ii LLLL. (c) Source current ii ssss. (d) APF current ii ffff. (e) and (f) DC-link capacitor voltages vv dddd and vv dddd2, respectively. (g) DC balance current II. (h) DC loss current II 2. (i) Instantaneous active power PP LL on load side. (j) Instantaneous active power PP SS on source side. 52

180 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS QL (Var) Qs (Var) Magnitude Magnitude x x (k) (l) (m) (n) Fig. 5.5: Continued. (k) Instantaneous reactive power QQ LL on load side. (l) Instantaneous reactive power QQ SS on source side. (m) Power factor on load side. (n) Power factor on source side. The comparative results obtained under various test cases is illustrated in Table 5.2. The THDs and fundamental peaks of source voltages, load currents and source currents of above described six test cases are presented. In test case, the three-phase source current THDs are effective reduced by employing SWFA based HPF system than the LPF based HPF system. However, the fundamental peaks of source current are equal using LPF and SWFA based controllers. It is evident from test case 2 that there is a % decrease in THDs of source currents with SWFA based controller and 2% decrease in THDs of the source current with LPF based controller as compared to the corresponding nominal values due to the increase of load current (i.e. a higher value of fundamental peak). Under the test case 3, current flows either from VSI to source or vice versa as the load is disconnected from the system and this current is maintained sinusoidal with an average THD value of 3.4%. Analyzing test cases 4 and 5, it is observed that the compensating performance of HPF with proposed SWFA based control strategy is slightly affected. In both the cases, the THDs of source currents are further increased from its nominal values. 53

181 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Table 5.2: Summary of the simulation results Test cases Supply/nonlinear load conditions Contro llers Items PCC voltages (during.4 ss < tt <.5 ss) Load currents (during.4 ss < tt <.5 ss) Source currents (during.4 ss < tt <.5 ss) Phase-a Phase-b Phase-c Phase-a Phase-b Phase-c Phase-a Phase-b Phase-c LPF Fund Peak 5 V 5 V 5 V 5.8 A 5.8 A 5.8 A A A A Sinusoidal balanced supply THD.28%.28%.28% 25.36% 25.36% 25.36% 6.4% 6.7% 5.95% with balanced nonlinear load (steady-state performance of Fund HPF) 5 V 5 V 5 V 5.7 A 5.7 A 5.7 A 48.2 A 48.7 A 48.7 A Peak SWFA THD.27%.27%.27% 25.44% 25.44% 25.44% 2.85% 2.83% 2.82% Fund 496 V 496 V 496 V 95.7 A 95.7 A 95.7 A 89.9 A 89.9 A 89.6 A Peak LPF Sinusoidal balanced supply with balanced nonlinear load THD.2%.2%.2% 8.2% 8.2% 8.2% 4.8% 4.7% 4.2% (during.4 s tt <.5 s load current is increased to Fund 496 V 496 V 496 V A A A 89.8 A 89.6 A 89.7 A %) Peak SWFA THD.5%.6%.6% 8.26% 8.27% 8.27% 2.6%.99% 2.% Sinusoidal balanced supply Fund 53 V 53 V 53 V 9.87 A 9.89 A 9.85 A with balanced nonlinear load Peak SWFA (during.4 ss tt <.5 ss load is disconnected) THD.4%.4%.4% 3.4% 3.4% 3.6% Sinusoidal balanced supply Fund with balanced nonlinear load V V V 34.8 A 34.3 A 34.2 A 32.4 A 32.6 A 32.4 A Peak (during.4 ss tt <.5 ss SWFA supply voltage is decreased THD 2.3% 2.3% 2.3% 25.38% 25.46% 25.46% 3.% 3.6% 3.% by 33.33%) Sinusoidal balanced supply Fund with balanced nonlinear load 5 V 5 V 5 V 5.6 A 5.6 A 5.6 A 48.5 A 48.3 A 48.5 A Peak (during.4 ss tt <.5 ss SWFA DC-link reference voltage is THD 2.6% 2.6% 2.6% 25.47% 25.47% 25.46% 3.29% 3.24% 3.3% increased to 6%) 5.6 Experimental results To verify the effectiveness of the proposed control strategy, a prototype has been developed using a SPARTAN-3A XC3SD8A DSP processor and tested in the laboratory. The design parameters are specified in Table 5.3. The device parameters used in the experimental setup are scaled down to low rated values. The test model is fed from a regulated power supply through an autotransformer. An SKKD /6 diode bridge rectifier with inductive load acts as a nonlinear load in a system and an IGBT module PM25RSB2 three-leg VSI is considered as APF. Two DC-link electrolytic capacitors of rating 22 μf and 25 V are connected in series that yields a total DClink capacitance of. mf with 5 V. The three-phase current and voltage signals are sensed using LEM LTS25-NP current and LEM LV25-P voltage sensors respectively. 54

182 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS Table 5.3: List of parameters used in experimental tests System quantities Parameters Symbol Values Supply voltages (line to neutral) VV ss 9 V Source System frequency ωω ππ rad/s Supply inductors LL ss.2 mh Load Current-source type of nonlinear load RR LL, LL LL 5 Ω, 36 mh VSI Passive filters Voltage control loop DC-link capacitors CC dddd = CC dddd2 22 μf DC-link capacitor voltage VV rrrrrr 4 V Switching frequency ωω ss 2ππ rad/s Filter inductors LL pp.5 mh Filter capacitors CC pp 4 μf Proportional gains KK PP = KK PP2.2 Ω - Integral gains KK II = KK II2 2 Ω - s - After sensing, these signals are applied to the SPARTAN-3A DSP board via ADC. The proposed control algorithm for extraction of reference signals and modulation technique for generation of switching pulses are implemented in the DSP processor using very high speed integrated circuit hardware description language (VHDL). The current measurement equipment utilizes Tektronix TCPA3 current amplifier with the Tektronix TCPA33 current probe. The measured current and voltage waveforms are sampled and stored in a Tektronix TPS224B DSO. The sampling frequency of the current probe, current amplifier and DSO are set to be 25 khz. The values of constant parameters, upper and lower level of truncation operator are same as simulation test as outlined in Table Response of HPF under steady-state Figs. 6(a) and (b) show the comparative experimental waveforms employing LPF based conventional and SWFA based proposed filtering approaches under steady-state condition. The top-to-bottom waveforms in each figure indicate source voltage vv aa, source current ii ssss, load current ii LLLL and compensating current ii ffff of phase-a respectively. It can be observed that ii ssss is compensated effectively using SWFA based controller and almost pure sinusoidal than the conventional method. However, both the controllers show zero degree phase shift between ii ssss and vv aa. Power factor on the load is about.84. As seen, the power factors on source side rise to.95 and.93 by employing SWFA and LPF based extraction scheme respectively. vv dddd and vv dddd2 are 55

183 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS (a) (b) Fig. 5.6: Experimental waveforms from top-to-bottom in each figure shows source voltage vv aa, source current ii ssss, load current ii LLLL and compensating currents ii ffff (X axis =. s/div). (a) Response of HPF under steady-state with 2 kw load by employing conventional controller. (b) Response of HPF under steady-state with 2 kw load by employing proposed controller ila (Amp) (a) isa (Amp) (b) isa (Amp) (c) Harmonic order Harmonic order Harmonic order Fig. 5.7: Harmonic spectrum of currents. (a) Load current (ii LLLL ). (b) and (c) Source current (ii ssss ) with conventional and proposed controller, respectively. adequately controlled around its half of the DC-link reference value with a minor ripple (i.e. V and 2 V using proposed and conventional control techniques respectively). The harmonic spectrum of ii LLLL and ii ssss employing conventional and proposed controllers as obtained from an experimental setup are depicted in Figs. 5.7(a)-(c). The THD of ii LLLL is found to be 38.9%. However, THDs of ii ssss utilizing conventional and proposed controllers are reduced to 6.5% and 3.2% respectively. From results, it is concluded that SWFA based filtering method suppresses the harmonic components adequately than the LPF based filtering approach. The waveforms of distorted load current ii LLLL and SWFA based compensated source current ii ssaa contain fundamental, harmonics and additive noise. The estimation of ii LLLL and ii ssss employing conventional ADALINE-RLS and proposed ADALINE- DFFRLS algorithms evaluate the compensation effect. The amplitude estimation using both the algorithms is shown in Fig In addition, the phase estimation of ii LLLL and ii ssss using above mentioned algorithms is shown in Fig In both the figures, the left 56

184 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS 2.5 Estimated fundamental amplitude 2.5 Estimated fundamental amplitude 2 2 ila (Amp).5 isa (Amp).5.5 ADALINE-RLS ADALINE-DFFRLS Estimated 5th harmonic amplitude.4 ADALINE-RLS ADALINE-DFFRLS.3.5 ADALINE-RLS ADALINE-DFFRLS Estimated 5th harmonic amplitude.4 ADALINE-RLS ADALINE-DFFRLS.3 ila (Amp).2 isa (Amp) Estimated 7th harmonic amplitude.4 ADALINE-RLS ADALINE-DFFRLS Estimated 7th harmonic amplitude.4 ADALINE-RLS ADALINE-DFFRLS.3 ila (Amp).2 isa (Amp) Estimated th harmonic amplitude.4 ADALINE-RLS ADALINE-DFFRLS Estimated th harmonic amplitude.2 ADALINE-RLS ADALINE-DFFRLS.5 ila (Amp).2 isa (Amp) Estimated 3th harmonic amplitude.2 ADALINE-RLS ADALINE-DFFRLS Estimated 3th harmonic amplitude.2 ADALINE-RLS ADALINE-DFFRLS.5 ila (Amp). isa (Amp) Fig. 5.8: Experimental waveforms of amplitude estimation of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column) by using conventional ADALINE-RLS and proposed ADALINE-DFFRLS algorithms. 57

185 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS 5 Estimated fundamental phase ADALINE-RLS ADALINE-DFFRLS 5 Estimated fundamental phase ADALINE-RLS ADALINE-DFFRLS ila (Deg) isa (Deg) Estimated 5th harmonic phase ADALINE-RLS ADALINE-DFFRLS Estimated 5th harmonic phase ADALINE-RLS ADALINE-DFFRLS ila (Deg) isa (Deg) Estimated 7th harmonic phase ADALINE-RLS ADALINE-DFFRLS Estimated 7th harmonic phase ila (Deg) isa (Deg) Estimated th harmonic phase ADALINE-RLS ADALINE-DFFRLS -5 ADALINE-RLS ADALINE-DFFRLS Estimated th harmonic phase ADALINE-RLS ADALINE-DFFRLS 5 ila (Deg) isa (Deg) Estimated 3th harmonic phase ADALINE-RLS ADALINE-DFFRLS Estimated 3th harmonic phase ADALINE-RLS ADALINE-DFFRLS ila (Deg) isa (Deg) Fig. 5.9: Experimental waveforms of phase estimation of load current ii LLLL (left column) and source current ii ssss with SWFA based controller (right column) by using conventional ADALINE-RLS and proposed ADALINE-DFFRLS algorithms. 58

186 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS column depicts parameter estimation of individual harmonic components present in ii LLLL and right column depicts harmonic parameter present in ii ssss. As seen from the figures, the estimation employing ADALINE-DFFRLS algorithm is least affected in the presence of additive noise produced from the hardware model. The tracking time for estimation utilizing the proposed algorithm is. s, i.e. half of the fundamental period. However, estimation based on the ADALINE-RLS algorithm suffers from oscillation before achieving the steady-state value. This algorithm takes.2 s, i.e. one fundamental period to attain the original value. Here estimation is performed only for few dominant harmonics. In a similar manner, estimation can be performed for remaining harmonics present in the waveforms of ii LLLL and ii ssss Response of HPF under transient Figs. 5.2(a) and (c) show the dynamic compensating performance of HPF with conventional controller under increase and decrease of load current ii LLLL respectively. It is observed from figures that there is a significant distortion in the source current ii ssss (a) (b) (c) (d) Fig. 5.2: Experimental results from top-to-bottom in each figure shows source voltage vv aa, source current ii ssss, load current ii LLLL and compensating currents ii ffff (X axis =. s/div). (a) Load increases from kw to 2 kw by employing conventional controller (b) Load increases from kw to 2 kw by employing proposed controller (c) Load decreases from 2 kw to kw by employing conventional controller (d) Load decreases from 2 kw to kw by employing proposed controller. 59

187 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS waveform and it attains the steady-state value within.4 ms from the instant of load change. Whereas Figs. 5.2(b) and (d) represent the response of the HPF employing SWFA approach under increase and decrease of load current respectively. It is evident from the figures that ii ssss adapts to the sudden increase/decrease of ii LLLL, and catches steady-state value within one fundamental cycle. 5.7 Chapter summary In this chapter, elimination of harmonics along with an evaluation of compensation effect is presented. A low rated, low voltage stress and small size novel DC-link capacitor midpoint HPF topology is designed for the effective compensation of harmonics and reactive currents. An SWFA based low pass filtering approach is applied to provide fast DC-link voltage regulation as well as evaluate the reference signal under various operating conditions. It is evident from simulation and experimental results that the dynamic compensation by HPF with proposed SWFA approach is superior as compared to the conventional LPF approach. The exact timevarying amplitude and phase of the fundamental and major harmonics of the load and source currents are determined by utilizing combinational ADALINE and recursive algorithms. It is noticeable that the estimation employing proposed ADALINE- DFFRLS algorithm is more accurate and faster in convergence than the conventional ADALINE-RLS algorithm based estimation. For power quality assessment and its improvement, the proposed HPF topology is a cost effective solution for mediumvoltage applications. The dynamic compensation using either shunt APF or HPF is described in subsequent chapters of 3, 4 and 5. The overall comparative compensation performance is illustrated in Table 5.4. By employing shunt APF based compensation in a system with supply voltage of 23 V, the required DC-link capacitor voltage (i.e. 66 V) is nearly three times of supply voltage, which is very high. This compensation approach is suitable for low-voltage applications. The compensation based on shunt HPF topology as described in chapter 4, the required DC-link capacitor voltage is approximately onefourth of the supply voltage. Considering 4 V supply system, the required DC-link voltage is 2 V, which is very less as compared to shunt APF. Thus this filtering topology can be implemented easily in low- and medium-voltage applications. In 6

188 Chapter 5: Harmonic elimination using HPF and estimation using ADALINE-DFFRLS addition, the midpoint DC-link capacitor concept is introduced in the previous shunt HPF topology to reduce the voltage further across each capacitor (i.e. reduced to oneeighth of supply voltage). Thus the voltage stress of each IGBT is reduced to half as compared to previous shunt HPF topology. The compensation based on this topology is more effective for medium- and high-voltage applications. It is also observed from simulation results under similar test cases that the THD of source current reduces to 5% using shunt APF topology. Whereas other two topologies show equal compensation, i.e. the THD of 2%. Table 5.4: Comparative performance analysis of three APF topologies Power filter topologies AC supply Required DC-link capacitor voltage Voltage stress of each IGBT Current-source type of nonlinear load THD of load current THD of source current Utilization Shunt APF 23 V 66 V 66 V 25.27% 5.4% Low-voltage Shunt HPF 4 V 2 V 2 V 23.8% 2.8% Low- and mediumvoltages Midpoint DC-link capacitor HPF.5 kv 65 V 65 V 25.44% 2.85% Medium- and high-voltages 6

189 Chapter 6 Conclusions and Future Work 6. Conclusions This thesis has investigated the power quality assessment and its enhancement in a distribution power system network by developing an effective filtering scheme with accurate harmonic estimation. The research effort is made to develop an innovative harmonic estimation using ADALINE-FXLMS. For improving the power quality of a system under different critical conditions, three different APF topologies, i.e. shunt APF, shunt HPF and midpoint DC-link capacitor HPF are proposed in this thesis. For effective control and operation of these topologies, the corresponding adopted novel detection techniques are nonlinear control, ADALINE-VLLMS algorithm and SWFA based filtering scheme. The specific contributions of this study are summarized as below. For fast and accurate estimation of harmonic parameters, a hybrid algorithm using ADALINE-FXLMS is employed. During estimation, the step size parameter can also be increased to the upper-bound limit without affecting the system stability. Moreover, the proposed algorithm is solid and robust to assess the distorted signal added with sub-harmonics, inter-harmonics, time-varying signal and decaying DC component. The overall simulation and experimental results have demonstrated 62

190 Chapter 6: Conclusions that the proposed ADALINE-FXLMS estimation algorithm is superior and more effective as compared to conventional ADALINE-LMS based scheme. For low-voltage application, a shunt APF with nonlinear control scheme is preferred in regards to the compensation of harmonics and reactive currents. Additionally, a modified PWM control scheme is proposed for the generation of switching signals to trigger the IGBTs. From the simulation results, it is concluded that the shunt APF equipped with proposed control strategy performs the filtering job successfully under various scenarios. A novel ADALINE-VLLMS control algorithm is applied for efficient operation of shunt HPF in the low- and medium-voltage distribution networks to facilitate power flow control and improve power quality. In this adopted topology, the rating of APF and DC-link capacitor voltage are significantly reduced. By analysing both simulation and experimental results, it is evident that the corresponding filter module is quite capable of maintaining power quality standard of a system under different critical conditions. A midpoint capacitor shunt HPF topology using SWFA controller is proposed for the improvement of power quality in three-phase medium- and high-voltage systems. This topology is a cost-effective, low rated and low voltage stress among all three topologies. The performance of the proposed SWFA controller is also compared with the conventional LPF controller in both simulations as well as experimental studies. In addition to, the compensating performance of the proposed HPF system has been evaluated by using hybrid ADALINE-DFFRLS algorithm. The three-phase source and load currents obtained from simulation and hardware model are considered as a test signal for evaluation of time-varying amplitude and phase of the fundamental and major harmonics. For power quality assessment and its improvement, the proposed HPF scheme is a cost-effective solution for medium- and high-voltage applications. 6.2 Future work During the course of this research, the following issues have been identified and are listed here as possible topics for future work in this area. 63

191 Chapter 6: Conclusions During harmonic amplitude and phase estimation of a distorted power signal, the fundamental frequency is considered as constant (i.e. 5 Hz). However, the results may be inaccurate in a system with time-varying fundamental frequency. The accurate estimation of harmonic components can be obtained by incorporating this variation in the model. For sustainable growth in power systems, recently renewable energy sources are gaining a lot of attention. These energy sources feeding nonlinear loads can be taken up as a further investigation in the field of power quality. Multilevel inverters can be an alternative choice especially in medium- and highvoltage applications. For further research, it would be interesting to examine whether it is worthwhile and cost-effective to develop APF configuration using multilevel inverter. Reactive power compensation and harmonic elimination using APF scheme need different requirements from the frequency of operation of inverter perspective. Harmonic elimination requires a high-frequency low-power inverter, whereas reactive power compensation requires low-frequency high-power operations. Therefore, it is important to develop a suitable methodology such that these tasks are decoupled and compensation can be achieved by two different inverters. 64

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202 Vita Priyabrat Garanayak was born in Odisha, India, in October 987. He received his Bachelor of Technology in Electronics & Telecommunication Engineering from Biju Patnaik University of Technology, India and his Master of Technology in VLSI and Embedded System Design from the Centre for Micro Electronics, Biju Patnaik University of Technology, India, in 29 and 2, respectively. From February 23 to August 23, he worked as a lecturer in the department of Electronics & Telecommunication Engineering at Indira Gandhi Institute of Technology Sarang, Odisha, India. Priyabrat Garanayak joined the department of Electrical and Electronics Engineering at National Institute of Technology Meghalaya, India, as a Junior Research Fellow, in September 23. From January 24, he enrolled in doctoral program in the department of Electrical Engineering at the National Institute of Technology Meghalaya, India. He has submitted his doctoral thesis in July 26. He has been working as a research associate in the department of Electrical Engineering at Indian Institute of Technology Delhi, India, since August 26. His research interests are harmonic mitigation, harmonic measurement, design of active and hybrid filters, unified power quality conditioner (UPQC), series-parallel uninterruptible power supply (SP-UPS). He is a student member of Institute of Electrical and Electronics Engineers (IEEE) and member of Institution of Engineering and Technology (IET).

203 Department of Electrical Engineering National Institute of Technology Meghalaya Shillong-7933, Meghalaya, India October 26