Energy Efficient Decoder Architecture For Communication System

Transcription

1 Energy Efficient Decoder Architecture For Communication System Chandana P, Agalya P, B. N Shoba Abstract In the communication domain low complexity and low power are the main criteria to be considered for the efficient utilization of the communication channel, which also requires reduction in the error rate. Turbo codes aids the energy constrained wireless communication by providing less energy consumption during data sending and receiving operation. In this paper, we are breaking down the LUT-Log-BCJR architecture into most fundamental add compare select unit and perform them using novel low complexity ACS unit, since we are using ACS unit with LUT architecture it employs an order of magnitude of fewer gates than previous LUT-log_BCJR architecture, providing approximately 72% energy consumption reduction compared to existing previous max log algorithm. Index Terms Energy-efficient, error-correcting code (ECC), LUT-Log-BCJR algorithm, turbo code. I. INTRODUCTION MODERN wireless communication standards rely on powerful channel coding to ensure reliable (error free) transmission. Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, look up table-log-bcjr (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental add compare select (ACS) operations and perform them using a novel low-complexity ACS unit. II. RELATED WORK Recent application-specific integrated circuit (ASIC) based turbo decoder architectures [5] [7] have been designed for achieving a high transmission throughput, rather than for a low transmission energy. Manuscript received April, Chandana P, is currently pursuing Masters degree program in VLSI and ES at Sapthagiri college of Engineering, Bengaluru, Karnataka,affiliated to VTU. Agalya P, Associate professor, Dept. of Electronic and Communication Engineering, Sapthagiri college of Engineering, Bengaluru, Karnataka. Shoba B N, Associate professor, Dept. of Electronic and Communication Engineering, Sapthagiri college of Engineering, Bengaluru, Karnataka For example, turbo codes have facilitated transmission throughputs in excess of 50 Mbit/s in cellular standards, such as the 3rd Generation Partnership Project 3GPP Long Term Evolution (LTE) and recent ASIC turbo decoder architectures have been designed for throughputs that are in excess of 100 Mbit/s [5], [6]. This has been achieved by employing the Max Log - BCJR turbo decoding algorithm, which is a low-complexity approximation of the optimal Logarithmic Bahl-Cocke-Jelinek-Raviv (Log-BCJR) algorithm [8]. The Max-Log-BCJR algorithm appears to lend itself to both high-throughput scenarios, as well as to the above-mentioned energy-constrained scenarios. This is because a low turbo decoder energy consumption is implied by Max-Log-BCJR algorithm s low complexity. However, this is achieved at the cost of degrading the coding gain by 0.5 db compared to the optimal Log-BCJR algorithm [9], increasing the required transmission energy by 10%. This disadvantage of the Max-Log-BCJR outweighs its attractively low complexity, when optimizing the overall energy consumption of sensor nodes that are separated by dozens of meters. This motivates the employment of the lookup-table-log- BCJR (LUT-Log-BCJR) algorithm [8] in energy-constrained scenarios, since it approximates the optimal Log-BCJR more closely than the Max-Log-BCJR and therefore does not suffer from the associated coding gain degradation. However, to the best of our knowledge, no LUT-Log-BCJR ASICs have been specifically designed for energy-constrained scenarios. Previous LUT-Log-BCJR turbo decoder designs [10] [13] were developed as a part of the on-going drive for higher and higher processing throughputs, although their throughputs have since been eclipsed by the Max-Log-BCJR architectures. This opens the door for a new generation of LUT-Log-BCJR ASICs that exchange processing throughput for energy efficiency. The energy consumption of conventional LUT-Log-BCJR architectures cannot be significantly reduced by simply reducing their clock frequency and throughput. This motivates our novel architecture of, which is specifically designed to have a minimal hardware complexity and hence a low energy consumption. we validate our architecture in the context of an LTE turbo decoder and demonstrate that it has an order of magnitude lower chip area, hence reducing the energy consumption of the state-of-the-art LUT-Log-BCJR implementation by approximately 72%. Compared to state-of-the-art Max-Log-BCJR implementations, our approach facilitates approximately 10% reduction in the overall energy consumption of at transmission ranges above 58 m. 1117

2 III. PROPOSED SYSTEM The lookup-table-log-bcjr (LUT-Log-BCJR) algorithm is useful in energy-constrained scenarios, since it approximates the optimal Log-BCJR more closely than the Max-Log-BCJR and therefore does not suffer from the associated coding gain degradation. We validate our architecture and demonstrate that it has an order of magnitude of lower chip area, hence reducing the energy consumption of the state-of-the-art LUT-Log-BCJR implementation by 72%. We can keep on changing the architecture of lookup-table-log-bcr to achieve an efficient frequency which in turn helps in Power Consumption. Fig 1.Turbo encoder and decoder scheme Fig.3.Recursive Systematic Coder\RSC These codes are very similar in nature to conventional convolutional codes, also called nonsystematic convolutional codes (NSC), which are commonly used for 2G cellular systems, data modems, satellite communications, and many other applications. Data {Xi} enter from the left and are stored in a linear shift register (D denotes a D flip-flop). Each time a new data bit arrives, the data is shifted to the right into the next flip-flop. Each of the tw output bits {Z1,i,Z2,i} is computed by XOR-ing a particular subset of the three bits stored in the shift register with the bit at the encoder s input. The systematic outputs are not needed because they are identical to each other (although ordered differently) and to the turbo code input (which becomes the systematic part of the overall turbo code word). Fig 2. Encoder Block Diagram One of the most interesting characteristics of a turbo code is that it is not just a single code. It is, in fact, a combination of two codes1 that work together to achieve a synergy that would not be possible by merely using one code by itself. In particular, a turbo code is formed from the parallel concatenation of two constituent codes separated by an interleaver. Each constituent code may be any type of FEC code used for conventional. The interleaver is a critical part of the turbo code. It is a simple device that rearranges the order f the data bits in a prescribed, but irregular, manner. Although the same set of data bits is present at the output of the interleaver, the order of these bits has been changed, much like a 1Turbo codes can also be constructed using three or more constituent codes. Such structures are called multiple turbo codes. However, they are not used in any standards and are therefore not discussed here. Fig 4. Energy-efficient LUT-Log-BCJR architecture Our architecture implements the entire algorithm using ACS units in parallel, each of which performs one ACS operation per clock cycle. Furthermore, the proposed architecture employs a twin-level register structure to minimize the highly energy-consuming main-memory access operations. At the first register level, each ACS unit is paired with a set of general purpose registers R1, R2, and R3. These are used to store intermediate results that are required by the same ACS unit in consecutive clock cycles. For example, this allows the four ACS operations equivalent to a calculation to be performed in four consecutive clock cycles using a single ACS unit, as Fig.4. Energy-efficient LUT-Log-BCJR architecture. The second register level comprises REG bank 1 and REG bank 2 of Fig. 4, which are used to temporarily store the LUT-Log-BCJR variables between consecutive values of the bit index during the 1118

3 recursions decoding processes. The REG bank 1 comprises registers for input variables C 1, C 3. Meanwhile, the sets of input C 3, C 2 are stored in REG bank 2 of Fig. 4. The main memory stores all the calculated ACS outputs for the decoding process. Since the proposed architecture supports a fully parallel arrangement of an arbitrary number of ACS units of Fig. 4, it may be readily applied to any LUT-Log- BCJR decoder, regardless of the specific convolution encoder parameters2 employed. Note that in contrast to the differentlength data paths of Fig. 2, the identical parallel data paths shown in Fig.4. have equal lengths, which avoids energy wastage, as described above. O TABLE I OPERATIONS OF THE ACS Function TABLE II COMPARISON OF THE IMPLEMENTED TURBO DECODER Fig 5. ACS Unit A. Novel ACS Unit In this section Fig.5 shows, the novel low-gate-count ACS unit, which performs one ACS operation per clock cycle. The control signals of the ACS unit are provided by the operation code O={0,1,2,3,4,5}, which can be used to perform the functions listed in Table I. The ACS unit is responsible for implementing the state metric computation. A direct implementation requires two identical data paths each with two additions, a comparison, and a selection. Op 1 In this clock cycle max * the calculation is activated by using the operation code O = of Table I and loading operands p^ and q^ from the registers R 1 and R 2 of Fig. 5, respectively. The result r^ is then stored in register R 3, which is the approximated as R 1 -R 2. The result C 0 determines max(r 1,R 2 ). Op 2 The MAX * calculation of (2) is completed in the fourth clock cycle by using the operation code O = of Table I. Here the operand P^ is provided by the maximum of R 1 and R 2, as identified by C 0 of Fig.5. Meanwhile, a value for the operand Q^ is selected from the set {0.75, 0.5,0.25,0}, depending on the contents of C 1 and C 2n of Fig. 5. As a result, we have Publication Proposed Existing Algorithm LUT-Log Max-Log Block size(bit) Area(mm 2 ) Power consumption(mw) Clock Frequency F (MHz) In Table II, we compare the proposed architecture to the latest LUT-Log-BCJR and Max-Log-BCJR decoder architectures. The area and energy consumptions E pr are estimated based on post-layout simulations. The implementation results arising from different technologies are also scaled3 to give a fair comparison. As shown in Table II, the energy consumption E pr of the proposed architecture is significantly lower than that of the conventional LUT-Log-BCJR architectures. Furthermore, our proposed architecture has a similar energy E tr consumption to that of the recent Max-Log-BCJR decoders, but facilitates a 10% lower transmission energy, as discussed in Section I. IV. SYNTHESIS RESULT The Figures Fig.6.1, Fig.6.2, Fig.6.3 and Fig.6.4 of this section are the final output waveform generated using Xilinx tool. In Fig.6.1 Encoder output waveform along with RCS and Interlever outputs are shown. In Fig.6.2 and Fig.6.3 decoder output waveform along with Upper and Lower LUT-Log BCGR outputs are shown. In Fig.6.4 de-interleved output and final result of Decoder outputs are shown. 1119

4 Fig.6.1 Synthesis output of Encoder, RCS and Interlever Blocks. Fig.6.4 Synthesis output of de-interlever and final result of Decoder outputs. Fig.6.2 Synthesis output of Decoder, Upper LUT-Log BCGR Blocks. V. CONCLUSION In this paper, we have proposed low complexity energy-efficient architecture providing low area and low energy consumption by breaking down the LUT log BCJR into its most fundamental ACS operations. In the previous existing architecture i.e conventional LUT log architecture may have wasteful design requiring high chip area leading high energy consumption, where in the proposed architecture consider different turbo codes for encoding and decoding algorithm by validating the architecture using an LTE turbo decoder, to have an order of magnitude of lower area than the existing conventional LUT-log-BCJR architecture and our proposed system provides approximately 72% lower energy consumption compared to max-log BCJR implementation. REFERENCES Fig.6.3 Synthesis output of Upper and Lower LUT-Log BCGR Blocks. [1] F. Akyildiz, W. Su, Y. Sankarasubramaniam, and E. Cayirci, Wireless sensor networks: A survey, Comput. Netw.: Int. J. Comput. Telecommun. Netw., vol. 52, pp , [2] P. Corke, T. Wark, R. Jurdak, H. Wen, P. Valencia, and D. Moore, Environmental wireless sensor networks, Proc. IEEE, vol. 98, no.11, pp , Nov [3] S. L. Howard, C. Schlegel, and K. Iniewski, Error control coding in low-power wireless sensor networks:when is ECC energy-efficient?, EURASIP J. Wirel. Commun. Netw., vol. 2006, pp. 1 14, [4] L. Li, R. G. Maunder, B. M. Al-Hashimi, and L. Hanzo, An energy-efficient error correction scheme for IEEE wireless sensor networks, Trans. Circuits Syst. II, vol. 57, no. 3, pp , [5] M.May, T. Ilnseher, N.Wehn, andw. Raab, A 150 Mbit/s 3GPP LTE turbo code decoder, in Proc. 1120

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