XR-2207 Voltage-Controlled Oscillator

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...the analog plus company TM Voltage-Controlled Oscillator FETURES Excellent Temperature Stability (20ppm/ C) Linear Frequency Sweep djustable Duty Cycle (0.% to.

1 ...the analog plus company TM Voltage-Controlled Oscillator FETURES Excellent Temperature Stability (20ppm/ C) Linear Frequency Sweep djustable Duty Cycle (0.% to.%) Two or Four Level FSK Capability Wide Sweep Range (000: Minimum) Logic Compatible Input and Levels Wide Supply Voltage Range ( 4V to V) Low Supply Sensitivity (0.% /V) Wide Frequency Range (0.0Hz to MHz) Simultaneous Triangle and Squarewave s June 7 PPLICTIONS FSK Generation Voltage and Current-to-Frequency Conversion Stable Phase-Locked Loop Waveform Generation Triangle, Sawtooth, Pulse, Squarewave FM and Sweep Generation GENERL DESCRIPTION The is a monolithic voltage-controlled oscillator (VCO) integrated circuit featuring excellent frequency stability and a wide tuning range. The circuit provides simultaneous triangle and squarewave outputs over a frequency range of 0.0Hz to MHz. It is ideally suited for FM, FSK, and sweep or tone generation, as well as for phase-locked loop applications. The has a typical drift specification of 20ppm/ C. The oscillator frequency can be linearly swept over a 000: range with an external control voltage; and the duty cycle of both the triangle and the squarewave outputs can be varied from 0.% to.% to generate stable pulse and sawtooth waveforms. ORDERING INFORMTION Operating Part No. Package Temperature Range M 4 Lead 00 Mil CDIP - C to +2 C CP 4 Lead 00 Mil PDIP 0 C to +70 C D 6 Lead 00 Mil JEDEC SOIC 0 C to +70 C ID 6 Lead 00 Mil JEDEC SOIC -40 C to + C BLOCK DIGRM Timing Capacitor C C 2 Î Î VCO BIS TWO SWO Triangle Wave Out Square Wave Out Timing Resistors R R2 R R Current Switches Figure. Block Diagram BKI2 BKI Binary Keying Inputs 7 EXR Corporation, 4720 Kato Road, Fremont, C 4 (0) FX (0)

2 PIN CONFIGURTION C C2 R R2 R R TWO SWO BIS BKI2 BKI C C2 R R2 R R4 BKI NC NC TWO SWO BIS BKI2 4 Lead PDIP, CDIP (0.00 ) 6 Lead SOIC (Jedec, 0.00 ) PIN DESCRIPTION Pin # Symbol Type Description Positive Power Supply. 2 C I Timing Capacitor Input. C2 I Timing Capacitor Input. 4 R I Timing Resistor Input. R2 I Timing Resistor 2 Input. 6 R I Timing Resistor Input. 7 R4 I Timing Resistor 4 Input. BKI I Binary Keying Timing Resistor Select Input. BKI2 I Binary Keying 2 Timing Resistor Select Input. 0 Ground Pin. BIS I Bias Input for Single Supply Operation. 2 Negative Power Supply. SWO O Square Wave Signal. 4 TWO O Triangle Wave Signal., 6 NC Only SOIC-6 Package. 2

3 ELECTRICL CHRCTERISTICS Test Conditions: Test Circuit of Figure and Figure 4, = = 6V, T = +2 C, C = 000pF, R = R 2 = R = R 4 = 20kΩ, RL = 4.7kΩ, Binary Inputs Grounded, S and S 2 Closed Unless Otherwise Specified Parameters General Characteristics Supply Voltage ID/M CP/D Min. Typ. Max. Min. Typ. Max. Units Conditions Single Supply V See Figure Split Supplies 4 4 V See Figure 4 Supply Current See Figure Single Supply 7 m Measure at Pin, S, S 2 Open Split Supply See Figure 4 Positive 7 m Measure at Pin, S, S 2 Open Negative m Measured at Pin 2, S, S 2 Open Oscillator Section - Frequency Characteristics Upper Frequency Limit MHz C =00pF, R = 2kΩ Lowest Practical Frequency Hz C =0µF, R = 2MΩ Frequency ccuracy % of f O Frequency Matching % of f O Frequency Stability Temperature ppm/ C 0 C < T < 70 C Power Supply %V Sweep Range 000: 000: 000: f H /f L R =.kω for f H R = 2MΩ for f L Sweep Linearity % C =000pF 0: Sweep 2. f H =0kHz, f L = khz 000: Sweep f H =00kHz, f L = 00Hz FM Distortion % 0% FM Deviation Recommended Range of Timing Resistors kω See Characteristic Curves Impedance at Timing Pins 7 7 Ω Measured at Pins 4,, 6, or 7 DC Level at Timing Terminals 0 0 mv Binary Keying Inputs Switching Threshold V Measured at Pins and, Referenced to Pin 0 Input Impedance kω Notes Bold face parameters are covered by production test and guaranteed over operating temperature range.

4 ELECTRICL CHRCTERISTICS (CONT D) Parameters Characteristics ID/M CP/D Min. Typ. Max. Min. Typ. Max. Units Conditions Triangle Measured at Pin mplitude V PP Impedance DC Level Linearity 0 0 Ω mv Referenced to Pin % From 0% to 0% to Swing Squarewave Measured at Pin, S 2 Closed mplitude 2 2 Vpp Saturation Voltage V Referenced to Pin 2 Rise Time nsec C L 0pF Fall Time nsec C L 0pF Notes Bold face parameters are covered by production test and guaranteed over operating temperature range. Specifications are subject to change without notice BSOLUTE MXIMUM RTINGS Power Supply V Storage Temperature Range C to +0 C Power Dissipation (package limitation) Ceramic package mW Derate above +2 C mW/ C Plastic package mW Derate above +2 C mw/ C SOIC package mW Derate above +2 C mW/ C 4

5 Q Q2 Q Q4 Q4 Q 2R Q Q R Q6 Q7 R Q Q Timing Capacitor 2 Q Q2 R Q0 Q R R R + 2R Triangle Wave 4 R2 4R R4 Binary Keying Inputs Timing Resistors Q6 Q7 B B Q R Q20 R6 Q2 R7 Square Wave Q27 Ground 0 Q22 Q24 Q2 Q26 BIS Q2 2 Figure 2. Equivalent Schematic Diagram

6 PRECUTIONS The following precautions should be observed when operating the family of integrated circuits:. Pulling excessive current from the timing terminals will adversely affect the temperature stability of the circuit. To minimize this disturbance, it is recommended that the total current drawn from pins 4,, 6, and 7 be limited to 6m. In addition, permanent damage to the device may occur if the total timing current exceeds 0m. 2. Terminals 2,, 4,, 6, and 7 have very low internal impedance and should, therefore, be protected from accidental shorting to ground or the supply voltage.. The keying logic pulse amplitude should not exceed the supply voltage. SYSTEM DESCRIPTION The functional blocks are shown in the block diagram given in Figure. They are a voltage controlled oscillator (VCO), four current switches which are controlled by binary keying inputs, and two buffer amplifiers for triangle and squarewave outputs. Figure 2 is a simplified schematic diagram that shows the circuit in greater detail. The VCO is a modified emitter-coupled current controlled multivibrator. Its oscillation is inversely proportional to the value of the timing capacitor connected to pins 2 and, and directly proportional to the total timing current I T. This current is determined by the resistors that are connected from the four timing terminals (pins 4,, 6 and 7) to ground, and by the logic levels that are applied to the two binary keying input terminals (pins and ). Four different oscillation frequencies are possible since I T can have four different values. The triangle output buffer has a low impedance output (0Ω TYP) while the squarewave is an open-collector type. n external bias input allows the to be used in either single or split supply applications. S2 I+ C 0.µF RL Binary Keying Inputs 0.µF 0 B V+ 2 C R 4 R2 R 6 R R2 R R4 C2 R4 7 SWO TWO 4 BIS V- 2.K.K Square Wave Triangle Wave S Figure. Test Circuit for Single Supply Operation 6

7 S2 I+ C Binary Keying Inputs 0.µF 2 V+ C B 0 C2 R R2 R R4 V R R2 R R4 SWO TWO 4 BIS I- RL Square Wave Triangle Wave 0.µF S Figure 4. Test Circuit for Split Supply Operation OPERTING CONSIDERTIONS Supply Voltage (Pins and 2) The is designed to operate over a power supply range of 4V to V for split supplies, or V to 26V for single supplies. Figure shows the permissible supply voltage for operation with unequal split supply voltages. Figure 6 and Figure 7 show supply current versus supply voltage Performance is optimum for 6V split supply, or 2V single supply operation. t higher supply voltages, the frequency sweep range is reduced. Ground (Pin 0) For split supply operation, this pin serves as circuit ground. For single supply operation, pin 0 should be C grounded through a µf bypass capacitor. During split supply operation, a ground current of 2I T flows out of this terminal, where I T is the total timing current. Bias for Single Supply (Pin ) For single supply operation, pin should be externally biased to a potential between V + / and V + /2V (see Figure ). The bias current at pin is nominally % of the total oscillation timing current, I T. Bypass Capacitors The recommended value for bypass capacitors is µf although larger values are required for very low frequency operation. Timing Resistors (Pins 4,, 6, and 7) The timing resistors determine the total timing current, I T, available to charge the timing capacitor. Values for timing resistors can range from 2kΩ to 2MΩ; however, for optimum temperature and power supply stability, recommended values are 4kΩ to 200kΩ (see Figure, Figure, Figure 0 and Figure ). To avoid parasitic pick up, timing resistor leads should be kept as short as possible. For noisy environments, unused or deactivated timing terminals should be bypassed to ground through 0.µF capacitors. Timing Capacitor (Pins 2 and ) The oscillator frequency is inversely proportional to the timing capacitor, C. The minimum capacitance value is limited by stray capacitances and the maximum value by physical size and leakage current considerations. Recommended values range from 00pF to 00µF. The capacitor should be non-polarized. 7

8 Positive Supply Typical Operating Range Positive Supply (m) R T =Parallel Combination of ctivated Timing Resistors T =2 C R T =2kΩ R T =kω R T =kω R T =20kΩ R T =200kΩ R T =2MkΩ Negative Supply (V) Single Supply Voltage (V) Figure. Operating Range for Unequal Split Supply Voltages Figure 6. Positive Supply Current, + (Measured at Pin ) vs. Supply Voltage T =2 C T =2 C Negative Supply Current (m) Split Supply Voltage (V) Total Timing Resistor RT MΩ 00kΩ 0kΩ kω 0 Timing Resistor Range 4V V 2V Single Supply Voltage (V) Figure 7. Negative Supply Current, I - (Measured at Pin 2) vs. Supply Voltage Figure. Recommended Timing Resistor Value vs. Power Supply Voltage

9 Frequency Error (%) 7 6 V S = 6V C=000pF K 0K 00K M 0M Timing Resistance (Ω) Figure. Frequency ccuracy vs. Timing Resistance Normalized Frequency Drift R T =2MΩ R T =20kΩ R T =200kΩ.6 T =2 C R T =Total R T =2kΩ.4 Timing Resistance.2 C=000pF Split Supply Voltage (V) Single Supply Voltage (V) Figure 0. Frequency Drift vs. Supply Voltage Normalized Frequency Drift (%) +2% +% 0 -% -2% -% 4kΩ 20kΩ 200kΩ 2MΩ 2kΩ V S = 6V C=000pF Temperature ( C) 200kΩ 20kΩ 2MΩ 4kΩ R=2kΩ Figure. Normalized Frequency Drift with Temperature

10 Binary Keying Inputs (Pins and ) The logic levels applied to the two binary keying inputs allow the selection of four different oscillator frequencies. The internal impedance at these pins is approximately kω. Keying voltages, which are referenced to pin 0, are <.4 V for zero and > V for one logic levels. Table relates binary keying input logic levels, and selected timing pins to oscillator output frequency for each of the four possible cases. Timing Capacitor 2 IT/2 C T4 T T2 T IT/2 Ib 0 Figure 2 shows the oscillator control mechanism in greater detail. Timing pins 4,, 6 and 7 correspond to the emitters of switching transistor pairs T, T2, T, and T4 respectively, which are internal to the integrated circuit. The current switches, and corresponding timing terminals, are activated by external logic signals applied to pins and. B Binary Keying Controls I 4 I2 6 7 I I4 R R2 R R4 2 V Logic Level Pin Pin Selected Timing Pins Frequency Figure 2. Simplified Schematic of Frequency Control Mechanism f 0 6 and 7 f + f 0 f 2 4 and f 2 + f 2 Table. Logic Table for Binary Keying Controls Definitions: f f f2 f2 RC R4C R2C RC Squarewave (Pin ) The squarewave output at pin is an open-collector stage capable of sinking up to 20m of load current. R L serves as a pull-up load resistor for this output. Recommended values for R L range from kω to 00kΩ. Triangle (Pin 4) The output at pin 4 is a triangle wave with a peak swing of approximately one-half of the total supply voltage. Pin 4 has a 0Ω output impedance and is internally protected against short circuits. MODES OF OPERTION Logic Levels: 0 = Ground, V Note For single supply operation, logic levels voltage at pin 0 are referenced to Split Supply Operation Figure is the recommended configuration for split supply operation. The circuit operates with supply voltages ranging from 4V to V. Minimum drift occurs with 6V supplies. For operation with unequal supply voltages, see Figure. With the generalized circuit of Figure, the frequency of operation is determined by the timing capacitor, C, and the activated timing resistors (R through R 4 ). The timing resistors are activated by the logic signals at the binary 0

11 keying inputs (pins and ), as shown in the logic table (Table ). If a single timing resistor is activated, the frequency is /RC. Otherwise, the frequency is either /(R R 2 )C or /(R R 4 )C. Figure B shows a fixed frequency application using a single timing resistor that is selected by grounding the binary keying inputs. The oscillator frequency is /R C. The squarewave output is obtained at pin and has a peak-to-peak voltage swing equal to the supply voltages. This output is an open-collector type and requires an external pull-up load resistor (nominally kω) to the positive supply. The triangle waveform obtained at pin 4 is centered about ground and has a peak amplitude of V + /2. Note For Single-Supply Operation, Logic Levels are referenced to voltage at Pin 0. Keying Inputs C 2 V+ C C2 SWO 4 B TWO 0 BIS R 4 R2 R 6 R4 7 V- 2 R R2 R R4 RL Square Wave Triangle Wave = Bypass Cap. General Case 2 V+ C C 2 SWO B TWO 4 0 BIS R R2 R R4 V C RL Square Wave Triangle Wave f=/r C = Bypass Cap R B. Fixed Frequency Case Figure. Split-Supply Operation

12 Single Supply Operation The circuit should be interconnected as shown in Figure 4 or Figure 4B for single supply operation. Pin 2 should be grounded, and pin biased from through a resistive divider to a value of bias voltage between V + / and V + /2. Pin 0 is bypassed to ground through a µf capacitor. For single supply operation, the DC voltage at pin 0 and the timing terminals (pins 4 through 7) are equal and approximately 0.6V above V B, the bias voltage at pin. The logic levels at the binary keying terminals are referenced to the voltage at pin 0. Keying Inputs 0 = Bypass Cap B V+ R 2 C R R2 4 C R2 R R 6 R4 C2 SWO TWO 4 BIS R4 V- 7 2.K RL.K Square Wave Triangle Wave. General Case C B 0 V+ 2 C C2 SWO TWO 4 BIS R R2 R R4 V R RL.K.K Square Wave Triangle Wave f=/r C = Bypass Cap B. Single Frequency Figure 4. Single Supply Operation 2

13 Frequency Control (Sweep and FM) The frequency of operation is controlled by varying the total timing current, I T, drawn from the activated timing pins 4,, 6, or 7. The timing current can be modulated by applying a control voltage, V C, to the activated timing pin through a series resistor R C. s the control voltage becomes more negative, both the total timing current, I T, and the oscillation frequency increase. The circuits given in Figure and Figure 6 show two different frequency sweep methods for split supply operation. Both binary keying inputs are grounded for the circuit in Figure. Therefore, only timing pin 6 is activated. The frequency of operation, normally f RC is now proportional to the control voltage, V C, and determined as: f RC VCR RCV- Hz If R = 2MΩ, R C = 2kΩ, C = 000pF, then a 000: frequency sweep would result for a negative sweep voltage V C V-. The voltage to frequency conversion gain, K, is controlled by the series resistance RC and can be expressed as: K f VC RCCV- Hz V The circuit of Figure can operate both with positive and negative values of control voltage. However, for positive values of V C with small (R C /R ) ratio, the direction of the timing current I T is reversed and the oscillations will stop. Figure 6 shows an alternate circuit for frequency control where two timing pins, 6 and 7, are activated. The frequency and the conversion gain expressions are the same as before, except that the circuit will operate only with negative values of V C. For V C > 0, pin 7 becomes deactivated and the frequency is fixed at: f R The circuit given in Figure 7 shows the frequency sweep method for single supply operation. Here, the oscillation frequency is given as: f RC R VC RC VT where VT = Vbias + 0.7V. This equation is valid from VC = 0V (RC is in parallel with R) to VC VT R RC Caution Total timing current I T must be less than 6m over the frequency control range.

14 f VCR CR RCV- C 2 V+ C C2 SWO TWO 4 B BIS 0 R R2 R R4 V IT 4.7K Square Wave Triangle Wave = Bypass Cap IO IC R R C V C V C Sweep or FM input Figure. Frequency Sweep Operation, Split Supply C 4.7K f VCR CR RCV- 0 2 V+ C C2 SWO TWO 4 B BIS R R2 R R4 V Square Wave Triangle Wave = Bypass Cap IO R R C IC V C V C Sweep or FM input Figure 6. lternate Frequency Sweep Operation, Split Supply 4

15 f CR R VC RC VT µf 0 µf C 4.7K 2 V+ C C2 SWO TWO B 4 BIS Vbias R R2 R R4 V K V T µf µf Square Wave Triangle Wave.K RC R VC- VC VC+ Sweep or FM input Figure 7. Frequency Sweep Operation, Single Supply Duty Cycle Control The duty cycle of the output waveforms can be controlled by frequency shift keying at the end of every half cycle of oscillator output. This is accomplished by connecting one or both of the binary keying inputs (pins or ) to the squarewave output at pin. The output waveforms can then be converted to positive or negative pulses and sawtooth waveforms. Figure is the recommended circuit connection for duty cycle control. Pin is shorted to pin so that the circuit switches between the 0,0 and the,0 logic states given in Table. Timing pin is activated when the output is high, and the timing pin is activated when the squarewave output goes to a low state. The duty cycle of the output waveforms is given as: Duty Cycle R2 R2 R and can be varied from 0.% to.% by proper choice of timing resistors. The frequency of oscillation, f, is given as: f 2 C R2 R The frequency can be modulated or swept without changing the duty cycle by connecting R 2 and R to a common control voltage V C, instead of (see Figure ). The sawtooth and the pulse output waveforms are shown in Figure.

16 4.7K C 2 0 V+ B C C2 SWO TWO 4 BIS Pulse Sawtooth R R2 R R4 V R2 R = Bypass Cap Figure. Duty Cycle Control 6

17 On-Off Keying The can be keyed on and off by simply activating an open circuited timing pin. Under certain conditions, the circuit may exhibit very low frequency (<Hz) residual oscillations in the off state due to internal bias currents. If this effect is undesirable, it can be eliminated by connecting a 0MΩ resistor from pin to.. Squarewave and Triangle s Two-Channel FSK Generator (Modem Transmitter) The multi-level frequency shift-keying capability of makes it ideally suited for two-channel FSK generation. recommended circuit connection for this application is shown in Figure 20. B. Pulse and Sawtooth s For two-channel FSK generation, the mark and space frequencies of the respective channels are determined by the timing resistor pairs (R, R 2 ) and (R, R 4 ). Pin is the channel-select control in accord with Figure. For a high logic level at pin, the timing resistors R and R 2 are activated. Similarly, for a low logic level, timing resistors R and R 4 are enabled. The high and low logic levels at pin determine the respective high and low frequencies within the selected FSK channel. When only a single FSK channel is used, the remaining channel can be deactivated by connecting pin to either or ground. In this case, the unused timing resistors can also be omitted from the circuit. C. Frequency Shift Keyed s Figure. Waveforms The low and high frequencies, f and f 2, for a given FSK channel can be fine tuned using potentiometers connected in series with respective timing resistors. In fine tuning the frequencies, f should be set first with the logic level at pin in a low level. Typical frequency drift of the circuit for 0 C to 7 C operation is 0.2%. Since the frequency stability is directly related to the external timing components, care must be taken to use timing components with low temperature coefficients. 7

18 µf C RL OV V f2 f Channel Select Keying Input 0 B V+ 2 C C2 SWO TWO 4 BIS f f2 FSK R R2 R R4 V R R2 R R4 µf 0K 0K 0K 0K Figure 20. Multi-Channel FSK Generation

19 4 LED CERMIC DUL-IN-LINE (00 MIL CDIP) Rev E D E Base Plane Seating Plane L B e B α c INCHES MILLIMETERS SYMBOL MIN MX MIN MX B B c D E E 0.00 BSC 7.62 BSC e 0.00 BSC 2.4 BSC L α 0 0 Note: The control dimension is the inch column

20 4 LED PLSTIC DUL-IN-LINE (00 MIL PDIP) Rev E D E Seating Plane L B e B 2 α e e B C INCHES MILLIMETERS SYMBOL MIN MX MIN MX B B C D E E e 0.00 BSC 2.4 BSC e 0.00 BSC 7.62 BSC e B L α 0 0 Note: The control dimension is the inch column 20

21 6 LED SMLL OUTLINE (00 MIL JEDEC SOIC) Rev..00 D 6 E H Seating Plane e B C α L INCHES MILLIMETERS SYMBOL MIN MX MIN MX B C D E e 0.00 BSC.27 BSC H L α 0 0 Note: The control dimension is the millimeter column 2

22 Notes 22

23 Notes 2

24 NOTICE EXR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXR Corporation is adequately protected under the circumstances. Copyright 7 EXR Corporation Datasheet June 7 Reproduction, in part or whole, without the prior written consent of EXR Corporation is prohibited. 24

XR-2206 Monolithic Function Generator

XR-2206 Monolithic Function Generator ...the analog plus company TM XR-0 Monolithic Function Generator FEATURES Low-Sine Wave Distortion 0.%, Typical Excellent Temperature Stability 0ppm/ C, Typical Wide Sweep Range 000:, Typical Low-Supply