Modeling, Analysis and Control of a Chain Cell Converter

Transcription

1 Moelng, Analyss an Control of a Chan Cell Converter A. Kran Kumar, an K. R. Payar, enor Member, IEEE Abstrat Chan ell onverter as a shunt onnete, multlevel voltage soure onverter has been propose for stat AR ompensaton. Ths onverter onssts of ental H-Brge Bulng Bloks (HBBBs) onnete n seres n eah phase. Chan ell onverter syntheszes a esre a waveform from several levels of DC voltages prove by the DC apators wth only one swthng per yle. The transent moel of the onverter s evelope onserng a three phase three wre system. The analyss an esgn of onverter ontrols s presente. DC voltage balanng strategy whh nvolves pulse swappng s mplemente. mulatons are arre out for the performane evaluaton of onverter ontrols. Chan ell onverter s also teste, when onnete n a strbuton system, as a TATCOM to ompensate the voltage flker ue to an ar furnae loa. ontrol of seven level han ell onverter, whh an be extene to any number of levels. The struture of sngle phase, seven level han ell onverter whh onssts of three ells onnete n seres s shown n Fg. a. Eah ell omprses an H-brge wth ts own apator harge to an ntal voltage of, as shown n Fg. b. Eah ell generates a three level output voltage omprsng +, 0 an. As all the ells n a phase are onnete n seres, the a output voltage E, s the summaton I. INTRODUCTION HUNT onnete stat ompensators (TATCOM) are nreasngly apple for fast reatve power ompensaton, ontrol of voltage flker an atve flterng. In aton to pulse wth moulate, two level (voltage soure) onverters, multlevel onverters an also be onsere for generatng snusoal waveform for these applatons. A han ell onverter onstrute wth H-Brge Bulng Bloks (HBBBs) onnete n seres n eah phase, forms a asae multlevel onverter [-]. The han ell onverter syntheszes a esre a waveform from several levels of DC voltages prove by DC apators wth only two swthng per yle. The han ell onverter has the followng avantages [5].. It s energy effent ue to less swthng losses ompare to Pulse Wth Moulate (PWM) onverters.. It s ost effetve as phase shftng transformers are not requre as n multpulse onverters.. Less eve ount as ompare to multlevel oe lamp onverters.. Less apator ount as ompare to multlevel flyng apator onverter. 5. Wth a sutable hoe of frng angles the lower orer harmons an be ompletely elmnate. 6. Beause han lnks swth n sequene, the maxmum voltage exurson of the onverter waveform s lmte by the number of swthes n seres. Therefore, rao nterferene s mnmse. Ths paper eals wth moelng, analyss an A Kran Kumar, Engneer, ITTIAM systems (P) Lt, Bangalore. Emal : kran.kumar@ttam.om. K R Payar, Emertus professor, Department of Eletral Eengneerng, Inan Insttute of ene, Bangalore. Emal : krpyar@ee.s.ernet.n /08/$ IEEE (a) (b) Fg.. (a) even level han ell onverter. (b) H-brge that forms the ell. of output voltages of eah of the ells. A stak of n ells per phase proues (n +) level symmetral starase voltage waveform, whh gves a better approxmaton to a sne wave. The output voltage of the sngle phase, seven level onverter s shown n the Fg. a. The phase urrent I wll be ether leang or laggng the phase voltage E by The average harge to eah apator s zero over half yle. Beause of (a) (b) Fg.. (a) even level output voltage of a han ell onverter. (b) wthng funtons for eah ell. ths symmetr harge flow, the average voltage on all the apators reman onstant at n steay state. The phase output voltage s ontrolle by ontrollng the frng angles of eah of the ells. The funamental omponent of output

2 voltage, E, ees the ompensatng urrent I. Fg. b shows the swthng funtons of eah ell n a sngle phase seven level onverter. The Fourer expanson for the swthng funtons a, a, an a are as follows a a a π π π n,,5... n,,5... n n,,5... n n [ os( nα )] sn( nωt) [ os( nα )] sn( nωt) () () [ os( nα )] sn( nωt) () The termnal voltage of a sngle phase, seven level han ell onverter s E a () Where, a a + a + a an s the voltage aross the nvual DC apators. II. TRANIENT MODELING OF CHAIN CELL CONERTER Conser a three phase, three wre system as shown n the Fg., where an, bn an n represent the soure voltages per phase wth respet to ts neutral pont n an E an, E bn, E N represent the three phase output voltage of a seven level han ell onverter wth respet to ts neutral pont N. where, a, b or. The transent moel of the three phase seven level han ell onverter for a three phase three wre system s obtane as C 0 0 t t C n ENn () t C I t R I L L L L L L where, the varables, an n (0) an (), represent the voltage aross the apators C, C, C respetvely.,, represent the swthng funtons for th phase of the onverter. The three phase, three wre system esrbe above s smulate for apatve an nutve operaton of han ell onverter. The system parameters use are lste n Appenx A. Fg. shows urrent an voltage waveforms when the apatve urrent s rawn by han ell onverter an Fg. 5 shows the waveforms when nutve urrent s rawn. Fg. 6 shows the onverter neutral voltage wth respet to the soure neutral voltage.e. E Nn. Fg.. A three phase three wre system. Conserng the phase a of the system, we an wrte I a an L + R I a + Ean t (5) where, E an s the onverter output voltage wth respet to the soure neutral n. E an an be wrtten as E an EaN + ENn (6) where, E Nn represents voltage between the soure neutral an the onverter neutral. mlarly, for the other two phases, Ebn EbN + ENn (7) En EN + ENn (8) Ang (6) - (8) an on rearrangng, we arrve at EaN + EbN + EN ENn (9) In ervng (9), t s assume that the sum of the soure voltage s zero (.e. zero sequene omponent oes not exst). The phase voltage of the onverter wth respet to ts neutral N, for a seven level han ell onverter, aorng to () s, E + + (0) N Fg.. Fgure showng termnal voltages E a, E b, E an the apatve urrents I a, I b an I rawn by three phase seven level han ell onverter. Fg. 5. Fgure showng termnal voltage E a, E b, E, an the nutve urrents I a, I b an I rawn by three phase seven level han ell onverter. III. ANALYI AND DEIGN OF CONTROLLER The funamental omponent of the onverter termnal voltage has to be ontrolle so as to net the esre reatve urrent. The termnal voltage s ontrolle by ontrollng the frng angles of the onverter. The frng angles are erve from the urrent ontroller an DC voltage ontroller. The esgn of

3 Fg. 6. Fgure showng onverter neutral voltage E Nn along wth termnal voltage E a an soure voltage a for phase a of the onverter. eouple urrent ontroller an DC voltage ontroller s one by onserng the moel of han ell onverter n -q referene frame, whh s base on the followng assumptons.. The soure voltage s onsere to be balane an snusoal.. The swthes are assume to be lossless. The harmons n the onverter output voltage, E, are neglete.. All the apators are assume to be lossless an the voltage aross eah of the apators s assume to be onstant at. Conser a system where the han ell onverter onnete to a bus through a reator havng an nutane L an resstane R as shown n Fg. 7a. There s no loss of generalty assumng phase of soure voltage as 0 0. voltage s taken as referene for the ompensator voltages. The onverter raws small real power to mantan the DC apator voltage. The nstantaneous atve an reatve power rawn wll be p an q q. Therefore, an q etermnes the atve an reatve power omponents of the onverter. Ths requres eouple ontrol of the two urrent omponents, an q, n orer to ontrol real an reatve power omponents, p an q nepenently. To ensure ths, the esre onverter output voltages are gven by e v ωl u (7) q eq vq + ωlq uq (8) Fg. 8 shows the DC voltage an eouple urrent ontrollers. The nner loops are the urrent ontrol loops whh generate the esre termnal voltage referene e an e q. The outer loop s the DC voltage ontrol loop whh generates the urrent referene n orer to ontrol the DC voltage aross eah of the apators. The reatve urrent referene q s etermne aorng to the reatve ompensaton requrements. Fg. 8. DC voltage an eouplng urrent ontrollers. Fg. 7. (a) Equvalent rut of ompensator onnete to the system. (b) Representaton n -q frame. The equatons for the rut shown n Fg.7(a) (usng -q omponents) are gven by, L + R u () t q L + Rq uq () t where, u v e ωl () q uq vq eq + ωl The equaton for s gven by k sn θ δ + t C where, (5) ( ( ) os( θ δ )) (6) q k [ os( α ) + os( α ) os ( α )] an ( + ) + π. + C 7 C C C C, C an C are the apatanes n three ells of eah phase, respetvely. The ervaton of the relaton n (6) s presente n Appenx B for referene. () () an (6) represent the moel of han ell onverter n -q referene frame. Control s aheve through varaton of k an δ. The zero rossng bus The urrent ontrollers are of PI type an are esgne usng pole zero anellaton metho. In esgnng the urrent ontrollers, onverter elay s neglete. Aorng to (7) an (8), the ontrol varables u an u q are obtane as outputs from two nepenent PI urrent ontrollers as shown n Fg. 9. Fg. 9. (a) -axs urrent ontroller. (b) q-axs urrent ontroller. T s hosen as L to anel the pole. K R, where τ τ s the esre tme onstant. The lose loop transfer funton for the -axs urrent an the q-axs urrent q are ( s) ( s) (9) τ s + q ( s) τ s + q ( s) L (0)

4 τ s hosen as 5ms. For ths value of τ, the ontroller parameters wll be K 0.7 an T 6.66mse. The purpose of DC voltage ontroller s to mantan a onstant DC voltage aross the apators by ontrollng the -axs urrent referene of. The DC voltage ontroller s esgne base on the small sgnal moel about the operatng pont. In the analyss, the onverter swthes an DC apators are assume to be lossless. We an wrte the power balane equaton as I e + eqq () About the operatng pont ( o, qo ), e o k o, e qo 0, o 0 an I o 0. Lnearsng () about the operatng pont, we arrve at, eoδ + qoδeq Δ I () o The soure voltage s assume to be onstant an the esre reatve urrent referene s also onstant. o, v q 0 an q 0. The small sgnal moel for the onverter about the operatng pont s obtane from () as Δeq ω olδ () ubsttutng () n (), we arrve at Δ I b Δ () ω L o qo where, b k+. The varaton of b wth the operatng o pont, qo, s plotte n Fg.0. The urve s plotte for k.75, orresponng to mnmum THD. p The haraterst equaton of the system s s + s+ 0. τ τ C τ etermnes the DC voltage ontroller settlng tme (T s ), aorng to the relaton, T s 9.τ. From the haraterst C equaton, the ampng rato s. The DC voltage ζ K p b τ K b ontroller gan K p s hosen as 0. The ampng rato ζ for the esgne DC voltage ontroller wll be 0.75, for the operatng pont of qo -pu.e. pu apatve urrent rawn by the han ell onverter. I. DC OLTAGE BALANCING TRATEGY The wave forms of bus voltage, onverter termnal voltage E, an the urrent nete by onverter, I, for phase a of the onverter are shown n Fg.. The phase urrent I wll be ether leang or laggng the phase voltage E by 90 0, when use as a TATCOM uner normal ontons. The average harge to eah apator wll be zero over half yle an thus the average apator voltage remans onstant over a funamental yle. However, the DC voltage annot be mantane ue to swthng an apator losses. If E s ontrolle suh that t lags by small angle δ, then the total E real power flow nto the onverter s snδ, where, X X s the mpeane of nterfae nutor. The phase shft of δ, s ontrolle by the outer DC voltage ontrol loop as shown n Fg. 8. ne the onuton peros of eah of the apators Fg.. Control of nvual DC apator voltages. Fg. 0. araton of b wth reatve urrent q. The DC voltage ontroller K p s esgne base on the small sgnal moel evelope about the operatng pont. The analytal moel of ontrol loop for DC voltage s shown n the Fg.. Fg.. Analytal moel for DC voltage ontroller esgn. The lose loop transfer funton obtane for the DC voltage ontroller s K pb (5) K pb τ C s + s + τ τ C n a phase are fferent, the swthng losses are fferent an hene eah DC apator voltage may not be exatly balane wth the outer loop only. eparate nner DC voltage ontrol loops for eah apator are neessary n orer to mantan eah of the apator voltages at. The purpose of nner ontrol loop s to offset the real power flow to nto eah of the nvual H-Brges [], whh s aheve by shftng the swthng patterns as shown n Fg.. The amount of harge flow ue to phase shft of α s ΔQ π α α +Δ +Δ α α I osα I osα sn Δα (6) where,,,...n. n s the number of apators per phase an I s the rms value of the lne urrent. The harge flow nto the th ell s proportonal to α. Thus, usng an nner ontrol loop, we shft the frng angle by α suh that the apator voltages are balane. The phase shfts are of the orer,

5 α << δ < 0.0ra. The number of nner ontrol loops requre are equal to (n ) for a three phase han ell onverter. The savantages of usng the above sheme for mantanng eah of the apator voltages of a han ell onverter are. Unequal utlzaton of the swthes.. Usng apators of fferent values makes the seleton ffult.. Large number of nner DC voltage balanng loops. There s also a problem of overhargng an uner hargng of apators, when the han ell onverter s use for harmon flterng, as shown n the Fg.. In orer to overome these savantages, a new ontrol strategy s propose [6] for mantanng the apator voltages, where eah apator of the onverter proues voltage pulses of all wths as shown n the Fg.. The avantages of ths pulse swappng tehnque are. We an use sngle value of apatane n all the ells of the onverter.. All swthes are equally utlze.. The voltage aross eah of apators wll be onstant, thus elmnatng the nner DC voltage balanng loops. Fg.. Overhargng an overshargng of apators. swappng log wll rotate the frng pulses every half yle among the ells. The phase angle of soure voltage, θ, s taken as referene for frng the swthes. The onverter ontrols are teste wth step hanges n urrent an DC voltage referenes an the smulaton results are presente. Fg. 5. Blok agram showng the generaton of frng pulses. The urrent ontroller s teste wth step hange n the urrent referene from apatve urrent of pu to nutve urrent of pu at 0.5 se an bak to apatve urrent of pu at 0.65 se. The response of the urrent ontroller s shown n the Fg. 6. The waveform showng the transton from apatve urrent of pu to nutve urrent of pu at 0.5 se for phase a of the onverter s shown n the Fg. 7 an the transton from nutve urrent of pu to apatve urrent of pu at 0.65 se s shown n the Fg. 8. It s observe that the response of the urrent ontroller s qute rap as expete an the settlng tme s a fraton of a yle. Fg. 6. Response for step hange n the reatve urrent from apatve to nutve an bak to apatve. Fg.. Pulse swappng strategy.. PERFORMANCE EALUATION OF CONERTER CONTROL A. TATCOM onnete to a voltage soure Fg. 8 shows the eouple urrent ontrol an DC voltage ontrol strategy whh generates the termnal voltage referene, E an the phase shft δ. Fg. 5 shows the blok agram for generatng the frng pulses to eah of the ells. The referene termnal voltage, E, generates the swthng angles for eah of the ells of han ell onverter through a swthng pattern table. Ths table ontans an array of possble termnal voltages of the han ell onverter an the orresponng frng angles for eah of the ells. The pulse Fg. 7. Waveforms showng the transton from apatve to nutve for phase a of the onverter.

6 Fg.. Compensaton sheme for generatng the ompensatng urrent referenes. Fg. 8. Waveforms showng the transton from nutve to apatve for phase a of the onverter. Fg. 9 shows the response of DC voltage ontroller for a step hange n DC voltage from 0.pu to 0.5pu an bak to 0.pu. The DC voltage ontroller settlng tme s foun to be 50mse as ompare to 6mse ompute theoretally. Fg. 9. Response to step hange n DC voltage. B. TATCOM as a ompensator n a strbuton system An eletr power system, shown n Fg. 0, s onsere for reatve power ompensaton at PCC (Pont of Common Couplng). It onssts of an ar furnae supple va H/M Fg. 0. hemat of eletr power system wth ompensator. transformer from a transmsson network. The M/L transformer supples power to the ar furnae. Appenx A gves the system ata. The ar furnae s a hghly varable nonlnear loa an proues voltage flker n the strbuton system. TATCOM onnete at the PCC shoul net the requre ompensatng urrent suh that soure urrent beomes balane an snusoal, thus, reung the flker at PCC. The ompensaton sheme, shown n Fg., s use to generate the referene urrents, an q, for TATCOM, whh wll ontan the harmons, negatve sequene an zero sequene omponents of loa urrent. The funamental omponent of loa urrent, whh has to be supple by soure, s extrate usng low pass flters. s an sq represents the referene -q omponents of the soure urrent. The referene soure urrents are s ar + Δs (7) s q K qarq (8) where, K q <, s the egree of ompensaton use. The shunt apatane onnete at PCC s esgne to supply half of the maxmum ompensatng urrent requre by the loa. Ths s norporate n the ontrol strategy by takng K q as 0.5. s represents the output of DC voltage ontroller. The referene urrents for the onverter, an are extrate by subtratng the loa urrent from the soure urrent. s (9) q sq arq (0) Fg. an Fg. shows the smulaton results for reatve AR ompensaton at PCC. From Fg., we an observe that varaton n the magntue of PCC voltage s 0.5pu before ompensaton. The han ell onverter s swthe on at 0.6 se to meet the ompensaton requrements. After ompensaton, the varaton n PCC voltage s 0.066pu. From Fg. 6, we an observe that the magntue of varaton n soure urrent reues from 0.6pu before ompensaton to 0.pu after ompensaton. The average magntue of the soure urrent s also reue ue to reatve ompensaton. ar I. CONCLUION In ths paper, han ell onverter s propose as a shunt onnete TATCOM. The transent moel of the han ell onverter s presente onserng a three phase three wre system. The ontrollers for the han ell onverter are esgne to net the esre reatve urrent an regulate the DC voltage aross the apators base on the small sgnal moel evelope about the operatng pont. Pulse swappng strategy s use to mantan the DC voltage aross eah of the apators onstant. The ontrol esgn s teste by transent gtal smulaton of the onverter onnete to a voltage soure. The performane of the shunt onnete han ell onverter n a strbuton system, for the ompensaton of voltage flker ause by an ar furnae, s also evaluate. The results valate the effeny of the ontrol esgn.

7 Fg.. Magntue of PCC voltage soure urrent I s, apator urrent I ap. Fg.. Magntue of ar urrent I ar an ompensator urrent I. II. APPENDIX A Chan ell onverter ata: F 50Hz; ω πf; X ωl 0.pu; R 0.0pu; apatane n eah ell: b ωc 9.98pu. Note that C C C usng pulse swappng strategy. Eletr power system ata: s pu; X s 0.pu; R s 0.0pu; X T 0.5pu; R T pu; X T 0.66pu; R T 0.008pu; X L 0.8pu; R L 0.08pu; b ap.08pu. III. APPENDIX B Conserng a han ell onverter wth n ells stake n seres per phase, the voltage evelope aross the termnals of any phase wll be E n () n where, a, b or represent the phase of the onverter. E s the prout of two vetors, DC voltages aross the apators an the swthng funton for that ell. n an n represent voltage aross the DC apator an the swthng funton for n th ell respetvely, where n,,, n. Equaton () an be represente as... n E (... n ) ΔE v n () represents the ombne swthng funton for phase of the onverter. E s neglete on assumpton thatn. The funamental omponent of swthng funtons for eah of the phases wll be a k sn ( ωt + θ δ ) () π b k sn( ωt + θ δ ) () π k sn( ωt + θ δ ) (5) where, k [ ( ( α ) os( α )... os( α n )] os π When the three phase output voltage of the onverter are transforme to -q frame of referene, we arrve at e k sn θ δ (6) e q k ( ) os( θ δ ) (7)

8 The varaton of voltage aross the apator of eah ell of phase s gven by n n (8) t Cn Conserng a phase of the onverter, we an wrte (8) as n n n (9) t C n C C n Equaton (9) an be represente as, n C C C n n Δ t n n Assumng that the ontrbuton of to DC voltage varaton s neglgble, we arrve at (0) t n Ceq where, ummng up the varaton n Ceq C C C n DC voltage n all the three phases, usng (0), we an wrte a b aa + bb + ( + + ) t n C where, where, t C t a a a + n b b Ceq + eq. Rearrangng (), we arrve at, () C aa + bb + () t n C. ubsttutng () - (5) n () we get, C eq ( sn( θ δ ) + os( θ δ )) () k q IX. REFERENCE [] F. Z. Peng an J.. La, "Multlevel onverter onverters - A new bree of power onverters," IEEE Transatons on Inustry Applatons, vol., no., pp , May/June 996. [] F. Z. Peng an J.. La, "A Multlevel voltage-oure Inverter wth eparate DC oures for tat AR Generaton," IEEE transatons on nustry applatons, vol., no.5, pp. 5-58, ept./ot [] K. R. Payar, "FACT Controllers n Power Transmsson an Dstrbuton", (New Delh) New Age Publshers, 007. [] D. W. anells, T. C. Green, M. Osborne, A. Power, "Power ystem Applatons for Chan Cell Converter," IEE, 85 publaton, AC/DC power transmsson, pp 9-97, Nov.00. [5] J. D. Answorth, M. Daves, P. J. Ftz, K. E. Owen, D. R. Traner, "tat AR ompensator (TATCOM) base on sngle phase han rut onverters," IEE proeengs Gener. Transm. Dstrb., ol.5, no., pp. 8-86, July 998. [6] F. Z. Peng, John W. MKeever, Donal J. Aams, "A Power Lne Contoner Usng Casae Multlevel Inverters for Dstrbuton ystems," IEEE transatons on Inustry Applatons, vol., no.6, pp. 9-98, Nov/De 998. X. BIOGRAPHIE A. Kran Kumar reeve hs BE egree n eletral Engneerng from Osmana Unversty, Hyeraba, INDIA n 00, ME egree n Eletral Engneerng from Inan Insttute of ene, Bangalore, INDIA n 007. He s urrently workng wth ITTIAM systems (P) Lt. K. R. Payar (M 9) reeve hs BE egree n Eletral Engneerng from Poona Unversty, Poona, INDIA n 96, ME egree from Inan Insttute of ene n 96, an PhD egree from Unversty of Waterloo, Waterloo, ON, Canaa n 97. He s an Honorary Professor of Eletral Engneerng at I.I.., Bangalore. He was wth Inan Insttute of Tehnology, Kanpur, Ina, from pror to onng I.I.. Hs researh nterests are n the area of HDC an FACT, system ynams an ontrol. He has authore four books an over 00 papers. Dr. Payar s a Fellow of Inan Natonal Aaemy of Engneerng.