IEEE 802.3af DTE Power via MDI System Considerations - System Modeling

Transcription

1 IEEE82.3af, March 2 IEEE 82.3af DTE Power via MDI System Considerations System Modeling Presented by Yair Darshan, PowerDsine yaird@powerdsine.com

2 IEEE 82.3af, March. 2.! Objectives! Identifying system parameters required to ensure PSE PD interoperate with minimum limitations on specific implementations.! Strategy! Derive actual or theoretical models for known system functions! Analyzing results! Add / Modify conclusions to system spec. 2

3 IEEE 82.3af, March. 2. Topics! System Powering/Detection functions modeling! Detection time vs. system parameters! PD input signature as function of leakage caused by different sources.! Dynamics between PD power supply and UVLO functions! System dynamics effects on Imin/Imax requirements! Where to locate inrush current limited at PSE side or PD?! PD input port main requirements. 3

4 System Powering/Detection Functions IEEE 82.3af, March. 2. Probing Voltage PSE Cs 2 diodes in series Isolating switch EMI Filter DTE 5V 44V 57V Rs Cb2 Control Cb Rsig SS UVLO EMI Filter Control Cs2 Low power switch 4

5 PSE Main Functions Measuring PSE switch power loss v(pse_csp,pse_csn)*v(pse_out_r,pse_csp) PSE_SWITCH_LOSS R2 k Measuring Rsig at PSE output port PSE_OUT Rsig_m R_Isig {R_Isig} PSE_OUT IEEE 82.3af, March. 2..*(75)*V(PSE_OUT,PSE_OUT_R)/(v(PSE_OUT,probe_rtn)v(PSE_OUT,PSE_OUT_R)+ TABLE = (,) (5,5) R25 k Results in KOhm E2 E E4 V(Rsig_m)*V(Rsig_w) Rsig Rsig_w V22 PW = {ps_delay.} TD = MS Port out + V = V2 = 2 TD = TR = ms PW = 5ms TF = ms PER = 2s D7 Dbreak V V = V2 V2 = 24 TD = {det_delay} TR = ms PW = 5m TF = ms PER = 2s D8 Dbreak probe_rtn V7 R26 75k V = V2 = 44 TD = {ps_delay} TR = MS PW = 2s TF = MS PER = 4s D PSE_OUT_R V4 6V V2.5V pse_csn 3 2 LM324 C nf R37 UA + R33 4 V+ V k OUT pse_csn R3 K R45 k pse_csp IRF5 D DN42 M PSE_OUT_R R_Isig =. C9.44uf Port out Detection probing source Part of PSE over current/current limiter circuit. 5

6 PD Main Functions IEEE 82.3af, March. 2. Measuring PD switch power loss Signature Resistor PD_IN D3 v(pd_csp,pd_csn)*v(,pd_csp) E3 PD_SWITCH_LOSS R23 k R36 PD's power supply "Big Cap" PD_PS_IN DN42. C8.uF R39 MEG R28 22K R34 3K V5 V3.35V 5 6 LM324 C2 nf UB + 4 V+ V OUT R32 K 7 R47 R3 k C 47u PD_IN_R 6V M2 R38 pd_csn R35 k pd_csp k M3 Isolating Switch IRFL53 IRFL53 Optional circuit To be discussed Isolating Switch and PD inrush current limiter may be integrated to one circuit Part off PD inrush current limiter circuit. 6

7 IEEE 82.3af, March. 2. PSE/PD Model Can check the following:! Current limit time response! Power Dissipation during startup for a given PD! Optimizing startup requirements! Power dissipation at steady state! Power dissipation at dynamic load operation! Detection timings and reflected Signature value! Possible sources of leakage current affecting Signature tolerance. 7

8 Cable Low Frequency Parameters IEEE 82.3af, March. 2. PSE_OUT PSE_OUT Rline {R_Line*Length} 2 L {L_Line*Length} PD_IN PD_IN Length = R_Line =. L_Line =.5uH C_Line = 5pF m /m (Scaled) /m (Scaled) /m (Scaled) C6 {.5*C_Line*Length} C5 {.5*C_Line*Length} PSE_OUT_R PSE_OUT_R Rline2 {R_Line*Length} L2 {L_Line*Length} 2 PD_IN_R PD_IN_R Low frequency model 8

9 PD Power Supply Model IEEE 82.3af, March. 2. PD_IN Vin_dc = 48 Fs = bypass_softstart = bypass_uvlo = V(Don)*I(Lp)/(V(Don)+V(Doff)) R36. PD_PS_IN E7 GVALUE G2 Drain Rdson {Rdson} Rsense {Rsense} Lp {Lp} R5. V(Don)*V(PD_PS_IN,Drain)+V(Doff)*V(,sec)/n POWER STAGE MODEL V(Doff)*I(Lp)/(n*(V(Don)+V(Doff))) G GVALUE sec D PD_PS_OUT Resr {Resr} Cout {Cout} Rload {Rload} Cout = 22uF Resr =. n =.527 Rdson =.8 Rload = 2.5 ps_delay = ms det_delay = 5ms Lp = 2u Rsense =.8 v(uvlo_on)*2*lp*fs*(v(vc)i(lp)*rsense)/(.+rsense*v(pd_ps_in,drain)) ext R7 48.7k R2 48.7k Don R9 46.4K Doff min(2*i(lp)*lp*fs/(v(pd_ps_in,drain)*v(don))v(don),v(don)) V9 2.5v R2 5k E5 C7 362*V(%IN+, %IN) PWM CONTROLER.47uF Vc ext ( V(%IN) +V(%IN2) ) PD_PS_OUT V v Control Loop Frequency respone measurements 4V V6 C6.U R6 K R8 3K PD_PS_IN REF4 ramp D2 C7.U DN75 G4 E8 *V(%IN+, %IN) UVLO GTABLE OUT+ IN+ OUT IN E6 E E9 uvlo_on_ uvlo_on soft_s v(uvlo_on_)*(v(soft_s)+bypass_softstart)+bypass_uv E soft_s S + + Sbreak VOFF =.2 VON =.5 V(%IN+, %IN) uvlo_on_ uvlo_on_ SOFT START.*V(%IN+, %IN) 9

10 PD Power supply model description IEEE 82.3af, March. 2.! Topology: Flyback converter. " Chosen for exhibits the worst case dynamic response.! Automatic operation at Continuous and Discontinuous Conduction Current operating modes (CCM and DCM)! Can be operate at Voltage or Current mode control concept! Fast and Accurate simulation technique based on Average Behavioral Modeling concept.! Includes: " Open and Closed loop analysis tools " Pulse by Pulse current limit block " UVLO function " Soft Start function

11 PD Power supply model Capabilities IEEE 82.3af, March. 2.! Can be used to: " Analyze Dynamics of Startup and Powering modes " Optimizing System Parameters requirements " Optimizing PD requirements " Help finding pitfalls in system definition

12 4 4 All functions together IEEE 82.3af, March. 2. V = V2 = 2.7 TD = TR = ms PW = 5ms TF = ms PER = 4s D7 Dbreak V ext prb_ofs = 2 V = V2 V2 = 24.7 TD = {det_delay} TR = ms PW = 5m TF = ms PER = 4s D8 Dbreak probe_rtn R26 75k V9 2.5v V7 PSE_OUT_R Don DC = V = V2 = 44 TD = {ps_delay} TR = MS PW = 2 TF = MS PER = 4s V4 6V Doff E 362*V(%IN+, %IN) V2.5V ext C7 pse_csn v(uvlo_on)*2*lp*fs*(v(vc)i(lp)*rsense)/(.+rsense*v(pd_ps_in,drain)) E5 min(2*i(lp)*lp*fs/(v(pd_ps_in,drain)*v(don))v(don),v(don)) E7 R7 48.7k R2 48.7k R9 46.4K D R2 5k R3 MEG.47uF UA LM324 C nf R37 k ( V(%IN) +V(%IN2) ) Vc R33 V+ V OUT R3 K pse_csp PD_PS_OUT V v R45 k IRF53 D DN42 M GVALUE PD_PS_IN ramp D2 C7.U DN75 C9.44uf PSE_OUT PSE_OUT_R V(Don)*I(Lp)/(V(Don)+V(Doff)) R6 K C6 S + +.U Cout = 22uF R8 Sbreak Resr =. 3K VOFF =.2 Lp = 2u VON =.5 Rload = 2.5 Rdson =.8 E9 uvlo_on_ uvlo_on n =.527 soft_s INOUT Rsense =.8 v(uvlo_on_)*(v(soft_s)+bypass_softstart)+bypass_uvlo ps_delay = ms det_delay = 5ms INOUT G2 INOUT Drain soft_s uvlo_on_ Rline {R_Line*Length} 2 G4 E Rdson {Rdson} Rsense {Rsense} V(%IN+, %IN) GTABLE.*V(%IN+, %IN) C6 {.5*C_Line*Length} C5 {.5*C_Line*Length} Rline2 {R_Line*Length} 4v Length = R_Line =. L_Line =.5uH C_Line = 5pF V6 L {L_Line*Length} m /m (Scaled) /m (Scaled) /m (Scaled) L2 {L_Line*Length} 2 Lp {Lp} R5. GVALUE G PD_IN C8.U PD_IN_R V(Doff)*I(Lp)/(n*(V(Don)+V(Doff))) *V(%IN+, %IN) uvlo_on_ D3 DN42 R39 MEG sec R34 3K D R28 22K PD_PS_OUT Cout {Cout} Resr {Resr} M2 R4 Rload {Rload} Vin_dc = 48 Rline = 2 Fs = bypass_softstart = bypass_uvlo = INOUT V(Don)*V(PD_PS_IN,Drain)+V(Doff)*V(,sec)/n PD_PS_IN E8 REF4 INOUT MEG V5 6V Title V3.35 pd_csn R38 UB LM324 C2 nf V+ V R35 k OUT pd_csp v(pse_csp,pse_csn)*v(pse_out_r,pse_csp) E2 PSE_SWITCH_LOSS R32 K Rsig_m TABLE = (,) (5,5) v(pd_csp,pd_csn)*v(,pd_csp) PD_SWITCH_LOSS PSE & PD System Mode, Yair Darshan/PowerDsine Size Document Number Rev Custom <Doc> A Date: Thursday, March 8, 2 Sheet of 7 PD_PS_IN IRF53 E3 E4 V(Rsig_m)*V(Rsig_w) Rsig Rsig_w INOUT V22 PW = {ps_delay.} TD = MS INOUT INOUT R36. R47 k R23 k R2 k R25 k M3 R3 3K Results in KOhm C 47uF E6 INOUT.*(75)*V(PSE_OUT,PSE_OUT_R)/(v(PSE_OUT,probe_rtn)v(PSE_OUT,PSE_OUT_R)+** E OUT+ IN+ OUT IN INOUT INOUT 2

13 IEEE 82.3af, March. 2. Summary! The proposed system model can be used for: " System dynamics analysis " System Stability " PerformanceRequirements analysis " The system model is specified for Powering and detection functions 3