AN017 AS1113 / AS1124

Transcription

1 AN017 IEEE Standard 802.3af PD Conformance Report AS1113 / AS1124 Rev 0.3 July 2007

2 CONTENTS Overview...3 PICs Proforma Table for PD...3 Conformance Test...5 Schematic, Layout, and BOM...6 Evaluation Boards and Interface Boards Used...13 List of Equipment Used and Test Setup...15 Test Result from PDA Tester...19 Detection / Classification Data Analysis...19 Test Result of PD Operation while Noise Presence from PSE...22 Analysis of PD Operation over Noise Presence...22 Back-feed Voltage Measurements...23 Power Supply Turn On / Off Analysis...23 Summary...24 Related Documentation...24 Contact Information...24 Important Notices /23/ Akros Silicon

3 Overview The AS1113 and AS1124 are two devices from the AS1100 family, which are highly integrated CMOS, single channel 10BASE-T / 100BASE-TX / 1000BASE-T powered device (PD) with a PD controller, DC-DC Controller, rectification and protection circuitry. AS1100 family devices are for Power over Ethernet (PoE) applications including Voice over IP (VoIP) Phones, Wireless LAN Access Point, Security and Web Cameras, Analog Telephone Adapters (ATA) and Point of Sales Terminals. AS1113 and AS1124 are designed to address 13W and 24W PoE applications respectively. The highest level of integration provides fast response to surge events through internal low impedance discharge path; limits stray surge currents from passing through sensitive circuits, such as the Ethernet PHY device, and also reduces the stress built on PHY and diode bridge by reducing the parasitic significantly in the energy discharging path. AS1100 family implements many design features that minimizes transmission of system common-mode noise on to the UTP (unshielded twisted pair.) Thus, AS1100 family proprietary protected powered device provides superior reliability and circuit protection, especially in EMI / surge / over-voltage critical enviroment for PoE application. AS1124 device was used for generating the conformance report. AS1113 will meet all performance standards as AS1124 does. In order to verify the PD controller functionality of AS1124 according to the IEEE Std Clause 33 Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI), the following sections are included in this report: Protocol Implementation Conformance Statement (PICS) proforma tables for PDs, from IEEE Std , Clause 33, , which is required by the standards, that the suppliers of DTE Power via MDI should complete. Conformance test, describes the key specification parameters defined in Clause 33 for powered devices and its test setup, procedure, and interpretation of test result. Akros products are designed to meet standards; we provide a full Sifos specification test results complying with IEEE Std 802.3af, for powered device used with the physical layers described in IEEE Std Clause 14, Clause 25, and Clause 40. The conducted tests show the device interoperability in general before customers actually implement it into their end system. It will save considerable time and effort and cost on PD evaluation and system level development. PICs Proforma Table for PD A completed proforma table is required for all Data Terminal Equipment suppliers. This section includes all the features supported or unsupported by AS1124 PD controller. It is marked as in the last column if it does support the feature, it is guaranteed by either test or design. Otherwise, it is marked as either N/A for not available, or No for no support. The key parameters requested by customers have been tested and described in the next section. For detailed information on how a particular test was conducted, please contact Akros Application Support. The contact information is listed at the end of this document. Table 1: PD Major Capabilities / Options Item Feature Sub-clause Value/Comment Status Support PDCL PD Classification PD supports classification O Table 2: Powered Device Features Item Feature Sub-clause Value/Comment Status Support PD1 Accept Power On either set of PI conductors M PD2 Polarity insensitive Both mode A and Mode B per table 33- M 7 PD3 Source power The PD will not source power on its PI M PD4 Voltage tolerance Withstand 0V to 57V at the PI M 8/23/ Akros Silicon

4 indefinitely without permanent damage PD5 PD behavior According to state diagram shown in Figure 33-1 PD6 Valid detection signature Presented on each set of pairs defined PD7 PD8 Non-valid detection signature Non-valid detection signature in if not powered via the PI Presented on each set of pairs defined in if not powered via the PI and will not accept power via the PI When powered, present an invalid signature on the set of pairs not drawing power PD9 Valid detection signature Characteristics defined in Table 33-8 M PD10 Non-valid detection Exhibit one or both of the M signature characteristics described in Table 33-9 PD11 Return Class 0 to 3 classification Implement classification selection according to maximum power draw PDCL: M specified in Table PD12 Classification signature As defined in Table PDCL: M PD13 Classification signature One classification signature during PDCL: classification M PD14 PD power supply Operate within the characteristics in M Table PD15 PD turn on voltage PD will turn on at a voltage less than M Von PD16 PD stay on voltage Must stay on for all voltages in the M range of Vport PD17 PD turn off voltage Must turn off at a voltage less than M Vport minimum and greater than Voff PD18 Input average power Applies for input power as specified in M Table averaged over one second PD19 Input inrush current Limited by the PD if Cport is greater M than or equal to 180uF so that Iinrush max is satisfied PD20 Peak operating current Not to exceed Pport max / Vport for more than 50ms max and 5% duty cycle max PD21 Peak current Not to exceed Iport max M PD22 RMS, DC, and ripple Bounded by Irms = [(Idc) 2 +(Iac) 2 ] 1/2 M current PD23 Maximum operating DC Defined by the following equation: M and RMS current Iport_max[mA] = 12950/Vport PD24 PI capacitance during As specified in sub-clause M normal powering mode PD25 Ripple and noise As specified in Table for the common-mode and/or differential pairto-pair noise at the PD PI M PD26 Ripple and noise specification For all operating voltages in the range defined by Table item 1 PD27 Ripple and noise presence Must operate correctly when connected to a PSE generating ripple and noise levels specified in Table 33-5 Item 3 PD28 Power supply turn on / turn off voltage As specified in Table when connected to a PSE through a 20 Ω series resistor M M M M M M M M 8/23/ Akros Silicon

5 PD29 Startup oscillations Shall turn on or off without startup M oscillations and within the first trial at any load value PD30 Classification stability Classification signature will remain valid M within Tclass and remain valid for the duration of the classification period PD31 Back-feed voltage Mode A and Mode B per M PD32 Maintain power signature (current draw) and (AC impedance) M defined in Table PD33 No longer require power Remove both components of maintain power signature M Conformance Test Conformance test was performed over two AS1124 PD devices, which were soldered on AS1100-EV-SPL Rev.2 S/N008 12V and AS1100-EV-ISO.W12T SN010 boards. Taking AS1100-EV-ISO.W12T SN010 board as an example, its schematic, layout, and BOM are copied in this document. Photos of evaluation boards / interface boards and test setup are posted for references. The test results are shared and data analysis is followed in this section. 8/23/ Akros Silicon

6 Schematic, Layout, and BOM Figure 1-1: Schematic of AS1100-EV-ISO.W12T SN010 8/23/ Akros Silicon

7 Figure 1-2: Schematic of AS1100-EV-ISO.W12T SN010 8/23/ Akros Silicon

8 Figure 2: Silk screen top of AS1100-EV-ISO.W12T SN010 Figure 3: Silk screen bottom of AS1100-EV-ISO.W12T SN010 8/23/ Akros Silicon

9 Figure 4: Layout Layer Top of AS1100-EV-ISO.W12T SN010 Figure 5: Layout Layer Bottom of AS1100-EV-ISO.W12T SN010 8/23/ Akros Silicon

10 Figure 6: Layout Layer GND1 of AS1100-EV-ISO.W12T SN010 Figure 7: Layout Layer Signal 1 of AS1100-EV-ISO.W12T SN010 8/23/ Akros Silicon

11 Figure 8: Layout Layer GND2 of AS1100-EV-ISO.W12T SN010 Figure 9: Layout Layer GND3 of AS1100-EV-ISO.W12T SN010 8/23/ Akros Silicon

12 Table 3: BOM of AS1100-EV-ISO.W12T SN010 8/23/ Akros Silicon

13 Evaluation Boards and Interface Boards Used Figure 10: AS1100-EV-SPL Rev.2 S/N008 12V Figure 11: AS1100-EV-SPL Rev.2 S/N008 12V 8/23/ Akros Silicon

14 Figure 12: AS1100-EV-ISO.W12T, SN010 Figure 13: AS1100-EV-ISO.W12T, SN010 Figure 14: Interface board for conformance test Figure 15: Resistive load used 8/23/ Akros Silicon

15 List of Equipment Used and Test Setup Table 4: List of Equipment Used Vendor Model number Description Parameter range HP 8116A Pulse/Function Generator 50MHz HP 34401A Multi-Meter 3A, 200V, 1000V Tektronix TDS7104 Digital Phosphor Oscilloscope 1GHz, 10GS/s Tektronix TDS7054 Digital Phosphor Oscilloscope 500MHz, 5GS/s Fluke 179 True RMS Multi-meter 400mA/10A; 600V/1000V Agilent 6063B System DC Electronic Load 3-240V / 0-10A 250W Agilent 6634B System DC Power Supply 0-100V / 0-1A Sifos PDA-100 PoE Powered Device Analyzer BK Precision 1711A DC-DC Power Supply 60V/2A NI LabView 8.0 Figure 16-1: Test setup one, used in testing PD features listed in Table 5 8/23/ Akros Silicon

16 Figure 16-2: Test setup one, used in testing PD features listed in Table 5 Item PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 Table 5: PD features tested with Sifos PDA-100. Feature Accept power Polarity insensitive Source power Voltage tolerance PD behavior Valid detection signature Non-Valid detection signature Non-valid detection signature Valid detection signature Non-valid detection signature Return Class 0 to 3 classification Classification signature Classification signature 8/23/ Akros Silicon

17 Figure 17: Test setup Two, verification of PD off time response Figure 18: Test setup Three, V/I related measurement The DUT is powered by the digital power supply, with voltage sweeps controlled by either LabView GUI or Visual Basic Interface or manually depending on different measurement requirement. Automatic voltage measurements were 8/23/ Akros Silicon

18 captured using the digital multi-meter set for voltage measurements. Automatic current measurements were made by the in-line digital multi-meter set for current measurements. The software script was used to increment the test voltages and record and store voltage and current measurements. V_I Slope and Offset Voltage calculations are taken with 50 mv steps rather than the prescribed 200 mv steps in other vendors measurement. 8/23/ Akros Silicon

19 Test Result from PDA Tester Table 6-1: PD Conformance test results with Sifos PD Analyzer Sifos Technologies, Inc. PDA-100 Test Results Date: 8/1/2007 class 0 8/1/ :35 RDET CDET IClass CLASS POWER I_max I_min I_avg pass/fail ALT-A, MDI 25.11k 0.085uF 1.8mA W 22.7mA 22.0mA 22.3mA Pass ALT-A, MDI-X 25.09k 0.085uF 1.8mA W 22.6mA 22.0mA 22.3mA Pass ALT-B, MDI 25.02k 0.085uF 1.8mA W 22.7mA 21.9mA 22.3mA Pass ALT-B, MDI-X 25.04k 0.084uF 1.8mA W 22.6mA 21.9mA 22.3mA Pass class1 8/1/ :37 RDET CDET IClass CLASS POWER I_max I_min I_avg pass/fail ALT-A, MDI 25.16k 0.093uF 9.6mA W 22.7mA 21.9mA 22.3mA Pass ALT-A, MDI-X 25.11k 0.085uF 9.6mA W 22.7mA 22.0mA 22.3mA Pass ALT-B, MDI 25.16k 0.085uF 9.7mA W 22.6mA 21.9mA 22.2mA Pass ALT-B, MDI-X 25.18k 0.085uF 9.6mA W 22.6mA 22.0mA 22.3mA Pass class 2 8/1/ :40 RDET CDET IClass CLASS POWER I_max I_min I_avg pass/fail ALT-A, MDI 25.16k 0.089uF 16.9mA W 22.7mA 21.9mA 22.3mA Pass ALT-A, MDI-X 25.11k 0.085uF 16.9mA W 22.7mA 21.9mA 22.3mA Pass ALT-B, MDI 25.13k 0.085uF 16.9mA W 22.7mA 22.0mA 22.3mA Pass ALT-B, MDI-X 25.25k 0.085uF 16.9mA W 22.7mA 21.8mA 22.3mA Pass class 3 8/1/ :41 RDET CDET IClass CLASS POWER I_max I_min I_avg pass/fail ALT-A, MDI 25.13k 0.090uF 25.8mA W 22.6mA 21.8mA 22.2mA Pass ALT-A, MDI-X 25.11k 0.084uF 25.8mA W 22.6mA 22.0mA 22.3mA Pass ALT-B, MDI 25.16k 0.085uF 25.8mA W 22.6mA 21.9mA 22.3mA Pass ALT-B, MDI-X 25.13k 0.085uF 25.8mA W 22.7mA 21.9mA 22.3mA Pass Detection / Classification Data Analysis IEEE 802.3af standard requires the valid detection signature, optional classification of the PD power, and maintain power signature. PD has to be work with any combination of the power port input polarity specified as in sub-clause In Table 6-1, the result shows that the PSE is able to detect the valid PD being connected and the correct power classification in each case, and read back the MPS (Maintain Power Signature) signal as long as there is valid current consumption about 22.3mA (>10mA min required) and Rdet = 25KΩ (< 26.25KΩ max required) and Cdet = 0.09uF (which meets the requirement of minimum 0.05uF). With all the alternative polarity combinations, the PD is also verified performing consistently. In order to check the detection signature requirement over the voltage range specified in Clause 33, the offset voltage was captured with LabView program, setup is shown in Figure 18. The data graph is shown in Figure The offset voltage is 1.31V (< 1.9V max required) and the offset current is 6uA (<9uA max required). Figure 19-2 shows AS1124 detection signature V-I slope (24.4k~25.8k Ohm) is within the valid range of the V-I slope requirement (23.75k~26.25K Ohm). 8/23/ Akros Silicon

20 Detection signature I/V curve Current (ua) V offset voltage Voltage (V) Figure 19-1: AS1124 detection signature offset 8/23/ Akros Silicon

21 Detection Signature V-I slope 40 V_I slope (k Ohm) Valid detection signature V_I slope range Votage (V) Figure 19-2: AS1124 detection signature V-I slope Verification process was also performed under the section of non-valid detection signature. When powered on one set of pair, the PD presents the invalid signature on the other pair. The detection signature resistance should be less than 12 kω or greater than 45 kω, as shown in Table 6-2. Table 6-2: Detection Signature Resistance, Opposite Mode Mode Min (kω ) Max (kω ) Allowed Pass / Fail A kω < Rsig > 45 kω Pass B kω < Rsig > 45 kω Pass 8/23/ Akros Silicon

22 Test Result of PD Operation while Noise Presence from PSE Figure 20: A sample GUI shows that PD operates correctly while noise presence to the PD port Analysis of PD Operation over Noise Presence AC noises was generated by HP functional generator and presented to the power pin through a 47uF capacitor and DC power supply was fed into the PD port through a 1mH inductor, which is a bias tee configuration for adding an AC ripple voltage over the DC power supply. Changed the frequency and amplitude and monitored it with oscilloscope to make sure actual power voltages and ripple stay within specification defined in Clause 33. The alternative mode was checked under the same condition. The device operation was checked with LabView Auto bench test program. The example test result is shown in Figure 20. LEDs in Figure 20 stands for operation status including Vout, Vout regulation and efficiency, green lights mean passing the spec values listed in Figure 20, and if anything fails, the related LED would be red. Each individual test was saved under an excel file that its path was specified in the section Part Name / Number in Figure 20, for an example, the test result at 400Hz and 0.5V peak to peak noise voltage was saved as 400Hz_0.5V. Table 7 shows test result over frequency ranges required, which means operations correct while ripple and noise from PSE is present. 8/23/ Akros Silicon

23 Table 7: PD normal operation when noise from PSE presented on the PD port Modes Frequency Injected Vpp (V) Pass / Fail < 500 Hz 0.5 pass A 500 Hz to 150 khz 0.2 pass 150 khz to 500 khz 0.15 pass 500 khz to 1 MHz 0.1 pass < 500 Hz 0.5 pass B 500 Hz to 150 khz 0.2 pass 150 khz to 500 khz 0.15 pass 500 khz to 1 MHz 0.1 pass Back-feed Voltage Measurements Test setup is shown in Figure 14 and 17. The DUT was powered, and a 100kΩ resistor was placed across the opposite mode (A or B), non-powered terminals. The voltage across the resistor was measured with the digital multimeter set to voltage measurements. The voltage present on the non-powered terminals of the powered PD should be less than 2.8 Volts for any configuration, shown in Table 8. Table 8: Back-feed voltage measurement Powered Mode Back-feed Voltage Pass / Fail A < 0.5 mv Pass B < 0.5 mv Pass The powered DUT did not present a significant back-feed voltage across the non-powered terminals. Power Supply Turn On / Off Analysis The DUT power supply should turn on before the supply voltage reaches Von = 42V at PD Vport, which includes power loss in the cable. The power supply should stay on over the entire Vport range between 36V and 57V. The PD shall turn off at a voltage less than Vport minimum = 36V and greater than Voff = 30V. The test was done with Visual Basic automatic test program. The result is shown in Table 9. It was also correlated with manual tests and Sifos test setup. Power supply turn on / off meet the PD requirement. Table 9: Power supply turn on/off results Mode Class Turn On Voltage (V) Pass/Fail Turn Off Voltage (V) Pass/Fail Pass Pass Pass Pass A Pass Pass Pass Pass Pass Pass Pass Pass B Pass Pass Pass Pass Pass Pass 8/23/ Akros Silicon

24 Summary AS1113 and AS1124 were designed to meet the IEEE Std 802.3af standard and its performance were checked according to the IEEE Std Clause 33 PD conformance proforma table. The tested results of key specification were described in this application note including, detection signature voltage / current offset / V_I slope, classification, accepting power in all combination of polarities specified, power supply turn on / off requirement, maximum backfeed voltage, ripple and noise immunity over wide frequency ranges, and maintain power signature by checking both resistance and capacitance. The tests were performed with the equipment meeting IEEE PSE compliance. Test procedures discribed in Cluase 33 for PDs were followed. Most of test results were gathered by automatic test programs which were manually correlated before capturing the final data. Based on the analysis of test results, both AS1113 and AS1124 PD controllers are interoperable with their interfacing DTE power devices which also satisfy all related conformance statements decribed in IEEE Std 802.3af. Related Documentation 1/ IEEE Computer Society, IEEE Std , Information technology Telecommunications and information exchange between systems Local and metropolitan area networks Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications, Section Two, Clause 33, Page / Brandon Irwin, In House Conformance Report, Akros, CONTACT INFORMATION Akros Silicon Inc SAn Ignacio Ave, Suite 250 San Jose, CA USA Tel: (408) ext. 100 Fax: (916) inquiries: marcom@akrossilicon.com Website: Important Notices Legal Notice Copyright 2007 Akros Silicon TM. All rights reserved. Other names, brands and trademarks are the property of others. Akros Silicon TM assumes no responsibility or liability for information contained in this document. Akros reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services without notice. The information contained herein is believed to be accurate and reliable at the time of printing. Life and Safety Policy Akros products are not authorized for use as critical components in life support systems for surgical implant into the body, or other applications intended to support or sustain life or any other applications whereby a failure of the Akros product could create a situation where personal injury, death or damage to persons, systems, data or business may occur. 8/23/ Akros Silicon