Switched Doherty PAs for 3G Thomas Apel

Transcription

1 Switched Doherty PAs for 3G Thomas Apel 2300 NE Brookwood Parkway Hillsboro, OR

2 Outline Introduction and motivation Pros and Cons Background: Stepped bias and switched periphery Switched Doherty Example PAs Performance improvement techniques Test data Tristate switched Doherty PA in BiHEMT process Conclusion 2

3 Why Use Switched Doherty PAs? CDMA talk-time is strongly influenced by PA current Average PA current is dependent on power efficiency at low power levels (in addition to full power PAE) Improvement in low power PAE requires: a reduction in supply voltage OR an increase in load impedance (compared to full power levels) Load impedance can be changed explicitly (switched) or implicitly (periphery switching) The results reported here use implicit load control to improve low power efficiency 3

4 Pros and Cons Switched Doherty PAs are not easy to implement Z inverter (Zo and insertion phase) Delay line (Zo and insertion phase) Interstage branch impedances ALL MUST BE CORRECT- consistent with final stage segmentation Performance advantages include: High PAE in both low and high power modes No insertion phase discontinuity during mode change Increased load insensitivity and superior 3 rd order reverse IMD due to quadrature operation in high power mode All periphery is used in high power mode External load impedance is same as conventional PA 4

5 Background: Conventional PA with Stepped Bias 1 st GENERATION CONVENTIONAL PA 1-BIT CONTROL ONLY DC QUIESCENT REDUCTION IN LOW MODE POOR LOW MODE PAE DUE TO MISMATCH + Vcc Hi/Lo Step Z int + Vreg BASE BIAS-2 Z Load RF output RF input LP + Vreg BASE BIAS-1 TQ7632 5

6 Background : Conventional PA with Switched Periphery 2 nd GENERATION CONVENTIONAL PA 1-BIT CONTROL BETTER LINEARITY IN LOW MODE THAN STEPPED BIAS POOR LOW MODE PAE DUE TO MISMATCH + Vcc Z int + Vreg BASE BIAS-2A RF input LP + Vreg Hi/Lo Step BASE BIAS-2 Z Load + Vreg BASE BIAS-1 RF output TQ7634 6

7 LOAD LOAD Switched Periphery Load Sharing Q1 Q1 Z LOAD M Z LOAD M Z _ M - 1 LOAD (open) Q2 Z LOAD Q2 Z LOAD HIGH POWER MODE LOW POWER MODE 7

8 LOAD LOAD Switched Doherty Load Sharing M Z LOAD M 2 Z LOAD Q1 Zo =M Z LOAD = 90 Q1 Zo =M Z LOAD = 90 M Z _ M - 1 LOAD M Z LOAD (open) Z LOAD Q2 Z LOAD Q2 Z LOAD HIGH POWER MODE LOW POWER MODE 8

9 Z INVERTER Z INVERTER CDMA Load Sharing Prototype 18 Q2 72 Q2 Z0 = 18 Z0 = 18 6 (open) Q1 4.5 Q1 4.5 DELAY LINE DELAY LINE HIGH POWER MODE LOW POWER MODE 9

10 Constant-K LC Impedance Inverter L C C L= Z 0 / 0, C= ( 0 Z 0 ) -1 10

11 M-derived LC Impedance Inverter L Cs Cs Ls Ls L= Z 0 / 0, Ls= Z 0 (3 0 ) -1, Cs= 3(4 0 Z 0 ) -1 TRAP RESONANCE SET TO 2 nd HARMONIC 11

12 Z INVERTER DELAY LINE Switched Periphery to Switched Doherty + Vcc-1 + BIAS-A + Vcc-1 + BIAS-A + BIAS-B + BIAS-B RF output RF output SWITCHED PERIPHERY SWITCHED DOHERTY 12

13 Z INVERTER DELAY LINE Switched Doherty PA + Vreg BASE BIAS-2A + Vcc RF input + Vreg BASE BIAS-2 Hi/Lo Step + Vreg BASE BIAS-1 RF output 13

14 Z INVERTER DELAY LINE Low Power Mode + Vreg BASE BIAS-2A + Vcc RF input + Vreg OFF BASE BIAS-2 + Vreg BASE BIAS-1 OFF Hi/Lo Step OFF RF output 14

15 Z INVERTER Low Power Mode + Vreg BASE BIAS-2A + Vcc RF input OPTIMUM PERIPHERY AND OPTIMUM LOAD + Vreg BASE BIAS-1 RF output 15

16 Z INVERTER Z INVERTER Contrast with Other Techniques SWITCHED DOHERTY IS DUAL PATH SPECIAL CASE ZL ~ 70 BASE BIAS-2A Z0 ~ 17 BASE BIAS-2A Z0 ~ 17 BASE BIAS-2B RF output (~ 4 ) OFF OFF BASE BIAS-2B RF output (~ 4 ) DUAL PATH ARCHITECTURE HIGH POWER MODE 16

17 Z INVERTER Z INVERTER Contrast with Other Techniques (continued) ZL = OFF OFF BASE BIAS-2A High RF Voltage ZIN ~ 0 BASE BIAS-2A D S Z0 ~ 17 Switch Control RF output (~ 4 ) RF output (~ 4 ) BASE BIAS-2B BASE BIAS-2B DISTORTION IN HIGH POWER MODE SWITCHED DUAL PATH 17

18 Z INVERTER Z INVERTER DELAY LINE DELAY LINE Isolation at Interstage Split + Vcc-1 + BIAS-A + Vcc-1 + BIAS-A + BIAS-B + BIAS-B RF output RF output NO ISOLATION WITH ISOLATION 18

19 PCS 1 ST Generation Switched Doherty 1120 x 1200 um um 2 final 550 um 2 driver external 2 nd harmonic tuning 19

20 PCS 2 ND Generation Switched Doherty 1170 x 1230 um um 2 final 550 um 2 driver internal 2 nd harmonic tuning 20

21 Cellular 2 ND Generation Switched Doherty 1120 x 1470 um um 2 final 550 um 2 driver internal 2 nd harmonic tuning 21

22 FISHBONE BASE Geometry for Low CBC 75% of STANDARD CELL CBC 57% of HAIRPIN CELL Rb SOA is 2X HAIRPIN CELL >1 db gain increase >2 % ha increase 22

23 LOW Zo LINE EQUIVALENT LOW Zo LINE Low Inductance Base Manifold Large base LB ± D LB Low LB ± D LB Low LB ± D LB Lateral manifold contributes to LB A low Zo transmission line can reduce LB This is realized with METAL-2 / BCB / METAL-1 stack Increased shunt capacitance is parasitic result Lumped equivalent model is convenient 23

24 Zo ( ) L (nh/mm) C (pf/mm) Low Interconnect L from Low Zo Lines CHARACTERISTIC Zo INCREMENTAL L and C 100 um GaAs 100 um GaAs 1.3 um BCB 1.3 um BCB 100 um GaAs 1.3 um BCB WIDTH (mm) WIDTH (mm) 24

25 Low Zo Base Manifold - PCS Band LOW POWER CELLS HIGH POWER CELLS 25

26 Low Zo Base Manifold - Cellular Band HIGH POWER CELLS LOW POWER CELLS 26

27 Improved Inductors Standard overlay increases L but looses Q Split and split-overlay increase Q Split singles loose area efficiency Split-overlay and hybrids are the best overall for good Q with area efficiency Split Line Spiral Single Layer Broadside Coupled Split Line Spiral 27

28 Cellular CDMA Performance 28

29 PCS CDMA Performance 29

30 UMTS Cellular WCDMA (Rel.99) 30

31 UMTS PCS WCDMA (Rel.99) 31

32 UMTS Cellular WCDMA (HSDPA) 32

33 UMTS PCS WCDMA (HSDPA) 33

34 Improvement: Tristate Switched Doherty Tristate (2-bit) power control. Build on switched Doherty (2-state) core No Vref needed -- PA operates directly from Vbatt. Enabled with logic interface (< 100uA control) Back compatible into standard sockets Vref pin is replaced by ENABLE logic input. Quiescent currents: 6 ma! ultra low power mode, 25 ma low power mode, and 78 ma high power mode. 34

35 Approach BiHEMT process enables integrated solution: Switched Doherty PA core in HBT VREF elimination with phemt current sources for HBT bias circuits Low current logic phemt RF switch in phemt 35

36 BiHEMT: Co-integration of HBT and phemt 36

37 Tristate PA Module with phemt and HBT Chips 37

38 HBT PA Size Reduced from Original Switched Doherty TRISTATE HBT PA Builds on original architecture HBT PA area is substantially reduced due to removal of complex bias and control circuitry Type-1 or type-6 current mirrors are designed to be driven by the Bias-Control chip ORIGINAL SWITCHED DOHERTY 38

39 Z INVERTER DELAY LINE Switched Doherty PA Core (2 state) + Vreg BASE BIAS-2A + Vcc RF input + Vreg BASE BIAS-2 Hi/Lo Step + Vreg BASE BIAS-1 RF output 39

40 Z INVERTER DELAY LINE Tristate Switched Doherty PA RF input-2 + V_enable (Vreg) + V_enable (Vreg) BASE BIAS-ULP BASE BIAS-2A + Vcc V Mode-2 RF input-1 + V_enable (Vreg) BASE BIAS-2 + V_enable (Vreg) BASE BIAS-1 V-Mode-1 RF output V Mode-2 40

41 Z INVERTER DELAY LINE Ultra-Low Power Mode RF input-2 + V_enable (Vreg) + V_enable (Vreg) BASE BIAS-ULP BASE BIAS-2A RF input-1 OFF + Vcc V Mode-2 OFF + V_enable (Vreg) OFF BASE BIAS-2 + V_enable (Vreg) BASE BIAS-1 V Mode-2 OFF V-Mode-1 OFF RF output 41

42 Simplified View of RF Loading in Tristate PA Switched Doherty 2-state core Tristate Ultra-low power mode uses load from low power mode 2-state RF input switch drives single cell in ultra-low mode 42

43 Separate phemt and HBT Chips phemt BIAS / CONTROL HBT POWER AMPLIFIER 43

44 Bias Control PA Interface 44

45 E/D phemt Bias Control with HBT PA ENABLE E/D phemt Bias Control with RF Input Switch I1 REF I2A REF I2B REF IULP REF + VBATT RF IN OUT-2 MODE (2) OUT-1 MODE (1) Vbe 1 REF Vbe 2A REF Vbe 2B REF Vbe ULP REF I1 mirror I2A mirror I2B mirror IULP mirror Vbias (to HBT) InGaP HBT PA Bias Mirrors 45

46 Standard HBT Bias Reference Circuits VREF required in each case 46

47 Elimination of VREF Current density is mirrored in RF (biased) device I REF set by (V REF Vbe)/RSENSE Precise control of VREF required Low ZSOURCE requires high I MIRROR (and high I REF) TYPE-I BIAS MIRROR REFERENCE CIRCUITS Current density is mirrored in RF (biased) device I REF set by independent of V REF by current source Low Z SOURCE is easily obtained since current flows from Vcc (V BAT) 47

48 D mode Current Sources for Bias Circuits IG D = I REF S phemt I MAX is well behaved (epi dependent) s < 7% (3s = 20%) Geometry scaled to set current 48

49 D mode D mode D mode D mode IG Pull-up for Imax Operation of Reference FET D IG = = S IG < 1 ma IG is dependent on Idss (a wide distribution) s = 16% (3s = 48%) Tight control of IG is not important 49

50 PA Enable VREF PIN used Logic interface VREF not needed 50

51 High Mode Quiescent Current SN (All) Vmode1 (V) 0.30 Vmode2 (V) I_total (ma) Vbatt-2 (V) Vcc1, Vbias, Venable (V) Temp (C) 51

52 Low Mode Quiescent Current SN (All) Vmode1 (V) 3.00 Vmode2 (V) I_total (ma) Vbatt-2 (V) Vcc1, Vbias, Venable (V) Temp (C) 52

53 Ultra-Low Mode Quiescent Current SN (All) Vmode1 (V) 3.00 Vmode2 (V) I_total (ma) Vbatt-2 (V) Vcc1, Vbias, Venable (V) Temp (C) 53

54 Tristate Switched Doherty PA Data Switched Doherty performance extended to ultra-low power mode Quiescent current typically below 6 ma in ultra-low mode Ultra-low mode supports up to +12 dbm with -40 dbc ACPR 54

55 BiHEMT Tristate Switched Doherty 1st GENERATION SWITCHED DOHERTY CORE 2nd GENERATION SWITCHED DOHERTY CORE 55

56 Conclusion Switched Doherty PAs have been realized in both PCS and Cellular bands for linear operation. Power efficiency and linearity are quite good in both high and low power operation. Basic switched Doherty architecture has been extended to Tristate operation with extremely low quiescent current in the lowest power mode BiHEMT process enables integration of phemt and HBT circuitry in Tristate PA Several techniques to improve performance have also been presented: A new HBT geometry provides reduced CBC Use of low Zo interconnect structures to reduce inductance in base feed manifold Use of composite split-line and overlay (broadside coupled) inductors for better area efficiency and good Q CDMA talk-time is significantly increased. 56

57 Acknowledgements Yulung Tang Tarun Juneja Brian MCNamara Tim Kramer Marla Hammond Jeff Damm Eric Reavis 57