WIRELESS power transfer (WPT) by means of electromagnetic

Transcription

1 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY Design Technique for Harmonic-Tuned RF Power Oscillators for High-Efficiency Operation Jinho Jeong and Daeung Jang Abstract In this paper, we propose an advanced nonlinear design technique for harmonic-tuned RF power oscillators, where the feedback, source, and load networks are independently designed based on the derived design equations. They present the transistor with the optimum impedances at fundamental and harmonic frequencies which are determined from the source- and load-pull simulations. The proposed oscillator topology and design equations are verified by the simulations and measurements of RF oscillator using GaN high electron mobility transistors. The fabricated harmonic-tuned oscillator exhibits a maximum efficiency of 83% with an output power of 6.1 W at 2.45 GHz. To the authors knowledge, this corresponds to the best efficiency performance among previously reported RF power oscillators. The phase noise is also as low as 138 dbc/hz at an offset frequency of 1 MHz. Index Terms Inverters, microwave oscillators, phase noise, power amplifiers (PAs). I. INTRODUCTION WIRELESS power transfer (WPT) by means of electromagnetic induction, magnetic resonance coupling, and electromagnetic radiation has been an attractive research topic [1] [3]. It has many industrial applications, including wireless charging of electric vehicles and mobile devices, biomedical systems, and solar power satellites [3] [7]. High-efficiency inverters, or oscillators, which convert dc to ac, are key components in WPT systems because their dc-to-ac conversion efficiencies have a significant effect on the overall efficiency of WPT systems [3], [7]. High-efficiency RF oscillators have many other industrial applications, such as communications, broadcasting, wireless sensor networks, radars, RF heating, and RF lighting [8] [10]. An RF oscillator basically consists of feedback and impedance-matching networks. A feedback network is designed to allow the closed-loop gain to equal unity at an oscillation frequency. Then, the impedance-matching networks are optimized for efficiency and output power. Unfortunately, feedback and matching networks interact with each other, changing initially designed impedances, which leads to the Manuscript received October 14, 2013; revised February 22, 2014 and April 4, 2014; accepted May 15, Date of publication June 13, 2014; date of current version December 19, This work was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean Government (MOE) (2012R1A1B ). The authors are with the Department of Electronic Engineering, Sogang University, Seoul , Korea ( jjeong@sogang. ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TIE need for iterations and tunings in the feedback and matching networks to optimize the performance of the oscillator [11]. A number of nonlinear design techniques have been reported for high-efficiency RF power oscillators. In [12] [15], switching-mode oscillators were presented for high efficiency by operating a transistor as a class-e switch. The feedback and matching networks could be electrically separated by an LC resonator at the drain of the transistor, which is a fundamental component of basic class-e power amplifiers (PAs) [13]. The designed class-e oscillator achieved an efficiency of 69% with an output power (P out ) of 67 W at 410 MHz. However, the efficiency of the switching-mode oscillator degrades with frequency because of the increased switching loss at high frequency [16]. On the other hand, harmonic-tuned oscillators are known to maintain high efficiency at higher frequencies [17] [20]. In [19], high-efficiency PA was designed first with harmonic impedance matching. That is, an output matching network was designed to provide optimum impedances for high-efficiency PA at the fundamental (f 0 ) and harmonic frequencies (2f 0 and 3f 0 ). Then, a feedback network was established between the input and output of the PA to meet the oscillation condition. In order to minimize the effect of the feedback network on the performance of the designed PA, 50-Ω-based directional coupler, phase shifter, and isolator were inserted into the feedback network. These external components led to an increase in the circuit size and a reduction in efficiency. The measured efficiency was 58% with P out of 47.9 W at 2.45 GHz. Recently, a simple nonlinear design technique has been proposed for harmonic-tuned RF power oscillators with high efficiency and compact size in [21]. An LC series resonator was employed in the feedback network to allow for independent design of the feedback and load networks while meeting the oscillation condition and providing optimum load impedances at f 0, 2f 0, and 3f 0. This method needed neither the iterative design nor bulky external components used in [19]. The designed oscillator showed a high efficiency of 80% with P out of 3.3 W at 2.42 GHz. In [21], however, the source impedance was assumed to be short circuited for the simplicity of the design, which limited the performance. It is well known that input terminations at harmonic frequencies as well as at the fundamental frequency have a significant effect on efficiency and P out of RF PAs [22], [23]. Therefore, they should be included in the design of RF oscillators as well to achieve optimum performance. In this paper, we propose an advanced topology for the harmonic-tuned RF oscillator in Section II, which can include the effect of source impedances at the fundamental and IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 222 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015 Fig. 1. Block diagram of the proposed harmonic-tuned RF oscillators. Fig. 2. Load- and source-pull simulations. harmonic frequencies. In addition, the design procedure is proposed with design equations for the optimized oscillator, which allows step-by-step design of the feedback, load, and source networks. The proposed idea is verified by simulations using ideal components. In Section III, the design of a high-efficiency RF oscillator using real components is discussed according to the proposed design technique. The measurement results and performance comparison are presented in Section IV. II. DESIGN TECHNIQUE OF PROPOSED OSCILLATORS Fig. 1 shows the block diagram of the proposed harmonictuned RF oscillator. It consists of transistor, feedback, load, and source networks. Several LC resonators are employed to allow for the independent design of each network. Each resonator has a resonant frequency of f 0, which is equal to the oscillation frequency. Compared with the topology presented in [21], the source network and two LC resonators at the gate side are added in this topology to include the effect of the input terminations at fundamental and harmonic frequencies on the efficiency and output power. A GaN high electron mobility transistor (HEMT; CGH40006P model by Cree Inc.) is selected as a transistor to verify the proposed design technique. A nonlinear transistor model provided by the vendor is used for the simulation. Its accuracy has already been verified in many publications [21], [24], [25]. The center frequency f 0 is chosen as 2.45 GHz, which belongs to the ISM band. The simulation is performed at the gate and drain bias voltages of V GG = 2.8 V and V DD =28V, respectively. 1) Optimization of Harmonic-Tuned PA: Asafirststepin the design, a harmonic-tuned PA is optimized for high power and high efficiency by finding the optimum load and source impedances Z Sopt and Z Lopt as shown in Fig. 2 [25]. For Fig. 3. Load-pull contours for P out (solid) and PAE (slotted) at (a) f 0, (b) 2f 0, and (c) 3f 0. The blank dot indicates the selected impedance for the oscillator design. (d) Simulated P out, gain, and PAE as a function of P avs. this purpose, load- and source-pull simulations are carried out at f 0 =2.45 GHz for the available source power (P avs ) of 30 dbm. The optimum source impedance at f 0 (Z Sopt,1 )isset to be 9+j17 Ω, which is selected from the source-pull simulation. Z Sopt,2 and Z Sopt,3 are fixed to j200 Ω and j200 Ω, respectively. Fig. 3(a) (c) shows the load-pull contours of P out and the power-added efficiency (PAE) on Smith charts at f 0, 2f 0, and 3f 0. The contours at one frequency are obtained while the transistor is terminated with optimum load impedances at the other two frequencies [24]. Note that, as demonstrated in

3 JEONG AND JANG: HARMONIC-TUNED RF POWER OSCILLATORS FOR HIGH-EFFICIENCY OPERATION 223 Fig. 4. Synthesis of the feedback and load network at f 0. This circuit is equivalent to the one in Fig. 1 at f 0. Fig. 3(b) and (c), the output power and efficiency are not very sensitive to the harmonic load impedances as long as they are inductive. The optimum load impedance at each frequency is determined considering both P out and PAE as follows: Z Lopt,1 =16+j26 Ω, Z Lopt,2 = j26 Ω, and Z Lopt,3 = j15 Ω at f 0, 2f 0, and 3f 0, respectively. They are indicated by the blank dot in Fig. 3(a) (c). Then, a harmonic-balance (HB) simulation is performed to predict P out and PAE performance of the optimized PA in which the transistor is terminated with the optimum impedance as shown in Fig. 2. The optimized PA exhibits a maximum PAE of 85.3%, a drain efficiency (DE) of 86.8%, and a P out of 39.2 dbm at P avs =30 dbm, as shown in Fig. 3(d). These P out and DE correspond to the best values that can be achieved when the harmonic-tuned oscillator is designed using the same transistor. 2) Synthesis of the Feedback Network: LC resonators in Fig. 1 are used to verify the proposed topology by simulations, so they are assumed to be ideal. Then, at f 0,the circuit in Fig. 1 can be simplified to the one in Fig. 4. The feedback and load networks in Fig. 4 are then synthesized so that the transistor can preserve the same fundamental voltages and currents at the gate and drain (V in, V out, I in, and I out in Fig. 2) as those in the optimized PA [15], [21]. These voltages and currents are computed from HB simulation of the optimized PA at P avs =30 dbm as follows: I in =0.421e j122o, V in = 0.696e j54.3o, I out =1.02e j25.2o, and V out =31.1e j33.2o.a π- ort -type embedding network can be derived from these terminal voltages and currents. In this paper, the π-network is chosen as shown in Fig. 4. Then, the elements B 1, G 1, B 2, and B 3 in Fig. 4 are determined by the following equations [15]: [ ] [ ] 1 G1 Re{Vout } Im{V = out } B 1 Im{V out } Re{V out } [ ] Re{Iin + I out } + B 3 Im{V in } (1a) Im{I in + I out } B 3 Re{V in } [ ] [ ] 1 B2 Im{Vout } Im{V in } Im{V in } B 3 = Re{V in } Re{V out } Re{V in } [ Re{Iin } Im{I in } ]. (1b) The calculated values are B 1 = , G 1 =0.0169, B 2 = , and B 3 = Reactive parts B 1, B 2, and B 3 constitute the feedback network, while real part G 1 forms the load network at f 0. The load network at 2f 0 and 3f 0 will Fig. 5. Finalized oscillator topology with π-type feedback network. The ideal directional coupler and external source V ex are included in the feedback network for the oscillator simulation. be determined next. The corresponding circuit elements are calculated to be L 1 =4.53 nh, R 1 =1/G 1 =59.3 Ω, L 2 = 4.81 nh, and C 3 =1.76 pf at f 0 =2.45 GHz. 3) Design of the Load Network: Substituting the designed feedback network into the circuit in Fig. 1, we can obtain the circuit in Fig. 5. This circuit is equivalent to the proposed topology shown in Fig. 1 at not only fundamental but also harmonic frequencies. As mentioned previously, the load network is designed to provide R 1 at f 0, i.e., Z OM,1 = R 1. (2a) Note that Z L is the parallel connection of Z OM and Z FD as shown in Fig. 5. Therefore, the real part of 1/Z Lopt,1 is formed by the load network (1/Z OM,1 ) and the imaginary part by the feedback network (1/Z FD ). The ideal series LC resonator SR 2 at the drain side in the feedback network provides an open circuit at harmonic frequencies, so that the feedback network does not affect Z L at those frequencies. Therefore, the load network can be designed at 2f 0 and 3f 0 to provide Z OM,i = Z Lopt,i, where i =2, 3. (2b) Equation (2) allows the output of the transistor to be terminated with the optimum load impedance Z Lopt. 4) Design of the Source Network: Similarly, the source network can be designed to provide optimum impedance. Fundamental source impedance Z IM,1 in Fig. 5 can be arbitrarily selected because there is a parallel LC resonator (PR 1 ) at the gate presenting an open circuit at f 0. That is, Z IM,1 = arbitrary. (3a) The gate of the transistor in Fig. 5 is terminated at f 0 with optimum impedance (Z Sopt,1 ) due to the aforementioned designed feedback network. Owing to ideal resonators SR 1 and PR 1, the source network at harmonic frequencies can be designed to satisfy that Z IM,i = Z Sopt,i, where i =2, 3. (3b) Equation (3) allows the input of the transistor to be terminated with the optimum source impedance Z Sopt.

4 224 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015 TABLE I PERFORMANCE OF THE SIMULATED OSCILLATOR 5) Simulation of the Designed Oscillator: The finalized oscillator topology in Fig. 5 is simulated using ideal values for L, C, Z OM, and Z IM. For oscillator analysis, an ideal directional coupler with excitation signal V ex is inserted in the feedback network, which allows us to check the injection and feedback signals (V inj and V fb, respectively). Then, the frequency and amplitude of V ex are determined in the HB simulation to meet the oscillation condition, i.e., the loop gain V fb /V inj is unity [17]. It was found from this simulation that the circuit in Fig. 5 oscillates at f 0 =2.45 GHz with P out of 39.1 dbm and an efficiency of 85.3%, which corresponds to almost the same result obtained in the optimized PA as compared in Table I. This result indicates that the transistor in the oscillator in Fig. 5 is operating with optimum source and load impedances at f 0, 2f 0, and 3f 0 as in the optimized PA in Fig. 2. In summary, the proposed oscillator in Fig. 5 can be optimally designed by using (1) (3), which allows the step-bystep design of the feedback, load, and source networks without interacting each other. III. DESIGN OF OSCILLATORS USING REAL ELEMENTS In Section II, the proposed oscillator is validated by the simulation. This section discusses the complete design of the proposed oscillator at 2.45 GHz using practical circuit elements. A. Simplification of the Oscillator Topology The LC resonators in Fig. 5 were assumed to be ideal with infinite Q-factors. In practice, however, they have finite Q-factors, leading to degradation in the performance. Therefore, it is desirable to reduce the number of LC resonators. Fortunately, we can remove one of the resonators in the feedback network without degrading the performance. In this paper, the resonator SR 2 is removed (i.e., replaced with a short circuit) as shown in Fig. 6. Then, the load network should be modified so that the transistor can still look into the optimum impedance Z Lopt.TheremovalofSR 2 does not cause any change in the impedance Z L at f 0, so that the modified load network in Fig. 6 is designed to have the same fundamental impedance as (2a), i.e., Z OM,1 = Z OM,1. (4a) On the other hand, the impedance Z L seen by the transistor at 2f 0 and 3f 0 is affected by Z FD, i.e., 1/Z L is given by 1/jωL 1 +1/(jωL 2 +1/jωC 3 ) due to the remaining resonator SR 1. The load network should be modified to satisfy that Z L,2 = Z Lopt,2 and Z L,3 = Z Lopt,3. The modified load Fig. 6. Oscillator topology used in the real implementation. impedances Z OM,2 and Z OM,3 are simply obtained by solving the following equation: 1 Z OM,i =, where i =2, 3. (4b) Z FD,i Z Lopt,i The source network in Fig. 5 should be designed to provide the optimum input harmonic terminations. It was found from the source-pull simulation that, for the transistor used in this work, high reactive impedances belong to the optimum impedance region for Z Sopt,2 and Z Sopt,3. Thus, an open circuit is selected as Z Sopt,2 and Z Sopt,3. Then, the parallel LC resonator PR 1 can be removed as shown in Fig. 6. Note that, in general, the source network and PR 1 in Fig. 5 cannot be removed for other transistor technologies and operating frequencies [22]. As compared in Table I, the simulated performance of the circuit in Fig. 6 is almost equal to that of the circuit in Fig. 5. Therefore, the circuit in Fig. 6 is implemented using real circuit elements. B. Implementation of the Feedback Network The LC resonator SR 1 in the feedback network degrades the phase noise performance as well as efficiency due to its low Q-factor. In order to alleviate this problem, a half-wave microstrip resonator is adopted in this work to replace SR 1, which, in general, exhibits higher Q-factors than LC resonators [26]. It has bandpass performance at f 0, which is the same as that of the LC resonator. However, it passes the signal at harmonic frequencies as well, which is undesirable for our application. To suppress the harmonics, a stepped impedance resonator (SIR) is utilized as shown in Fig. 7(a), where Z 01 and Z 02 are selected as 50 and 70 Ω, respectively. The high ratio of Z 02 /Z 01 reduces the length of the resonator [27]. In order to couple the resonator to the microstrip feedline, a parallel coupled line is used at both ends of the resonator as shown in Fig. 7(b). Each coupled line is designed to have even- and odd-mode impedances of Z 0e =70Ωand Z 0o =38Ω, respectively. The electrical length θ is determined to be 40 from the simulation. Fig. 7(c) shows the simulated S 11 and S 21 in decibels of the designed SIR with a fundamental resonance frequency f 0 of 2.45 GHz. As expected, the harmonic resonance frequencies deviate from 2f 0 and 3f 0 owing to the use of the SIR. Instead, the SIR exhibits reactive impedances at 2f 0 and 3f 0. However, this nonopen impedance at the harmonics can lead

5 JEONG AND JANG: HARMONIC-TUNED RF POWER OSCILLATORS FOR HIGH-EFFICIENCY OPERATION 225 Fig. 8. Feedback network using distributed elements. Fig. 9. Load network for harmonic impedance matching. Fig. 7. Half-wave resonator. (a) SIR. (b) SIR with parallel coupled section. (c) Simulated magnitude of S 11 and S 21 of the designed SIR. (d) Simulated phase of S 11 and S 21 of the designed SIR. to performance degradation of the oscillator. For the simulation of the oscillator with SIR, a 50-Ω line with an electrical length of 290 at f 0 was added to the SIR to compensate for nonzero phase delay by the SIR [the phase shift in S 21 in Fig. 7(d)] so that the circuit can oscillate at f 0. The oscillator simulation yields a P out of 38.8 dbm and an efficiency of 81.6%. This slight performance degradation can be recovered by modifying Z OM,2 and Z OM,3, considering the reactive impedances of the SIR at 2f 0 and 3f 0 and the effect of the additional 50-Ω line. The simulation with modified Z OM,2 of j34 Ω and Z OM,3 of j39 Ω leads to the recovery of the performance, i.e., P out of 39.1 dbm and efficiency of 83.6%, as shown in Table I. Lumped elements used in the feedback network also have the drawback of low Q-factors degrading the performance. To alleviate this problem, they can be also implemented by using transmission lines. That is, the shunt inductance L 1 is synthesized with a short-ended stub (TL F 1 ), the series inductance L 2 with a high-impedance line (TL F 2 ), and the shunt capacitance C 3 with an open stub (TL F 3 ) as depicted in Fig. 8. Fig. 10. Schematic of the implemented oscillator. Dimensions of microstrip lines are denoted by width/length in millimeters. In the SIR, S represents the spacing (in millimeters) of the coupled line. C. Implementation of the Load Network The load network should be configured to present optimum load impedance as shown in Fig. 9. Node A is designed to be virtually grounded at 2f 0 and 3f 0, assuming that Z OM,2 and Z OM,3 are purely inductive. Then, a single transmission line TL 1 is used to match the impedances at 2f 0 and 3f 0. This was possible because the optimum impedance at both 2f 0 and 3f 0 covers a wide range of inductive regions and are close to each other as shown in Fig. 3(b) and (c) [21]. TL 3 and TL 5 allow A to be virtually grounded at 2f 0, where TL 3 is quarter-wave long at f 0 and the open stub TL 5 is quarter-wave long at 2f 0. The open stub TL 2 with quarter-wave length at 3f 0 provides A with a virtual ground at 3f 0.TL 3 is used as part of a bias circuit with open stub TL 4 of quarter-wave length at f 0. The remaining matching circuit is finally designed to provide Z OM,1 at f 0. D. Final Design The design of the oscillator was completed using a 20-milthick Taconic TLY-5 substrate with a dielectric constant of 2.2. Fig. 10 shows the complete design of the oscillator. The

6 226 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015 Fig. 11. Simulated results of the circuit of Fig. 10. (a) Load impedances experienced by the transistor (Z L in Fig. 10) atf 0, 2f 0, and 3f 0. Blank dots and crosses represent the impedances by the load-pull simulation and the designed oscillator (the circuit in Fig. 10), respectively. (b) Waveform of the drain-to-source voltage and current. Fig. 13. Measured efficiency (η), output power (P out), and oscillation frequency (f 0 ) as a function of (a) gate bias voltage at a drain bias voltage of 30 V and (b) drain bias voltage at a gate bias voltage of 4.0 V. Fig. 14. Measured spectrum as a function of offset frequency at V GG = 4.0 V and V DD =30V. The resolution and video bandwidths are 3 khz and 100 Hz, respectively. Fig. 12. Photograph of the fabricated oscillator. feedback network is implemented with distributed elements, such as lines, stubs, and a half-wave resonator, except for the dc blocking capacitor (3.3 pf). An electromagnetic simulation is performed to accurately predict the performance of the oscillator. The oscillation simulation is carried out on the circuit in Fig. 10 using ideal coupler and external source as shown in Fig. 5. It shows that the circuit oscillates at f 0 =2.45 GHz. In this simulation, the load impedance (Z L in Fig. 10) is Fig. 15. Measured output power spectrum at V GG = 4.0 V and V DD =30V. computed by taking the ratio of the drain voltage to current at each harmonic frequency while the circuit is oscillating at f 0. Fig. 11(a) shows the comparison between the computed

7 JEONG AND JANG: HARMONIC-TUNED RF POWER OSCILLATORS FOR HIGH-EFFICIENCY OPERATION 227 TABLE II COMPARISON OF THE REPORTED HIGH-EFFICIENCY OSCILLATORS load impedances in this simulation and the optimum load impedances determined from the load-pull simulation. This figure ensures that the transistor in the designed oscillator is operating with the optimum load impedances. The simulated drain voltage and current waveforms are presented in Fig. 11(b). The waveforms do not seem to be an optimum because there are somewhat long overlaps between the voltage and the current. That is caused by the parasitic elements of the transistors. The simulated P out is 38.1 dbm with an efficiency of 80.0% at f 0. This simulation performance includes the effect of the losses due to microstrip lines (conductor and dielectric losses) and parasitics of the lumped capacitors. These simulation results demonstrate that the load and feedback networks are optimally designed to allow high-efficiency operation. IV. MEASUREMENTS Fig. 12 shows the fabricated oscillator with the circuit size of 6cm 11 cm. It was mounted on an aluminum heat sink. In order to suppress the parasitic oscillations at low frequencies, several capacitors in the range of nanofarads to microfarads are added in the gate and drain bias lines. Fig. 13 shows the measured P out, efficiency η, and oscillation frequency f 0 as a function of V GG and V DD, respectively. It should be noted that no circuit tunings were made on the fabricated oscillator in the measurements. In Fig. 13(a), the oscillation frequency was varied only by 2 MHz, while V GG changes from 4.2 to 2.2 V, which corresponds to a much lower frequency variation compared with that in [21], implying good frequency stability over V GG variation. P out changed only by 0.7 db with V GG, which is because the transistor in the oscillator operates at almost saturated powers. On the other hand, P out is a strong function of V DD as illustrated in Fig. 13(b), which is the same case for the PAs. The fabricated oscillator shows P out of 37.6 dbm and efficiency of 78.7% with an oscillation frequency of GHz at V GG = 2.8 V and V DD =28V, which are very close to the simulation results. The maximum efficiency of 83.1% was achieved at V GG = 4.0 V and V DD =30 V with P out of 37.8 dbm and f 0 =2.448 GHz, as shown in Fig. 13. The phase noise performance was also measured using an Agilent signal analyzer N9020A. Fig. 14 shows the measured output spectrum at the bias condition for maximum efficiency, i.e., V GG = 4.0 V and V DD =30V. The phase noise is as low as 138 dbc/hz at a 1-MHz offset. Fig. 15 shows the measured output power spectrum at the same bias condition. The third harmonic is largest and 50 db below the fundamental frequency, so the harmonics are effectively suppressed. An isolator (or circulator) with bandpass characteristics, which is usually placed at the output of PAs and oscillators to protect the transistors and to improve frequency stability over the load variation, can further suppress the harmonic powers. Table II compares the performance of the reported highefficiency RF oscillators. The designed oscillator in this work exhibits the best efficiency performance among high-efficiency oscillators designed using both switching and harmonic tuning methods. It is worthwhile to note that P out and efficiency were improved by 2.7 db and 2%, respectively, compared with the oscillator using the same device at the same frequency [21]. The phase noise was also improved by 15 db owing to the use of an SIR instead of an LC resonator. These results prove the validity of the proposed nonlinear design technique of the harmonic-tuned oscillator. The figure of merit (FoM) is also included in the table, showing the good performance of the designed oscillator in terms of efficiency and phase noise [28]. V. C ONCLUSION In this paper, the design technique of a harmonic-tuned RF oscillator has been proposed, and a high-efficiency oscillator at 2.45 GHz has been designed using GaN HEMTs. The fabricated oscillator showed an excellent performance in output power, efficiency, and phase noise. The proposed technique can be effectively applied to the design of RF power oscillator ICs because it allows good agreement between simulation and measurement without circuit tunings after fabrications. It can be very valuable for high-efficiency RF signal generation for many industrial applications.

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Solid-State Circuits Conf., 2005, pp Jinho Jeong received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1997, 1999, and 2004, respectively. From 2004 to 2007, he was a Postdoctoral Scholar with the University of California at San Diego, La Jolla, CA, USA, where he was involved in the design of high-efficiency and highlinearity RF power amplifiers (PAs). In 2007, he joined the Department of Electronics and Communications Engineering, Kwangwoon University, Seoul. Since 2010, he has been with the Department of Electronic Engineering, Sogang University, Seoul. His research interests include monolithic microwave integrated circuits, THz integrated circuits, high-efficiency/high-linearity PAs and oscillators, and wireless power transfers. Daeung Jang received the B.S. degree in biomedical engineering from Yonsei University, Wonju, Korea, in He is currently working toward the M.S. degree in the Department of Electronic Engineering, Sogang University, Seoul, Korea. His research interests include wireless power transfer and linearization of power amplifiers.