Review Paper on Low Power VLSI Design Techniques

Transcription

1 Review Paper on Low VLSI Design Neha Thakur 1, Deepak Kuar 2 1 Assistant Professor, ECE Deptt., SRMS WCET, Bareilly, India 2 Assistant Professor, ECE Deptt., Raa University, Kanpur, India 1 nehathakurec@gail.co, 2 deepakpatel03@gail.co, Abstract: Low power has eerged as a principal thee in today s world of electronics industries. dissipation has becoe an iportant consideration as perforance and area for VLSI Chip design. With shrinking technology reducing power consuption and over all power anageent on chip are the key challenges below 100n due to increased coplexity. For any designs, optiization of power is iportant as tiing due to the need to reduce package cost and extended battery life. For power anageent leakage current also plays an iportant role in low power VLSI designs. Leakage current is becoing an increasingly iportant fraction of the total power dissipation of integrated circuits. This paper describes about the various strategies, ethodologies and power anageent techniques for low power circuits and systes. Future challenges that ust be et to designs low power high perforance circuits are also discussed. the past decade to address the continuously aggressive power reduction requireents of ost of the high perforance. The basic techniques for low power design such as: clock gating for reducing dynaic power, ultiple threshold voltage (ulti-vt) to decrease leakage current, are well-established and supported by existing tools [17]. Fro Figure 1 we can analyze how any changes takes place in circuit design using power dissipation [15]. Keywords: Dissipation, low power, process nodes, leakage current, power anageent. I. INTRODUCTION The advantage of utilizing a cobination of low-power coponents in conjunction with low-power design techniques is ore valuable now than ever before. Requireents for lower power consuption continue to increase significantly as coponents becoe battery-powered, saller and require ore functionality. In the past the ajor concerns for the VLSI designers was area, perforance and cost. consideration was the secondary concerned. Now a day s power is the priary concerned due to the rearkable growth and success in the field of personal coputing devices and wireless counication syste which deand high speed coputation and coplex functionality with low power consuption. The otivations for reducing power consuption differ application to application. In the class of icro-powered battery operated portable applications such as cell phones, the goal is to keep the battery lifetie and weight reasonable and packaging cost low. For high perforance portable coputers such as laptop the goal is to reduce the power dissipation of the electronics portion of the syste to a point which is about half of the total power dissipation. Finally for the high perforance non battery operated syste such as workstations the overall goal of power iniization is to reduce the syste cost while ensuring long ter device reliability. For such high perforance systes, process technology has driven power to the fore front to all factors in such designs. At process nodes below 100 n technology, power consuption due to leakage has joined switching activity as a priary power anageent concern. There are any techniques [15] that have been developed over Figure 1: Evolution in dissipation[15] II. LOW POWER STRATEGIES There (Table I)) are different strategies available at different level in VLSI design process for optiizing the power consuption: Design Level Operating Syste Level Software level Architecture level Circuit/Logic level Technology Level Table I. Strategies for low power designs Strategies Portioning, down Regularity, locality, concurrency Pipelining, Redundancy, data encoding Logic styles, transistor sizing and energy recovery Threshold reduction, ulti threshold devices Effective power anageent is possible by using the different 14

2 strategies at various levels in VLSI Design process. So designers need an intelligent approach for optiizing power consuptions in designs. III. POWER DISSIPATION BASICS In a circuit three coponents are responsible for power dissipation: dynaic power, short-circuit power and static power. Out of these, dynaic power or switching power is priarily power dissipated when charging or discharging capacitors and is described below [5, 6]: P dynaic = C L Vdd 2 α f (1) Where C L : Load Capacitance, a function of fan-out, wire length, and transistor size, Vdd: Supply, which has been dropping with successive process nodes, α: Activity Factor, eaning how often, on average, the wires switch, f: Frequency, which is increasing at each successive process node. Static power or leakage power is a function of the supply voltage (Vdd), the switching threshold (Vt), and transistor sizes (Figure2). As process nodes shrink, leakage becoes a ore significant source of energy use, consuing at least 30% of total power [2]. Crowbar currents, caused when both the PMOS and NMOS devices are siultaneously on, also contribute to the leakage power dissipation [17]. Most circuit level iniization techniques focus only on Sub threshold leakage reduction without considering the effects of gate leakage [15].For this MTCMOS schee [4] has been proposed for reduction of sub threshold leakage current in sleep ode. Figure-2 shows the various coponents responsible for power dissipation in CMOS. reduction offers the ost effective eans of iniizing power consuption. Without requiring any special circuits and technologies, a factor of two reduction in supply voltage yields a factor of four decreases in power consuption. Unfortunately, there is speed penalty for supply voltage reduction and delays drastically increase as Vdd approaches to the threshold voltage Vt of the device. The approach to reduce the supply voltage without loss in throughput is to odify the threshold voltage of the devices. Reducing the Vt allows the supply voltage to be scaled down without loss in speed.the liit of how low low the Vt can go is set by the reqireent to set adequate noise argins and control the increase in the subtreshold leakage current [6,8,10]. Table II. Low power techniques used today [1, 2] Traditional Frequency Dynaic Reduction Efficient Frequency Leakage power reduction Miniize usage of low Vt cells Back Biasing Other reduction Multi Oxide devices Miniize capacitance circuits Supply Device Threshold Supply Island Reduce Oxide Thickness Use Fin FET 4.2. Physical Capacitance 15 IV. Figure 2 Dissipation in CMOS [4] LOW POWER DESIGN SPACE Fro the above section it is revealed that there are three degrees of freedo in the VLSI design space :, Physical Capacitance and data activity. Optiizing for ore power entails an attept to reduce one or ore of these factors. This section briefly describes about their iportance in power optiization process Because of its quadratic relationship to power, voltage Dynaic power consuption depends linearly on the physical capacitance being switched. So, in addition to operating at low voltages, iniizing capacitances offer another technique for iniizing power consuption.the capacitances can be kept at a iniu by using less logic, saller devices, fewer and shorter wires[6,8,10]. As with voltage, however, we are not free to optiize capacitances independently, for exaple reducing device sizes reduces physical capacitance, but it also reduces the current drive of the transistor aking the circuit operate ore slowly Switching Activity There are two coponents to switching activity : F clk which deterines the average periodicityof data arrivals and E(sw)

3 which deterines how any transitions each arrival will generate[14]. E(sw) is reduced by selecting proper algoriths architecture optiization, by proper choice of logic topology and by logic level optiization which results in less power[15]. The data activity E(sw) are cobined with the physical capacitance C to obtained switch capacitance C sw =C.E(sw),which describes the average capacitance charge during each data period1/fclk which deterines the power consued by CMOS circuit[9]. [9]. When selecting a technology to optiize the power for a given design, you ust take both aspects into consideration: the need to use a saller geoetry to reduce active power and the need to use a low-leakage variant to reduce leakage. V. POWER MINIMIZATION TECHNIQUES This section addresses (TABLE II) the different approaches to iniize the power at different levels: 5.1. Reducing Chip and package capacitance This can be achieved through process developent such as SOI with partially or fully depleted wells, CMOS scaling to subicron device sizes and advanced interconnect substrates such as ulti chip odule (MCM). This approach can be very effective but is also very expensive [15, 19] Scaling the supply voltage ( Scaling) This approach can be very effective in reducing the power dissipation, but often requires new IC fabrication processing [13] Using power anageent strategies Effective power anageent involves selection of the right technology, the use of optiized libraries, IP (intellectual property), and design ethodology [1, 19]. Figure-3 shows the effective power anageent strategy The Role of Technology Selection: Proper technology selection is one of the key aspects of power anageent [1]. The goal of each technology advanceent is to iprove perforance, density, and power consuption. The typical approach in developing a new generation of technology is to apply constant-electric-field scaling. Process designers scale both the applied voltage and the oxide thickness to aintain the sae electric field [13,16]. This approach reduces power by about 50% with every new technology node However, as the voltage gets saller, the threshold voltage also ust scale down to eet the perforance targets of that technology. This scaling unfortunately increases the sub threshold current and hence the leakage power. To overcoe this constraint, process engineers no longer apply constant-field scaling for processes of 65 n or saller; instead, they used a ore generalized for of scaling. Because it is ipossible to optiize a technology for both perforance and leakage at once, each technology usually has two variants. One variant ais for high perforance, and the other shoots for low leakage. The priary differences between the two are in the oxide thickness, supply voltage, and threshold voltage. The technology variant with the thicker gate oxide ais for low-leakage design and ust support a higher voltage to achieve a reasonable perforance 16 Figure 3: Technology selection for [9] effective power anageent Circuit-Design : After selecting technology, the focus is on design techniques to optiize power. (Figure 5). One has to start by selecting the appropriate logic gate fro the standard cell library. Each gate in a standard cell library uses the sallest transistors and has ultiple versions with different drive strengths, sizes, delays, ultiple-threshold voltage and power consuption. Because the ain paraeter for controlling active power is the power-supply voltage, cell designers typically design and characterize the gates to operate at voltages as uch as 30% lower than the power-supply voltage [1]. Figure4: Trade off between leakage and Lowering the power-supply voltage produces saller currents, resulting in ore delay. However, this slowdown is acceptable if the design is not pushing the edges of a given technology. Increasing the threshold voltage reduces the leakage current in the device. Leakage power also controlled by designing logic

4 gates with ultiple-threshold-voltage devices [16], including standard high and low threshold voltage devices. Figure-4 shows the variation of gate delay Vs leakage power CAD Methodologies and Technique: Today s EDA tools effectively support these power-anageent techniques [3]. They also provide additional power savings during ipleentation. Low power VLSI designs can be achieved at various levels of the design abstraction fro algorithic and syste levels down to layout and circuit levels. Table III. Trade off associated with power anageent techniques Reduction Benefit Technique Multi Vt optiizati on Multi supply voltage Shut off Dynaic and adaptive frequency scaling Substrate Biasing 17 Tiing Area Penalty Penalty Archite cture Methodology Ipact Desig n Verifi Iple cation entation Little Little Low Low None Low Little Little Low Low None Low Large Soe Little High Low Huge Soe Soe High High High High Large Soe Soe High High High High Large Soe Soe None None High 5.4. Low anageent in Physical Design Physical design tools interpret the power intent and ipleent the layout correctly, fro placeent of special cells to routing and optiization across power doains in the presence of ultiple corners, odes, and power states, plus anufacturing variability [2, 3]. An increasingly coon technique to reduce power in physical design is the use of ultiple voltage islands (doains), which allows soe blocks to use lower supply voltages than others, or to be copletely shut off for certain odes of operation [6].s are a significant source of dynaic power usage. Low-power clock tree synthesis (CTS) strategies [5, 6] include lowering overall capacitance and iniizing switching activity to achieve power saving. However, getting the best power results fro CTS depends on the ability to synthesize the clocks for ultiple corners and odes concurrently in the presence of design and anufacturing variability, and in ulti-voltage flows [8]. gating technique is effective for reducing leakage power by teporarily turned off the circuit [17, 8]. This teporary shutdown tie can also call as "low power ode" or "inactive ode". When circuit blocks are required for operation once again they are activated to "active ode". Shutting down the blocks can be accoplished either by software or hardware. Now-a-days a dedicated power. anageent controller is used for this purpose [17]. Table-3 gives the trade-off associated with the various power anageent techniques [17]. VI. CONCLUSION The need for lower power systes is being driven by any arket segents. Unfortunately designing for low power adds another diension to the already coplex design proble and the design has to be optiized for power as well as Perforance and Area. In conclusion various issues and ajor challenges regarding low power designs are:- 1 Technology Scaling: It relates with the following factors like: Capacitance per node reduces by 30%, Electrical nodes increases by 2X, Die size grows by 14% (Moore s Law), Supply reduces by 15% and Frequency Increases by 2X. To eet these issues relatively 2.7 X active power will increase. 2 Leakage power: To eet frequency deand Vt will be scaled which results high leakage power. A low voltage / low threshold technology and circuit design approach, targeting supply voltage around 1V and operating with reduced thresholds. 3 Dynaic power anageent techniques, varying supply voltage and execution speed according to the activity easureent. 4 Low power interconnect, using advance technology, reduced swing or activity approach. 5 Developent of power conscious techniques and tools for behavioral synthesis, logic synthesis and layout optiization. 6 saving techniques that recycle the signal energies using the adiabatic switching principals rather the dissipating the as a heat and proising in certain applications where speed can be trades for low power. VII. REFERENCES [1] Michael Keating, David Flynn, Robert Aitken, Ala Gibsons and Kaijian Shi, Low Methodology Manual for Syste on Chip Design, Springer Publications, New York, [2] Creating Low- Digital Integrated Circuits The

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