Towards a Language Based Synthesis of NCL. circuits
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1 Towrs Lnguge Bse Synthesis of NCL Ciruits Hemngee K. Kpoor, Ahinv Asthn, Toms Krilvičius, Wenjie Zeng, Jieming M n K Lok Mn Astrt This pper is n ttempt to provie lnguge front- to synthesise synhronous ontrol iruits using NCL tehnology. The trget implementtion eing ely insensitive (DI), the speifition lnguge shoul e DI s well. Dely Insensitive Sequentil roesses (DIS) is proess lger where the ehviour of synhronous ontrol logi loks is epresse y the proesses. We show tht one n onfine the orphn pths in n NCL implementtion y eomposing the lnguge epressions. A few si DIS onstruts hve een suessfully mppe to NCL n smll ses stuies performe. This is step towrs n lterntive synthesis pth for NCL iruits. Ine Terms Speifition lnguges, logi esign, integrte iruits I. INTRODUCTION WITH reent vnes in the fiel of hip mnufturing tehnology, lthough pking ensity of logi on silion wfer hs inrese tremously, t the sme time evies re pprohing their physil limits in terms of imensions s well s elys. Effet of elys is eoming more prominent over the timing issues of esign. With eresing imensions of evies there eists possiility of inrese power ensity. Ciruits tht re insensitive to elys, issipte lesser power, fster in spee n re lokless, re require. Clok-less or synhronous iruits [1], [] re otine y repling the lok y the itionl ontrol iruits. However, utomtion tools n speifition lnguges re missing for esign of suh iruits. Digitl iruits re esigne n implemente to stisfy the given speifitions. Corret working n require performne ep on ertin ftors relte to the physil prmeters of the implementtion tehnology, suh s with of trnsistors, elys in the interonnets, pitnes, metl lyers et. Dely-Insensitivity is the property of elivering orret funtioning, inepent of the physil elys in wires n gtes. Suh iruits n e esrie using proess lgeri lnguge lle Dely Insensitive Sequentil roesses (DIS) []. Null Conventionl Logi [4] [6] is ely-insensitive iruit implementtion methoology tht lims to synthesise DI iruits. The term NCL is erive from the notion of sene of t using speil null (not t) vlue. We ttempt to provie lnguge front- to synthesise NCL using DIS. The similrities etween the nture of H.K. Kpoor, Inin Institute of Tehnology Guwhti, Ini, e-mil: hemngee@iitg.ernet.in A. Asthn, Memer IEEE, Ini, Ini, e-mil: hinvsthn@ieee.org T. Krilvičius, Blti Avne Tehnologies Institute, Vilnius, Lithuni, e-mil: t.krilviius@gmil.om W. Zeng, J. M n K.L. Mn, Dept. of Computer Siene n Softwre Engineering, Xi n Jiotong-Liverpool University (XJTLU), e-mils: wenjie.zeng07@stuent.jtlu.eu.n, jieming84@gmil.om n k.mn@ jtlu.eu.n the speifitions from the ltter, n the si uiling loks from the former, provie n opportunity to ientify n lternte synthesis pth. The pper is orgnize s follows. The net setion isusses relte work. In Setion DIS n its synt re presente. Setion 4 isusses NCL n Setion 5 gives the trnsltion metho. Cse stuies performe using the given tehnique re shown in Setion 6. Finlly we rw some onlusions in Setion 7. II. RELATED WORK Currently, the lnguge se synthesis of synhronous iruits uses CS [7] se formlisms. The relte work inlues lnguges like CH [8], Tngrm [9], Bls [10], DI-Alger [11] n DIS []. Grphil moelling tehniques inlue etri nets tht use the tool etrify [1] for synthesis. There hve lso een ttempts to use inustry-stnr HDLs like Verilog n VHDL to synthesise synhronous iruits. However, these lnguges lk the si onstruts require for synhronous ehviour, therefore speil pkges shoul to e e to the lnguge. VHDL is urrently use to synthesis NCL-se iruits. Verilog long with the tool pipefitter hs lso een pplie to synthesis of lrge iruits inluing n synhronous DLX pipeline proessors [1]. III. DIS DIS, vrint of DI-Alger [11] n CS [7], is struture prllel progrmming lnguge speifilly esigne for ehviourl speifition of ely insensitive iruits. Using DIS, eveloper n speify the ehviour of DI iruit in terms of proesses. It llows esigner to speify ehviour of synhronous logi loks n investigte iverse hnshke protools. Gte net-list n e otine from DIS speifitions using tools ipn [14] n petrify [1]. Former is use to trnslte the DIS epressions into etri net, n the lter synthesises the iruit from the etri net speifition. A. Lnguge Synt Behviour of iruit is esrie s proess in DIS. Eh proess is ssoite with n input n output lphet n is ple of soring inputs n emitting outputs. The lnguge synt is efine s follows: pro :=vr stop skip error urst pro ; pro pro or pro pro pr pro foreveropro selet lt-set lt-set ::=[urst [thenpro]{lturst [thenpro]}]
2 urst ::= siglist1/siglist is n innput n output urst, where the set of input events (siglist 1 ) must our efore the output events (siglist ) re generte. siglist is set of signls (possily empty), speifie s siglist ::= sig{, sig} where enotes n empty list n signl nmes re given in omm-seprte list. A proess n e ientifie y using proess vrile. Behviours like stop n error re use to speify proesses tht will eventully iverge (o nything whtsoever). A skip oes not perform ny tion n termintes immeitely. It n lso e written s skip = /. A gure hoie ehviour n e speifie using n lt set epression. The hoies re gure y the urst epression. The proesses whose gur is stisfie re hosen for eeution. Continuous eeution is provie y the forever onstrut. The or opertor speifies non-eterministi hoie etween two proesses. roesses n e ompose sequentilly ; Q n in prllel pr Q. For two proesses n Q with input lphetsi ni Q n output lphets O n O Q when ompose in prllel, must stisfy lphet restritions I I Q = n O O Q =. In other wors, they shoul not generte the sme outputs n nnot shre inputs. However, output from one proess n e input to the other proess in the omposition. Suh signls ((I O Q ) (I Q O )) re lle internl signls n re not oservle from the environment. The ehviour is ely-insensitive, hene every trnsition on wire must e knowlege efore nother trnsition is sent on tht sme wire, euse two onseutive trnsitions on the sme wire my superimpose on eh other leing to the trnsmission interferene. I.e., pulses nnot e sfely trnsmitte. One set of input vlues les to one set of output vlues. The finl genertion of output n e esily etete y using ompletion etetion iruit. To re new set of input vlues, previously generte outputs re flushe y mking ll the inputs NULL. I N U T S Fig.. A 1 B C D E resenttion (vlition) ounries for input vriles Fig. shows onnetion of NCL gtes (1-11) forming multi-level logi implementtion. A, B, C, D n E re the logil ounries for the representtion of signl. The finl set of generte outputs (t the ounry E) is vli iff ll the outputs of ounry D re vli, n so on. Following the hin, it is esy to see tht ll the output elements n e generte only when ll the inputs hve rrive [17]. Input Wvefront Bsi of NCL gte 7 8 Output Wvefront O U T U T S / ; / ; = / ; / ; error / ; / ; = error Fig.. Digrm for si NCL gte Fig. 1. IV. NULL CONVENTIONAL LOGIC N t wvefront D null wvefront null wvefront null wvefront Wvefronts in t flow N t wvefront Null onventionl logi (NCL) [4], [15], [16] is evition from the onventionl oolen systems where the vlue of the signl itself is use to show its rrivl/presene/vliity. Thus eh vrile in the epression hs two vlues: () DATA (initing the vlue s well s vliity) n () NULL (initing sene of t). DATA n e n strt set of vlues. Use of NULL vlue for vrile gives this system the nme Null Conventionl Logi (NCL). As the vriles represent their own presene, the vliity of the outputs is esily etermine, therefore is not require to ompute the stilise output genertion time. It reues the uren of estimting the timing requirements n strengthens the logil struture of the system [6]. There re two oneptul flows for signls in n NCL implementtion: the t-wvefront n the flow of NULL items (to ler ll sttes) lle the null-wvefront, fig. 1. D A si NCL gte is shown in fig.. It hs three inputs n threshol of two, hene -of- NCL gte. The numer insie the gte enotes it s threshol. As follows from the esription, to get logil 1 in output t lest two out of three inputs shoul hve vlue 1, e.g. let, n e t he inputs n z e n output, then the gte represents logil eqution Output = To reset the output to 0, ll the inputs must go to 0 irrespetive of the threshol. Until ll the inputs re reset the gte hols the previous stte. Note tht n N-of-N NCL gte is equivlent to n N input C-element [18]. Fig. 4. V. MAING DIS EXRESSIONS TO NCL, /, ;,, /, e ;,,, / e, f ; 4,,,, e / f, g ;,,,, e, f / g, h ; 5 6 Burst with N ( N 6) inputs n two outputs
3 ) Burst epression: s isusse erlier, DIS urst n e iretly mppe to n NCL gte. Further optimistions n e performe on the implementtion to tke re of threshol limittions n to reue the overll gte ount. An input-output urst in DIS mens tht trnsitions on the inputs must e followe y trnsitions on the output. Eh DIS urst therefore onsists of pir of t n null wvefront in the NCL implementtion. E.g., the urst / in DIS is implemente in NCL to hve t wvefront on signls n ; genertion of t wvefront on strts the null wvefront on ; whih in turn strts the null wvefront on. To trnslte DIS urst hving N inputs n M outputs we use n N-of-N NCL gte with output forke in M ifferent iretions. E.g., urst B =,,/,e wits for ll inputs (,,) to eome vli efore it n generte the output signls (,e). The seon gte in the fig. 4 is similr to the ove urst epression. The other strutures in the figure show emple ursts n their NCL implementtions with input signls rnging from two to si. Fig. 5. Non-frgmente urst. Fig. 6. Frgmente urst. ) Non-eterministi hoie: or Q. To perform it we nee mutul-elusion, whih n e implemente using Mute element, fig. 8. The two requests to the Mute re ssume to e present when the omposition is invoke y the environment. The Mute then ritrrily eies whether to eeute or Q. Fig. 9. Input Burst Input Burst Sequentil Composition of Bursts Q Output Burst Output Burst e) Sequentil omposition: ; Q n e implemente using sequener element. The sequener keeps trk of the orer of eeution. The ompletion of is n input to the sequener, whih in turn enles the eeution of Q. The t n null-wvefronts for shoul e omplete efore those of Q. When Q hs signls istint from, the null-wvefront of n e elye to hppen onurrently with t-wvefront of Q. A generi sequener is shown in fig. 9, the implementtion is given only for smll size urst ompositions (f. Setion VI). CDp CDq In NCL the numer of inputs to gte nnot e more thn si, hene ursts with more thn si inputs re eompose. For emple, the urstb =,,/ is implemente without eomposition s shown in fig. 5, n with eomposition s in fig. 6, using two -of- gte. ) Gure hoie: selet lt-set. The seletion n e one with the help of eision-wit element (esrie in Setion VI). t wvefront ENVIRONMENT t wvefront internl signls Q enles Completion etetion of lst urst in Fig. 10. ENVIRONMENT rllel Composition of Burst Epressions Fig. 7. inputs to A forever proess outputs to environment f) rllel omposition: pr Q. Both proesses re implemente using their respetive proess onstruts n they n run onurrently. The internl signls of eh re ross-onnete, fig. 10. ) Infinite repetition: forever o pro is require to epress ontinuously running hrwre. The proess is implemente using other si trnsltion rules. The ompletion of the lst urst in it will enle the first urst. 0 1 VI. CASE STUDIES 0 Merge 1 1 Fig. 8. ENVIRONMENT r1 r MUTEX ELEMENT en enq Q r1, r initilty enle en, enq : enle, Q Non-eterministi hoie mong proesses () Norml MERGE element Fig. 11. Moel of Merge element using NCL gtes () MERGE using NCL gte A Merge [19] hs two input terminls, n one output terminl. It merges signls on the input terminls to the output terminl. Input n output signls lternte. The environment hs to gurntee mutul elusion on the inputs. merge = foreveroselet 0/ lt 1/
4 The merge elements wits for n tivity on the inputs n propgtes the output. As tivity over single input element is enough to generte the output n the environment gurntees mutul elusion of input elements, the merge element n e forme using 1-of- NCL gte, fig. 11. A generlise K-merge K-merge = forever o selet0/ lt 1/ lt... lt k/ n e implemente using 1-of-K NCL gte. Fig. 1. JOIN () Norml JOIN element Moel of Join element using NCL gtes () JOIN element using NCL gte Join [19] hs two input terminls n one output terminl. It wits until input signls on oth input terminls rrive, fter whih it proues signl on its output terminl. join = forevero,/ As join element wits for oth inputs to rrive, we n use -of- NCL gte for its implementtion, fig. 1. Similrly, K-join element n e synthesise using K-of-K NCL gte. DECISION WAIT ELEMENT () Blok igrm of Deision Wit element Fig Moel of 1 Deision wit element 0 1 () Deision Wit element using NCL gtes 1 Deision Wit hs three inputs (0, 1,n ), n two outputs (0, 1). It wits for signl on one of the i inputs n signl on, efore it outputs on i. The environment hs to gurntee mutul elusion on the - inputs (shown y erroneous ehviour fter oth 0 n 1 rrive). Eh gur is implemente using n pproprite threshol NCL gte, see fig. 1. eision-wit = forever o sel 0,/0 lt 1,/1 lt 0,1/ then error 0 1 This emple shows sequentil omposition of two urst epressions. Completion of the first urst / triggers the eginning of the seon urst /. We nee the onept of stte to sequene the ursts. The implementtion is shown in fig. 14. The first gte is enle initilly n when rrives, the output is generte. It enles the seon gte n isles the first gte enling the reeption of n genertion of. sequener = forevero/ ; / Note tht in the given implementtion, the t wvefront on / hppens efore the t wvefront on / n the null wvefront on / hppens onurrently with the t wvefront of /. It eomes limittion when we ompose urst using ommon signls. For suh ses we nee to omplete the null-wvefront of the first urst efore the t wvefront of the seon n egin. It n e implemente with using stte vriles s in the toggle element Fig. 15. T () A Toggle Element () Toggle Element using NCL gtes Moel for Toggle Element se on NCL gtes Toggle [19] hs one input () n two outputs ( n ). Eh input signl proues one output signl. Input n output signls lternte. Signls on the output lso lternte, first on then on, et. toggle = forevero/ ; / As mentione, we nee stte vrile to implement suh sequentil omposition, see fig. 15. The stte vrile is require euse, fter the t-null wvefronts on / re over, the iruit is in the sme stte s it strte, n it hs no wy to istinguish etween the first n the seon. It is lle stte oing onflit in igitl logi [0], [1]. M T 0 1 M Element Deision wit 0 1 Fig. 14. Blok n Internl igrms for Sequener element Fig. 16. Moel for to 4 phse onverter using NCL gtes Fig. 17. Moel of ll element to 4 hse Converter [19] hs two inputs ( n ) n two outputs ( n ). Input n output lternte (together forming pssive hnshke hnnel), s o output n input (together forming n tive hnshke hnnel). Every phses enlose 4 phses. Conv = forever o selet / then
5 selet / then selet / lt /- then error lt /- then error lt /- then error Effetively the ehviour is following to4 phse onverter = forevero/ ; / ; / with the onstrint tht inputsn re mutully elusive. Oserving, we get two sequentil ompositions, viz., /;/ n /;/. The first one, given the onstrint tht n re mutully elusive n e implemente using merge-element. The seon omposition is similr to toggle element. As the two ompositions re onnete, output of one goes s input to the other. The implementtion using merge (M) n toggle (T) is shown in Figure 16, n it is sme s tht given in [19]. A non-ritrting, loking ll-element [19] hs three inputs (0, 1, ) n three outputs (, 0, 1). A signl ppering on either of the i s will proue signl t. The omintion of signl t i n will proue signl t i. It oes not mtter whih of the two input signls rrives first. The environment of the Cll must gurntee mutul elusion of the signls on 0 n 1. The i n signls lternte, the i n i signls lternte, n the n i signls lternte. ll = forever o selet 0/ then selet /0 lt 0/- then error lt 1/ then selet /1 lt 1/- then error lt /- then error The esription puts onstrints tht inputs 0 n 1 re mutully elusive (inite y ivergene fter oth 0 n 1 rrive). The output is generte y either 0 or 1. Hene, we n use merge-element with inputs 0 n 1 to generte. The overll ehviour of Cll is gure hoie implemente y 1 eision-wit (DW) element. The inputs to DW re 0,1, n outputs - 0,1. See this implementtion, mthing one in [19], in fig. 17. Fig. 18. e () VII. ORHAN ATHS f g () Orphn pth, () Confine orphn pth An orphn pth is rnhe off onnetion rrying t to n NCL gte n is not use to proue ny output [6]. When the output of n NCL implementtion trnsitions to omplete DATA stte, it implies tht the input t set is omplete n tht the trnsitions to DATA hve propgte over the effetive pth. There will lso e ineffetive pths rnhing off from this effetive pth tht o not ontriute to the output n therefore re not logilly etermine y the output. These ineffetive pths re lle orphns euse e () f g they hve lost ll of their logil reltions. In the fig. 18, orphn pths re epite y otte lines. A. Ientifying Orphn pths in DIS Orphn pths n e ientifie t point, when prtiulr t wvefront follows two ifferent pths prouing ifferent outputs. In terms of DIS, = forever o selet,,/f lt,,e/g Here DATA wvefronts on n follow two ifferent pths to get mie with other elements n proue vrious elements. Deping on the vilility of other input elements, only one of the split DATA wves will result in n output urst. Other wvefronts on n will remin ineffetive. E.g., if we get DATA wvefront on,,, the iruit will s DATA wvefront on the output f, n the wvefront epite y the otte line (going to the seon gte) eomes orphn. B. Confinement of Orphn pths Though one nnot voi orphn pths in n NCL implementtion, we suggest to onfine n onvert them. Orphn pths stem from the forke pths. By etrting the ommon urst epression, it n e implemente using n etr NCL gte. The output of this etr intermeite gte is neither n input nor n output n n e use s n internl signl. Suh n internl element enotes the presene of ommon input urst s well. E.g., in the ove epression we seprte the ommon input urst,/- n rewrite it: = forever o,/- ; selet /f lt e/g Then we epn it using n internl vrile (): = forever o,/ ; selet,/f lt,e/g Internl vrile represents stey presene of n. One my notie tht gets forke n sent to the seprte ursts; it results into n orphn pth s well. The min ifferene etween n orinry orphn pth n is the following: the ltter is logilly etermine. The ie to generte lso reues the numer of orphn pths signifintly. Element my still ehve s slow orphn ut its impt is reue, euse it nnot get mie with DATA or NULL wvefronts. Those wvefronts re governe y the presene/sene of n. Inste of ppering t the eginning of the epression, the fork is onfine insie the epression n onverte into n internl vrile. The onfinement is illustrte in fig. 18-(). C. Avntge t the lnguge level A slow orphn is not prolem for the orretness, s the output DATA wvefront is generte using other vriles. However, this triling wvefront on the orphn my interfere with the sueeing DATA wvefront in non-eterministi mnner n use unepete glithes. As isusse in [6], there my eist n implementtion, where ll the inputs of n NCL gte re fe y the orphn pths in the iruit. Suh n NCL gte gives out n orphn
6 pth s its output. Though the output of the gte my lso e use y nother gte, hene there must e some seurity mesure restriting the orphn inputs to hnge their stte. By renming the genertion of orphn output s one of the ompletion etetion riteri of the iruit, solves the issue. The DATA wvefront is not llowe to hnge the stte, until onflit mong the orphn pths is not over. Using DIS Our solutions iffers from the one in the erlier works, euse the epressions re in the form of I/O ursts n not s omintionl logi. The ompletion etetion of urst is etermine y the genertion of ll the output elements. Confining the orphn pth within the epression mkes superfluous other ompletion etetion riteri. The internl element generte y the etrte urst epression seems to e similr to the orphn output of [6]. However, ue to the onfinement of the orphn pth, this internl element nees not e epose to the environment, therey reuing the ompleity in the ompletion etetion iruitry. Even fter this frgmente implementtion, the input n output elements re iretly relte to eh other s speifie y the DIS epression, unwre of the ft tht the ursts were frgmente efore their tul implementtion. VIII. CONCLUSION The pper presente n ttempt to fin n lterntive synthesis pth for NCL se implementtions. The trget implementtion eing ely-insensitive the lnguge hosen ws DIS. The si onstrut of the lnguge, n inputoutput urst, ws foun to e iretly implementle using N-of-M NCL gtes. The min ie of synthesis is to onstrut the si uiling loks of DI [] using NCL gtes. Then ientify these in the DIS lnguge n mp them ppropritely. While trnslting given ehviour, wht remins is to ientify suh si loks in the lnguge n mp them to NCL implementtions. However, the onept of t followe y null wvefront forms ruil ftor. Cre nees to e tken to mke sure tht eh t wvefront is omplete in orer to generte the orret outputs n lso the omputtionl lok goes through null wvefront efore nother omputtion n egin. This les to the stuy of orphn pths [6], pths not use y the iruit ut still rrying t wvefronts. The implition of hysteresis n vrile threshol on the implementtion lso nee to e resse. Issues relte to stte vrile insertion to solve stte oing onflits is nother prolem. This is ue to the ft tht lthough the logi loks n unergo t-null wvefront, the stte vriles nee to e prevente from oing so immeitely (in orer to hol stte). This ontrolle nullifition of stte vriles remins to e solve. The pper emonstrte this with smll emple of toggle element whih h only one stte oing onflit. However, generi metho of stte vrile insertion requires eeper stuy of the wvefronts n orret ientifition of ples to insert stte vriles. Although mny issues still remin to e resse, this initil stuy hs given onfiene in esigning suh n lterntive synthesis pth. This is positive step s urrently there is no pure synhronous lnguge front- to NCL synthesis. Automtion of the omplete synthesis lso nees to e elt with. REFERENCES [1] S. Huk, Asynhronous esign methoologies : An overview, roeeings of the IEEE, vol. 8, pp. 69 9, Jnury [] J. Sprsø n S. Furer, riniples of Asynhronous Ciruit Design A System respetive. Kluwer Aemi ulishers, 001. [] M. B. Josephs n D.. Furey, A progrmming pproh to the esign of synhronous logi loks, in Conurreny n Hrwre Design, Avnes in etri Nets, ser. Leture Notes in Computer Siene, vol Springer, 00, pp [4] K. M. Fnt n S. A. Brnt, Null onvention logi : A omplete n onsistent logi for synhronous igitl iruit synthesis, in ASA. IEEE Computer Soiety, 1996, pp [Online]. Aville: [5] K. Fnt n S. Brnt, Null onvention logi, [Online]. Aville: iteseer.ist.psu.eu/fnt94null.html [6] F. K. M., Logilly Determine Design Clokless System Design with Null Conventionl Logi. New Jersey: Wiley Intersiene, 005. [7] C. Hore, Communiting sequentil proesses, Comm. ACM, vol. 1, no. 8, pp , ug [8] A. J. Mrtin, rogrmming in VLSI: From Communiting roesses to Self-time VLSI Ciruits, in roeeings of UT Yer of rogrmming Institute on Conurrent rogrmming. Aison-Wesley, Mrh [9] K. v. Berkel, Hnshke Ciruits - An Asynhronous rhiteture for VLSI progrmming. Cmrige University ress, 199. [10] A. Brsley n D. Ewrs, Compiling the Lnguge Bls to Dely-insensitive Hrwre, Hrwre Desription Lnguges n their Applitions, pp , April [11] M. B. Josephs n J. T. Uing, An overview of DI lger. in 6th Hwii Int. Conferene on System Siene (HICSS 199), JAN 199, pp [1] J. Cortell, M. Kishinevsky, A. Konrtyev, L. Lvgno, n A. Ykovlev, etrify: A Tool for Mnipulting Conurrent Speifitions n Synthesis of Asynhronous Controllers, IEICE Trnstions on Informtion n Systems, vol., no. E80-D, pp. 15 5, [1] M. Ame, I. Blunno, n C.. Sotiriou, Automting the Design of n Asynhronous DLX Miroproessor, in roeeings of the 40th Design Automtion Conferene (DAC), ACM, 00, pp [14] D. Furey n M. B. Josephs, Asynhronous iruit esign vi utomte petri net genertion, 00. [Online]. Aville: uk/ furey/petrinet omintors.pf [15] M. Ligthrt, K. Fnt, R. Smith, A. Tuin, n A. Konrtyev, Asynhronous esign using ommeril HDL synthesis tools, in ASYNC. IEEE Computer Soiety, 000, p [16] S. K. Bnpti n S. C. Smith, Design n hrteriztion of NULL onvention rithmeti logi units, in roeeings of the Interntionl Conferene on VLSI, VLSI 0, June - 6, 00, Ls Vegs, Nev, USA, H. R. Arni n L. T. Yng, Es. CSREA ress, 00, pp [17] C. L. Seitz, System Timing, in Introution to VLSI Systems, Me n Conwy, Es. Aison-Wesley, 1980, h. 7. [18] I. E. Sutherln, Miropipelines. Commun. ACM, vol., no. 6, pp , [19] T. Verhoeff, Enylopei of ely-insensitive systems (EDIS), eis/eis.html, Dept. of Mth. n C.S., Einhoven Univ. of Tehnology. [0] J. Cortell, M. Kishinevsky, A. Konrtyev, L. Lvgno, n A. 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