A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems

Transcription

1 A Low-Complexity -Point Mixed-Radix FFT Proessor for MB-OFM UWB Systems Sang-In Cho and Kyu-Min Kang In this paper, we present a fast Fourier transform (FFT) proessor with four parallel data paths for multiband orthogonal frequeny-division multiplexing ultrawideband systems. The proposed -point FFT proessor employs both a modified radix- algorithm and a radix- algorithm to signifiantly redue the numbers of omplex onstant multipliers and omplex booth multipliers. It also employs substruture-sharing multipliation units instead of onstant multipliers to effiiently ondut multipliation operations with only addition and shift operations. The proposed FFT proessor is implemented and tested using. µm CMOS tehnology with a supply voltage of. V. The hardware- effiient -point FFT proessor with four data streams an support a data proessing rate of up to Gsample/s while onsuming mw. The implementation results show that the proposed -point mixed-radix FFT arhiteture signifiantly redues the hardware ost and power onsumption in omparison to existing -point FFT arhitetures. Keywords: Fast Fourier transform (FFT), mixed-radix, omplex onstant multiplier (CCM), substruture-sharing multipliation unit (SMU), ultra-wideband (UWB). Manusript reeived Apr., 9; revised Sept., 9; aepted ov. 9, 9. This work was supported by the IT R& program of KCC/KEIT [A Study on the Radio Requirements of Coexistene for ynami Spetrum Aess]. Sang-In Cho (phone: , siho@etri.re.kr) and Kyu-Min Kang (orresponding author, phone: , kmkang@etri.re.kr) are with the Broadasting & Teleommuniations Convergene Researh Laboratory, ETRI, aejeon, Rep. of Korea. doi:./etrij..9. I. Introdution Ultra-wideband (UWB) systems supporting various data rates from tens of Mb/s to hundreds of Mb/s are very suitable for appliation to short range wireless ommuniations beause they an share the frequeny band with existing narrowband systems []-[]. One of the andidate shemes for the highspeed UWB physial layer (PHY) is a multiband orthogonal frequeny-division multiplexing (MB-OFM) sheme. One OFM symbol in the MB-OFM UWB system onsists of subarriers and 7 zero samples. The subarriers are omposed of data subarriers, pilot subarriers, guard subarriers, and 6 null subarriers. Therefore, the fast Fourier transform (FFT) proessor of the MB-OFM UWB system onduts a -point FFT operation, where the sampling frequeny is 5 MHz and the subarrier frequeny spaing is.5 MHz. Although the FFT period is. ns, the -point FFT operation is allowed to be performed within.5 ns beause a length-7 zero-padded suffix duration (7. ns) is added in one OFM symbol []. Many FFT arhitetures have been developed over the last three deades. Reently, several parallel data-path pipelined FFT proessors for UWB appliations have been developed []-[9]. A -point mixed-radix FFT algorithm with a fourdata-path approah, inluding radix- and radix- FFT algorithms, was presented in [] to redue the number of omplex multipliations. When the -point FFT algorithm is broken into three suessive FFT algorithms, that is, one radix- FFT algorithm and two radix- FFT algorithms, the hardware ost of omplex multipliers in the mixed-radix multipath delay feedbak (MRMF) FFT proessor omes to be only.% of that in a split-radix multipath delay ommutator (SRMC) FFT proessor [], []. By modifying ETRI Journal, Volume, umber, February Sang-In Cho et al.

2 the approah proposed by K. Maharatna and others in [], Y.W. Lin and others in [] effiiently realized nontrivial omplex multipliers, at the fourth stage among seven stages for the -point FFT operation, with nine hard-wired onstant units. Chakraborty and others proposed a hardware-effiient omplex onstant multiplier (CCM) struture in [7]. Although alternative FFT arhitetures for UWB appliations have also been disussed in [] and [9], the hardware ost is still high due to several nontrivial omplex multipliations needed at two stages for the -point FFT operation. To further redue the hardware omplexity and power onsumption, Cho and others reently presented a four-parallel data-path -point mixed-radix deimation-in-frequeny (IF) FFT proessor operating at over MHz in [5]. In the proposed FFT proessor, nontrivial omplex multipliation operations are only needed at the fourth stage by breaking up the -point FFT algorithm into two FFT algorithms, namely, radix- FFT and radix- FFT algorithms. Beause a relatively large number of onstant multipliers are required to implement twiddle fators (TFs) at the end of eah stage in a onventional radix- FFT arhiteture [], a modified radix- FFT struture without onstant multipliers at the third stage is presented. However, the proposed FFT arhiteture was not fully analyzed in [5]. There were also mistakes in the figures of [5]. In this paper, we present mathematial formulation and analysis of the proposed - point mixed-radix FFT algorithm. etailed harateristis of the proposed FFT proessor are also analyzed. The amended figures of the signal flow graph, butterfly units (BUs), and CCMs of the proposed FFT proessor are given. We ompare the hardware omplexity of the proposed FFT proessor and several existing -point FFT arhitetures with four parallel data paths. Multipliation units using a substruture-sharing sheme are additionally suggested to effiiently implement the onstant oeffiient multipliers with shift operations and additions [], []. The organization of this paper is as follows. The mathematial formulations of the -point mixed-radix FFT algorithm are given in setion II. In setion III, we desribe the proposed FFT arhiteture with four parallel data paths. The hardware omplexity of the proposed FFT arhiteture is ompared with that of the existing -point FFT arhitetures for MB-OFM UWB systems in setion IV. Conlusions are given in setion V. II. -Point Mixed-Radix FFT Algorithm Given a length- omplex input sequene x(n), its disrete Fourier transform (FT) an be desribed as nk X( k) = x( n) W, k =,,,, () n= nk j( nk / ) where W = e is the TF, k is a frequeny index, and n is a time index. As reported in many works []-[], a hardware-effiient mixed-radix FFT algorithm should be employed to redue the number of omplex multipliations beause the -point FFT is not at a power of or. In this setion, we present a modified radix- IF FFT algorithm for stages to and a radix- IF FFT algorithm for stages 5 to 7.. Modified Radix- FFT Algorithm To derive a modified radix- IF FFT algorithm, onsider the first steps of the deomposition of an -point FFT (=). By a five-dimensional linear index map, indies k and n are denoted by k = k+ k + k + k + 6 k5, k, k, k, k =,; k5 =,,, 6 n= n+ n + n + n + n5, 6 n, n, n, n =,; n5 =,,. 6 Using () and (), () an be rewritten as X( k + k + k + k + 6 k ) 5 6 x n n n n n 5 n5= n= n= n= n= 6 ( n+ n+ n+ n+ n5)( k+ k+ k+ k+ 6 k5) W 6 6 n5( k+ k+ k+ k) n5k5 H /6( n5, k, k, k, k ) W W /6. n5 = = ( ) = () After some straightforward alulation, we have the fourth butterfly unit as H ( n ) = H ( n, k, k, k, k ) /6 5 /6 5 ( k + k + k ) k = H/ n5 + W6 H/ n5 + W () () ( ) ( ), 6 (5) where the third butterfly unit H / (n), the seond butterfly unit H / (n), and the first butterfly unit H / (n) are obtained by H/ ( n) = H/( n, k, k, k) ( k+ k) k = H/ ( n) + W H/( n+ ) W, (6) Sang-In Cho et al. ETRI Journal, Volume, umber, February

3 H/ ( n) = H/( n, k, k) = H ( n) + W H ( n+ ) W, k k / / TF for stage k H/ ( n) = H/( n, k) = x( n) + x( n+ ) W. () In the onventional radix- FFT arhiteture [], a relatively large number of multipliers are needed to implement ( k k k) the TFs, W + + 6, at the end of the third stage. To effetively eliminate multipliers in the third stage of the onventional radix- FFT arhiteture, we move some parts, ( k k) W + 6, of the TFs at the end of the third stage to the end of the seond stage. Then, the forth butterfly unit beomes k k H/6( n5 ) = H /( n5 ) + W H /( n5 + ) W, (9) 6 TF for stage where the third butterfly unit H /( n5) is expressed as n ( k k) /6 + /( 5) = 6 TF for stage H n W H n + W H n+ W ( k + k ) k / / TF for stage ( ) ( ). (7) () ote that is the floor funtion, whih returns the largest integer less than or equal to its argument value.. Radix- FFT Algorithm In this subsetion, we further deompose the butterfly of radix- into three stages by adopting a radix- FFT algorithm. Let G/6( n5 ) = G/6( n5, k, k, k, k) n5( k+ k+ k+ k) = H /6( n5 ) W, () and TF for stage k = k + k + k, k, k, k =,, () n = n + n + n, n, n, n =,. () Using ()-(), () an be rewritten as X ( k + k + k + k + 6k + k + 6 k ) G /6(n5 n6 n7 ) n7= n6= n5= (n5+ n6+ n7)( k5+ k6+ k7) W ( k5+ k6) k7 G/6 () W G/6() W, TF for stage 6 = + + = + () where G/6 ( n) = G/6( n, k5, k6) = G ( n) + W G ( n+ ) W,(5) k5 k6 / / 6 TF for stage 5 G/ ( n) = G/( n, k5) k5 = G/6 ( n) + G/6( n+ ) W. (6) We break up the -point FT into a 6-point FT and an - point FT, where the 6-point and -point FTs are implemented by applying the modified radix- FFT algorithm and radix- FFT algorithm, respetively. ote that the inverse FFT (IFFT) of a length- omplex sequene x(n) an be obtained by * * nk. (7) k = xn ( ) = X ( kw ) The IFFT an be performed by taking the omplex onjugate of the input data first and then the outgoing data without hanging any oeffiients in the original FFT algorithm []. III. Four-Parallel ata-path FFT Arhiteture. Proposed Four-Parallel ata-path Mixed-Radix FFT Arhiteture Beause the sampling rate of the analog-to-digital (A/) onverter is 5 MHz in the MB-OFM UWB system, it is not easy to design a reeiver struture with a single data-path using urrent CMOS proess tehnologies. A four-parallel data-path reeiver struture inluding an FFT blok and a Viterbi deoder an be onsidered to limit the system lok of the baseband modem ore to a maximum of MHz for pratial VLSI implementation [5], [6]. In this paper, we propose a hardware-effiient -point mixed-radix FFT arhiteture with four data paths to meet the high-speed requirements. The signal flow graph of the proposed fourparallel data-path -point FFT proessor is shown in Fig., where the input sequene is broken into four parallel data streams. The order of the four parallel input sequenes of the proposed FFT proessor is x(m), x(m+), x(m+), and x(m+), where m =,,,. The radix- butterfly unit is simplified as shown in Fig.. Figure shows a blok diagram of the proposed four-parallel data-path -point FFT proessor. The proposed FFT arhiteture onsists of butterfly units (BU, BU, and BU), omplex onstant multipliers (CCM, CCM, and CCM), omplex booth multipliers ETRI Journal, Volume, umber, February Sang-In Cho et al.

4 Modified radix- Radix- x() x() x() x(6) x() x() x() x() x(6) x() x() x() x(5) x(56) x(6) x(6) x(6) x(7) x(76) x() x() x() x(9) x(96) x() x() x() x() x(6) x() x() x() x() x(5) x(9) x() x(7) x() x(5) x(9) x() x(7) x() x(5) x(9) x(5) x(57) x(6) x(65) x(69) x(7) x(77) x() x(5) x(9) x(9) x(97) x() x(5) x(9) x() x(7) x() x(5) x() x(6) x() x() x() x() x(6) x() x() x() x() x(6) x(5) x(5) x(5) x(6) x(66) x(7) x(7) x(7) x() x(6) x(9) x(9) x(9) x() x(6) x() x() x() x() x(6) x() x(7) x() x(5) x(9) x() x(7) x() x(5) x(9) x() x(7) x(5) x(55) x(59) x(6) x(67) x(7) x(75) x(79) x() x(7) x(9) x(95) x(99) x() x(7) x() x(5) x(9) x() x(7) W(6) W(6) -W(6) -W(6) W(6) W(6) -W(6) -W(6) W(6) W(6) -W(6) -W(6) W(6) W(6) -W(6) -W(6) - - W(6) W(6) -W(6) -W(6) W(6) W(6) -W(6) -W(6) - - W(6) W(6) -W(6) -W(6) W(6) W(6) -W(6) -W(6) - - W(6) -W(6) - - W() -W() W() -W() W() -W() W() -W() - W() W() W() -W() W() W() W() - W(6) W() W() -W(6) W() W(5) W(9) -W() W(5) W(5) W() -W() W() W(5) W() -W() W(7) -W() W(5) -W() W(6) -W(6) - W() W() W() -W() W() -W() W() -W() W() W(6) -W() W() W() W(6) -W() W(6) W() -W() W() -W() W(5) -W(6) - W() W() -W() -W() W(6) W() W() -W(6) -W() -W() j-w() W() W(7) W(7) -W() W(5) -W() -W(7) -W(7) W(9) W() -W() -W() W() -W(7) -W() j-w(9) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) W(6) -W(6) X() X(6) X() X(96) X(6) X() X() X() X() X(7) X() X() X() X() X(56) X() X() X(6) X(6) X() X() X() X(5) X(6) X() X(76) X() X() X() X(9) X(6) X() X() X(66) X() X(9) X() X() X(5) X() X() X(7) X() X(6) X(6) X(9) X(5) X() X(6) X(7) X() X() X() X(6) X(5) X() X() X(7) X(6) X() X() X(9) X(6) X(6) X() X(65) X() X(97) X(7) X() X(9) X() X(9) X(7) X() X(5) X(5) X(9) X(57) X() X(5) X(69) X(7) X() X() X(5) X(5) X(7) X() X(77) X(5) X(9) X(9) X(9) X(6) X(5) X() X(67) X(5) X(99) X(9) X() X(5) X(5) X() X(75) X() X(7) X(7) X(9) X(59) X() X(7) X(7) X(9) X() X() X(7) X(55) X(9) X(5) X(79) X(7) X() X() X(95) X(6) X(7) Stage Stage Stage Stage Stage 5 Stage 6 Stage 7 W(m) denotes W m for m=,,,. Fig.. Signal flow graph of the proposed four-parallel data-path -point mixed-radix FFT proessor. In In Out Out In In : omplement operation Fig.. Blok diagram of the radix- butterfly unit. + + Out Out (CBMs), and registers [5], [7]. As disussed in setion II, the proposed FFT arhiteture is based on both the modified radix- and the radix- IF FFT algorithms in order to redue the number of multipliers. The proposed FFT arhiteture atually requires multipliers in three stages, namely, stages,, and 6. The other stages performing j multipliation arithmeti an be implemented by simply exhanging the imaginary value with the omplement of the real value without atual multipliation operation (see Fig. (b)).. Butterfly Units The proposed FFT arhiteture employs three kinds of Sang-In Cho et al. ETRI Journal, Volume, umber, February

5 Pipeline Modified radix- Radix- x()x()x() 6 BU 6 BU TF CCM TF BU BU TF CBM TF BU BU k 5 W X()X(6)X() BU X(7)X()X(6) x(9)x(5)x() BU BU CCM BU BU CBM BU CCM x()x(6)x() 6 BU BU TF CCM BU BU TF CBM BU x()x(7)x() k 6 TF TF j W X()X()X() 5 BU BU BU BU BU BU BU CCM CBM CCM X()X()X(96) Stage Stage Stage Stage Stage 5 Stage 6 Stage 7 BU BU: Butterfly units (Type I III) CCM CCM: Complex onstant multipliers (Type I III) CBM: Complex booth multiplier W ( k k)( k k) TF (Twiddle fator for stage ): W n5( k k k k) TF (Twiddle fator for stage ): Fig.. Blok diagram of the proposed four-parallel data-path -point mixed-radix FFT proessor. butterfly units (BU, BU, and BU). The butterfly units perform omplex addition and omplex subtration with the two omplex data inputs as shown in Figs. (a) to (). A omplex input from the first-in-first-out (FIFO) buffer and an inoming omplex input are utilized to ondut omplex addition and omplex subtration in the BU of Fig. (a). One of the two omplex outputs in the BU is stored in the FIFO buffer and the other output is passed to the next stage. The BU in Fig. (b) is onstruted by adding a j multipliation unit at the end of the BU. The BU of Fig. () is a onventional radix- butterfly unit.. Complex Constant Multipliers Figures 5(a) to () show three kinds of CCMs used for the proposed FFT arhiteture. Four CCMs are employed in stage, and one CCM and one CCM are employed in stage 6 for the proposed FFT arhiteture, while four nontrivial multipliers (CBMs) are employed in stage. Seven kinds of TFs are needed at the end of stage in the proposed FFT arhiteture. In the CCM of stage, the multipliation operations of the omplex input and the TFs,, W, j, jw, W, W, and W 6 6, 6 are onduted using four ontrol signals. The TF seletion methods in CCM, CCM, and CCM with ontrol signals are given in Table. ote that the seven TFs orrespond to the trigonometri funtions of, j, os( / ), sin( /), and os( / ). CCM is omposed of six real multipliers, three omplement logis, two real adders, and ten multiplexers. In Fig. 5(a), when the twiddle fator is ±W 6 or W, 6 four onstant oeffiient fixed-width multipliers employing os( / ) or sin( / ) are utilized, whereas two onstant oeffiient fixed-width multipliers employing os( / ) are used when the twiddle fator is W or jw. The multipliation output of CCM in Fig. 5(b) is alulated by In { os( k5 / ) jsin( k5 / ) } with k 5 = or. The multipliation output of CCM in Fig. 5() is equivalent to the output of the CCM multiplied by j. As disussed in [], CCM or CCM with -bit word length an be implemented by using ten real adders and two multiplexers. In CCM, six real multipliers an also be implemented using real adders and shift operations. Aordingly, CCM an be implemented using 6 real adders and multiplexers. The CCM arhiteture is approximately three times more omplex than the CCM or CCM arhiteture. In many FFT proessors, multipliers are implemented so that the resultant bit width of the multipliation output remains the same as that of their input. Aordingly, a roundoff error may our by shortening the bit width of the multipliation output. A fixed-width modified booth multiplier in [7] and a fixed-width anoni signed digit multiplier in [] use error ompensation bias shemes to effiiently ompensate for the round-off error. ote that the CBM employed in stage of the proposed FFT arhiteture is omposed of two booth enoders, four partial produt generators, several adders, and a read-only memory (ROM), whih is detailed in [6] and [7]. ETRI Journal, Volume, umber, February Sang-In Cho et al. 5

6 Complex input from buffer Re(In) Im(In) Re(In) Im(In) Complex input from buffer Re(In) Im(In) Re(In) Im(In) Re(In) Im(In) Re(In) Im(In) Complex output to buffer Fig.. Butterfly units: (a) type I (BU), (b) type II (BU), and () type III (BU). BU_sel (a) Complex output to buffer BU_sel (b) () Re(Out) Im(Out) Re(Out) Im(Out) Re(Out) Im(Out) mult. unit Re(Out) Im(Out) Re(Out) Im(Out) BU_sel Re(Out) Im(Out) Table. Seletion of the twiddle fators in CCM, CCM, and CCM. Twiddle fator W j jw W 6 W 6 W 6 CCM_sel CCM_sel x x CCM_sel CCM_sel CCM_sel CCM_sel x denotes don t are value. Re(In) a b a b a= os, b= sin, = os CCM_sel CCM_sel CCM_sel CCM_sel Re(In) Im(In) Re(In) Im(In) (a) = os (b) = os Fig. 5. Complex onstant multipliers: (a) type I (CCM), (b) type II (CCM), and () type III (CCM). CCM_sel CCM_sel. Substruture-Sharing Multipliation Units () Re(Out) Im(Out) Im(Out) Re(Out) Re(Out) Im(Out) Beause six real multipliers are needed to implement CCM as shown in Fig. 5(a), the hardware omplexity of CCM is rather high. In this paper, we propose an enhaned CCM with two substruture-sharing multipliation units (SMUs), shown in Fig. 6, to redue the hardware omplexity of CCM. The SMU of Fig. 6(a) is utilized for the multipliation operations of a real input value and three onstant oeffiients, os( / ), sin( /), and os( / ). These three multipliation operations an be performed by simply using six additions and eight shift operations as shown in Fig. 6(b) if the proposed FFT proessor is implemented with a -bit word length. Figure 7 shows an SMU for the enhaned CCM and CCM. In -bit word 6 Sang-In Cho et al. ETRI Journal, Volume, umber, February

7 Re(In) y SMU ay by y Im(In) y ay SMU a= os, b= sin, = os by y Re(Out) Im(Out) Table. Implementation results of the proposed FFT proessor. Word length bits bits bits SQR (db) 5 7 o. of gates ) 7,5,, Operating speed (MHz) Proessing rate (Msample/s),, 9 Power (mw) ) 9 ) Based on A gates. ) Power onsumption is estimated by Synopsys Power Compiler. CCM_sel CCM_sel CCM_sel CCM_sel Coeffiients eimal a = os.99 b = sin.7 = os.77 y 7 Fig. 6. Enhaned omplex onstant multiplier: (a) enhaned CCM and (b) substruture-sharing multipliation unit (SMU) for the enhaned CCM. z (a) omplement k : k-bit right-shift operation (b) omplement deomposition Coeffiients eimal omplement = os.77 Fig. 7. Substruture-sharing multipliation unit (SMU) for the enhaned CCM and CCM. length implementation, by employing the SMU sheme, CCM or CCM an be designed using only eight adders and two multiplexers. As suh, the hardware omplexity of CCM, CCM, and CCM an be signifiantly redued using the proposed multiplierless multipliation units with the substruture-sharing sheme. z by y ay IV. Implementation Results We determined the internal word length of the proposed FFT proessor using a fixed-point simulation with MATLAB before hardware implementation. After the word length of the proposed FFT proessor was hosen, the FFT arhiteture was modeled in Verilog HL and funtionally verified using a ModelSim simulator. Then, the FFT arhiteture was synthesized with the appropriate time and area onstraints using the Synopsys esign Compiler. ote that the FFT proessor was implemented and tested using Samsung. µm CMOS tehnology and a standard ell library. Table ompares the implementation results of the proposed FFT proessor for three internal word lengths. The signal-toquantization noise ratio (SQR) of the proposed FFT proessor is about db when the word length is bits, and the SQR of the proposed FFT proessor is about 7 db when the word length is bits. The hardware ost and power onsumption of the proposed FFT proessor are inreased as the internal word length inreases, whereas the operation lok Output SR (db) Input SR = db Input SR = db Input SR = 6 db Input SR = db Input SR = db Input SR = db 6 6 Internal word length (bits) Fig.. Output SR for a fixed input SR with various internal word lengths in the proposed FFT proessor. ETRI Journal, Volume, umber, February Sang-In Cho et al. 7

8 Arhiteture o. of omplex registers Proposed FFT proessor Table. Comparison of the proposed and existing -point FFT arhitetures. Modified C.-P. Fan et al. [] Y.W. Lin et al. [] Modified Y. Jung et al. [9] Modified radix-, radix- Radix-, radix- Radix-, radix- Radix-, radix- Radix-, radix- (56.%) o. of nontrivial multipliers ).6 (.%) o. of trivial.97+. multipliers ) (5.9%) o. of omplex adders (%) (56.%) (57.%) +6 (%) (%) (56.%) +.6 (6%) 6 (.%) (%) (%) 6 (5.7%) 6 (.%) (5.%) Z. Wang et al. [] S. Qiao et al. [9] (%) + (%) + (.9%) (%) Radix-, radix-, radix- (67.%) +.6 (6%) (.%) (7.5%) Word length bits - bits - - bits Throughput rate (R: lok rate) R R R R R R ) The nontrivial multiplier is the onventional omplex variable multiplier [], [9]. ) In Table, the number of trivial multipliers is ounted as the number of the omplex onstant multipliers for the twiddle fator and adders in the existing FFT proessors [], []. W or W, whih is realized by shifters speed of the FFT proessor is dereased as shown in Table. Implementation results indiate that the proposed FFT proessor with a -bit internal word length an support a data proessing rate of Gsample/s with a power dissipation of mw at 5 MHz. ote that the throughput rate of the MRMF FFT proessor in [] is up to Gsample/s, and it onsumes 75 mw. The power onsumption of the proposed FFT proessor is approximately 6% lower than that of the MRMF FFT proessor. Figure shows the output signal-tonoise ratio (SR) for the fixed input SR with various internal word lengths in the proposed FFT arhiteture. As the word length is equal to or greater than bits, the output SR is almost saturated, and aordingly, the quantization noise an be nearly ignored. Based on the simulation results, the proposed FFT proessor is implemented with a -bit internal word length. Table ompares the hardware omplexity of the proposed FFT proessor and the existing -point four-parallel datapath FFT arhitetures. Beause the proposed FFT proessor employs modified radix- and radix- FFT arhitetures, nontrivial multipliation operations are only needed at stage. In the proposed FFT arhiteture, four nontrivial omplex multipliers at stage are implemented with the CBMs presented in [7] with 6% of the hardware ost of onventional omplex variable multipliers [], [9]. In addition, the hardware omplexities of CCMs at stage and CCM (or CCM) at stage 6 are signifiantly redued by about % and %, respetively, by employing the proposed SMU arhitetures as ompared to those of onventional CCMs. ote that the trivial multipliation operations of the MAC CPU MAC: medium aess ontrol CPU: entral proessing unit Tx: transmitter Rx: reeiver CE: hannel estimator CPU memory PHY Rx memory FFT/ IFFT PHY Rx ore MAC Memory Viterbi deoder Viterbi deoder Rx CE Syn memory memory Syn PHY Tx ore Memory for debugging Fig. 9. Floor plan of an MB-OFM UWB SoC. AFE PHY Tx memory PHY: physial layer FFT: fast Fourier transform Syn: synhronization blok AFE: analog front-end IFFT: inverse FFT proposed FFT proessor an be performed with approximately 5% of the hardware ost of the onventional radix- FFT proessor in []. The proposed FFT proessor redues the hardware omplexity of omplex multipliers by about % as ompared to the MRMF FFT proessor in []. Table indiates that the proposed -point mixed-radix FFT Sang-In Cho et al. ETRI Journal, Volume, umber, February

9 proessor is a hardware-effiient struture and is therefore suitable for high-speed UWB appliations. Figure 9 shows the floor plan of an MB-OFM UWB system-on-a-hip (SoC) inluding the proposed lowomplexity -point mixed-radix FFT proessor. The implemented MB-OFM UWB SoC onsists of several modules, namely, a medium aess ontrol (MAC), a PHY, an analog front-end (AFE), a entral proessing unit (CPU), and memory bloks. In our implementation, the -point FFT/IFFT blok oupies about 5.% of the silion area of the PHY module. V. Conlusion In this paper, we have proposed a hardware-effiient - point mixed-radix IF FFT proessor with four data paths for MB-OFM UWB systems. We have derived a mixed-radix FFT algorithm omposed of modified radix- FFT and radix- FFT algorithms. By employing the mixed-radix FFT algorithm in the proposed FFT arhiteture, we have signifiantly redued the number of both CCMs and CBMs. In addition, the hardware omplexity of the proposed CCMs for trivial multipliations has been redued by approximately % when ompared to that of the existing CCM strutures by adopting multipliation units using a substruture-sharing sheme. Implementation results have shown that the proposed mixed-radix FFT proessor with -bit internal word length and four parallel data paths an support a data proessing rate of up to. Gsample/s with a power dissipation of mw at 5 MHz using. µm CMOS tehnology. Referenes [] A. Batra et al., esign of a Multiband OFM System for Realisti UWB Channel Environments, IEEE Trans. Mirow. Theory Teh., vol. 5, no. 9, Sept., pp. -. [] K.M. Kang and S.S. Choi, Initial Timing Aquisition for Binary Phase-Shift Keying iret Sequene Ultra-wideband Transmission, ETRI Journal, vol., no., Aug., pp [] W. Abbott et al., Multiband OFM Physial Layer Speifiation, Version. (draft), WiMedia Alliane, Feb. 7. [] Y.W. Lin, H.Y. Liu, and C.Y. Lee, A -GS/s FFT/IFFT Proessor for UWB Appliations, IEEE J. Solid-State Ciruits, vol., no., Aug. 5, pp [5] S.I. Cho, K.M. Kang, and S.S. Choi, Implementation of - Point Fast Fourier Transform Proessor for UWB Systems, Pro. IEEE IWCMC, Aug., pp. -. [6] J.S. Lee et al. A High-Speed, Low-Complexity Radix- FFT Proessor for MB-OFM UWB Systems, Pro. IEEE ISCAS, May 6, pp [7] T.S. Chakraborty and S. Chakrabarti, A Redued Area GSPS FFT esign Using MRMF Arhiteture for UWB Communiation, Pro. IEEE APCCAS, ov., pp. -. [] Z. Wang et al., A ovel FFT Proessor for OFM UWB Systems, Pro. IEEE APCCAS, e. 6, pp [9] S. Qiao et al., An Area and Power Effiient FFT Proessor for UWB Systems, Pro. IEEE WICOM, Sept. 7, pp [] J. Garía, J.A. Mihel, and A.M. Burón, VLSI Configurable elay Commutator for a Pipeline Split Radix FFT Arhiteture, IEEE Trans. Signal Proess., vol. 7, no., ov. 999, pp [] K. Maharatna, E. Grass, and U. Jagdhold, A 6-Point Fourier Transform Chip for High-Speed Wireless LA Appliation Using OFM, IEEE J. Solid-State Ciruits, vol. 9, no., Mar., pp. -9. [] C.-P. Fan, M.-S. Lee, and G.-A. Su, A Low Multiplier and Multipliation Costs 56-Point FFT Implementation with Simplified Radix- SF Arhiteture, Pro. IEEE APCCAS, e. 6, pp [] K.K. Parhi, VLSI igital Signal Proessing Systems: esign and Implementation, ew York; John Wiley & Sons, 999. [] G. Zhong et al., An Energy-Effiient Reonfigurable Angle- Rotator Arhiteture, Pro. IEEE ISCAS, vol., May, pp [5] C.H. Shin et al., A esign and Performane of -Parallel MB- OFM UWB Reeiver, IEICE Trans. Commun., vol. E9-B, no., Mar. 7, pp [6] S.W. Choi, K.M. Kang, and S.S. Choi, A Two-Stage Radix- Viterbi eoder for Multiband OFM UWB Systems, ETRI Journal, vol., no. 6, e., pp [7] K.J. Cho et al., esign of Low-Error Fixed-Width Modified Booth Multiplier, IEEE Trans. VLSI Syst., vol., no. 5, May, pp [] S.M. Kim, J.G. Chung, and K.K. Parhi, Low Error Fixed-Width CS Multiplier with Effiient Sign Extension, IEEE Trans. Ciruits & Systems II, vol. 5, no., e., pp [9] Y. Jung, H. Yoon, and J. Kim, ew Effiient FFT Algorithm and Pipeline Implementation Results for OFM/MT Appliations, IEEE Trans. Consumer Elet., vol. 9, no., Feb., pp. -. Sang-In Cho reeived the BS and MS degrees in information and teleommuniation engineering from Chonbuk ational University, Korea, in 997 and 999, respetively. Sine 999, he has been with the Eletronis and Teleommuniations Researh Institute (ETRI), aejeon, Korea. His urrent researh interests inlude VLSI digital signal proessing and digital ommuniations with appliations to UWB transmission systems. ETRI Journal, Volume, umber, February Sang-In Cho et al. 9

10 Kyu-Min Kang reeived the BS, MS, and Ph degrees in eletroni and eletrial engineering from Pohang University of Siene and Tehnology (POSTECH), Gyeongbuk, Korea, in 997, 999, and, respetively. Sine, he has been with the Eletronis and Teleommuniations Researh Institute (ETRI), aejeon, Korea. His urrent researh interests inlude spetrum engineering, digital signal proessing, and high-speed digital transmission systems. Sang-In Cho et al. ETRI Journal, Volume, umber, February