Additional parameters Parameter Min Typ Max. Units Condition Weight 1 g

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Typical Applications Base Stations Test + Measurement Features Surface Mount Package Reflow Process Compatible Low Phase Noise Build in PLL-Circuit Output range Standard frequencies 1 MHz 185 MHz 1;

1 Typical Applications Base Stations Test + Measurement Features Surface Mount Package Reflow Process Compatible Low Phase Noise Build in PLL-Circuit Output range Standard frequencies 1 MHz 185 MHz 1; 25; 52; 56; 61.44;77.76; 14 MHz ; 153.6; ; 16; 179,2; 184,32 MHz Reference Ordering 5 Input frequency 2 65 MHz ± 1 ppm Signal HCMOS IFH Reference Level Reference Input Impedance V pp kω HCMOS / similar sinewave Output Ordering 5 output frequency MHz Signal HCMOS RFH Load 15. pf Rise and Fall time 5 15 pf 1 to 9 % Duty cycle 4 6 Vs/2 Supply voltage (Vs) Ordering 5 Supply voltage [Standard] VDC SV33 Current consumption 5 ma steady +25 C & 3.3VDC Additional parameters Phase Noise 3-7 dbc/hz 1 122,88 MHz -13 dbc/hz 1 Hz HCMOS -132 dbc/hz 1 khz -147 dbc/hz 1 khz -155 dbc/hz 1 khz -156 dbc/hz 1 MHz Jitter.2 ps 12kHz.. 2MHz Additional parameters Weight 1 g Processing & Packing Handling & processing note Operating temperature range C Operable temperature range Storage temperature range C v page 1 of 5

2 Type G283 Input : Single ended (HCMOS or Sinewave) Output : Single ended HCMOS Height H Pin Length L A1 3, NA Pin Connections Dimensions : mm Description 1 Ref. in High stable input frequency for syncronisation 2 Control Test output of the control voltage for the Only for modul test or observance 3 GND Ground connection. Keep traces physically short and connect immediately to ground plane for best performance 4 RF-OUT RF syncronised output. 5 Lock Detector Test output signal for PLL lock detected. Output High signal PLL in lock Low signal PLL out of lock Only for modul test or observance 6 Vs Power supply pin FX-71-xxxx * VI AYYWW Marking v page 2 of 5

3 Absolute Maximum Ratings Supply voltage (Vs) 6. V Typical Phase Noise and Jitter 122,88MHz; HCMOS output range [Hz] 12kHz to 2MHz Jitter [ps rms] 2ps Block Diagramm Control Reference PLL Circuit Loop Filter Lock Detector v page 3 of 5

Standard Shipping Method A Lage im Gurt Position in tape Pin 1 Abwickelrichtung Unwinding direction X P B K *bei W 24 mm nur untere Lochreihe by W 24 mm only lower hole line Gurtoberseite Tape upper

4 Standard Shipping Method A Lage im Gurt Position in tape Pin 1 Abwickelrichtung Unwinding direction X P B K *bei W 24 mm nur untere Lochreihe by W 24 mm only lower hole line Gurtoberseite Tape upper side Gurtunterseite Tape buttom side Production tolerance complying DIN IEC Enclosure Type Tape width W [mm] Quantity per meter Quantity per reel Dimension P G283 tbd tbd 1 tbd Recommended Reflow Profile Profile Feature Pb-Free Assembly /Sn-Pb Assembly Profile Feature Pb-Free Assembly /Sn-Pb Assembly Average ramp-up rate (T L to Tp) 3 C/second max. Time 25 C to Peak Temperature 8 minutes max. Preheat -Temperature Min Ts min) -Temperature Min Ts max) -Time (min to max) (ts) 15 c 2 c 6-18 seconds Time maintainted above - Temperature (T L) - Time (t L) 217 C 6-15 seconds Ts max to T L - Ramp-up Rate 3 C/second max. Time maintainted above - Temperature (T L) - Time (t L) 217 C 6-15 seconds Time within 5 C of actual Peak Temperature (tp) 2-4 seconds Peak Temperature (Tp) max 26 C Ramp-down Rate 6 C/second max. Note: All temperatures refer to topside of the package, measured on the package body surface. SMD oscillators must be on the top side of the PCB during the reflow process. v page 4 of 5

5 How to Order this Product: Model Input Output Supply Voltage RF Output Package FX-71 SV33 RFH A1 Supply: SV33: 3.3V Signal: RFH: HCMOS v page 5 of 5

Reflow Process Compatible Low Phase Noise Build in PLL-Circuit

Typical Applications Base Stations Features Surface Mount Package Reflow Process Compatible Low Phase Noise Build in PLL-Circuit Output Frequency range Standard frequencies 10 MHz 700 MHz 10; 25; 26; 39.3216;